EDB102 Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER
EDB102S Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere)
EDB102S-T Rectron - 1A,100V,SF SM BRIDGE,50ns,DB-S
EDB103 Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER
EDB103S Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere)
EDB103S-T Rectron - 1A,150V,SF SM BRIDGE,50ns,DB-S
EDB104 Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER
EDB104S Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere)
EDB104S-T Rectron - 1A,200V,SF SM BRIDGE,50ns,DB-S
EDB105 Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER
EDB105S Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere)
EDB105S-T Rectron - 1A,300V,SF SM BRIDGE,50ns,DB-S
EDB106 Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER
EDB106S Rectron - GLASS PASSIVATED SUPER FAST SILICON SURFACE MOUNT BRIDGE RECTIFIER (VOLTAGE RANGE 50 to 400 Volts CURRENT 1.0 Ampere)
EDB106S-T Rectron - 1A,400V,SF SM BRIDGE,50ns,DB-S
EDC002 Micro Electronics - Digit of Display = 8 ; External Dimensions LXW (mm) = 63.50 X 20.32 ; View Area LXW (mm) = 60.70 X 13.46 ; Character Dimensions H (mm) = 10.7 ;
EDC004 Micro Electronics - Digit of Display = 1 ; External Dimensions LXW (mm) = 50.00 X 33.00 ; View Area LXW (mm) = 38.90 X 27.90 ; Character Dimensions H (mm) = 34.5 ;
EDC006 Micro Electronics - Digit of Display = 1 ; External Dimensions LXW (mm) = 76.20 X 55.88 ; View Area LXW (mm) = 65.02 X 50.81 ; Character Dimensions H (mm) = 56.18 ;
EDC031 Micro Electronics - Digit of Display = 6 ; External Dimensions LXW (mm) = 88.00 X 30.00 ; View Area LXW (mm) = 83.00 X 18.00 ; Character Dimensions H (mm) = 15 ;
EDC190 Micro Electronics - Digit of Display = 4 ; External Dimensions LXW (mm) = 50.80 X 30.48 ; View Area LXW (mm) = 45.72 X 17.78 ; Character Dimensions H (mm) = 12.95 ;
EDD1216AASE Elpida - 128m Bits Ddr Sdram (8m Words X 16 Bits)
EDD1216AASE-6B-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AASE-7A-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA Elpida - 128m Bits Ddr Sdram (8m Words X 16 Bits)
EDD1216AATA-5 Elpida - 128m Bits Ddr Sdram (8m Words X 16 Bits, Ddr400)
EDD1216AATA-5B-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
EDD1216AATA-5C-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
EDD1216AATA-6B-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA-7A-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits)
EDD1216AATA-7B-E Elpida - 128M bits DDR SDRAM (8M words x 16 bits)
EDD1232AABH Elpida - 128m Bits Ddr Sdram (4m Words X 32 Bits)
EDD1232AABH-6B-E Elpida - 128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AABH-7A-E Elpida - 128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AAFA Elpida - 128m Bits Ddr Sdram (4m Words X 32 Bits)
EDD1232AAFA-6B-E Elpida - 128M bits DDR SDRAM (4M words x 32 bits)
EDD1232AAFA-7A-E Elpida - 128M bits DDR SDRAM (4M words x 32 bits)
EDD2504AKTA Elpida - 256m Bits Ddr Sdram (64m Words X 4 Bits)
EDD2504AKTA-6B Elpida - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-6B-E Elpida - 256m Bits Ddr Sdram (64m Words X 4 Bits)
EDD2504AKTA-7A Elpida - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-7A-E Elpida - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-7B Elpida - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-7B-E Elpida - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2504AKTA-E Elpida - 256M bits DDR SDRAM (64M words x 4 bits)
EDD2508AETA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2508AETA-5B-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2508AETA-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2508AETA-6B-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2508AETA-7A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2508AKTA-5 Elpida - 256m Bits Ddr Sdram (32m Words X 8 Bits, Ddr400)
EDD2508AKTA-5B Elpida - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2508AKTA-5B-E Elpida - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2508AKTA-5C Elpida - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2508AKTA-5C-E Elpida - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
EDD2508AKTA-5-E Elpida - 256m Bits Ddr Sdram (32m Words X 8 Bits, Ddr400)
EDD2516AETA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2516AETA-5B-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2516AETA-5C-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2516AETA-6B-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD2516AETA-7A-E Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDD5116AFTA Elpida - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
EDS1216AGTA Elpida - * Single pulsed /RAS * Burst read/write operation and burst read/single write operation capability * Byte control by UDQM and LDQM
EDS1216AGTA-6B-E Elpida - * Single pulsed /RAS * Burst read/write operation and burst read/single write operation capability * Byte control by UDQM and LDQM
EDS1216AGTA-75-E Elpida - * Single pulsed /RAS * Burst read/write operation and burst read/single write operation capability * Byte control by UDQM and LDQM
EDS1216CABH Elpida - 128M bits SDRAM (8M words x 16 bits)