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Electronic components list Elpida, page 1



  1. Elpida Memory

    Site: www.elpida.com
    Rate: 887


    Manufacturers


    D4564841G5 - 64m-bit Synchronous Dram 4-bank, Lvttl
  2. E0852E20 - • Double-data-rate architecture; two data transfers perclock cycle• The high-speed data transfer is realized by the 4 bitsprefetch pipelined architecture• Bi-directional differential data strobe (DQS and /DQS)is transmitted/received with data for capturing data atthe receiver• DQS is edge-aligned with data for READs; centeralignedwith data for WRITEs• Differential clock inputs (CK and /CK)• DLL aligns DQ and DQS transitions with CKtransitions
  3. EBD10RD4ABFA -
  4. EBD10RD4ABFA-6B -
  5. EBD10RD4ABFA-7A -
  6. EBD10RD4ABFA-7B -
  7. EBD10RD4ADFA - 1gb Registered Ddr Sdram Dimm (128m Words X72 Bits, 1 Rank)
  8. EBD10RD4ADFA-6B - 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)
  9. EBD10RD4ADFA-6B-E - 1gb Registered Ddr Sdram Dimm (128m Words X72 Bits, 1 Rank)
  10. EBD10RD4ADFA-7A - 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)
  11. EBD10RD4ADFA-7A-E - 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)
  12. EBD10RD4ADFA-7B - 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)
  13. EBD10RD4ADFA-7B-E - 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)
  14. EBD10RD4ADFA-E - 1GB Registered DDR SDRAM DIMM (128M words x72 bits, 1 Rank)
  15. EBD11ED8ABFB - 1gb Unbuffered Ddr Sdram Dimm Ebd11ed8abfb (128m Words x 72 Bits, 2 Banks)
  16. EBD11ED8ABFB-6B - 1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words x 72 bits, 2 Banks)
  17. EBD11ED8ABFB-7A - 1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words x 72 bits, 2 Banks)
  18. EBD11ED8ABFB-7B - 1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words x 72 bits, 2 Banks)
  19. EBD11ED8ADFB - 1gb Unbuffered Ddr Sdram Dimm (128m Words X72 Bits, 2 Ranks)
  20. EBD11ED8ADFB-5 - 1gb Unbuffered Ddr Sdram Dimm (128m Words X72 Bits, 2 Ranks)
  21. EBD11ED8ADFB-5B - 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
  22. EBD11ED8ADFB-5C - 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
  23. EBD11ED8ADFB-6B - 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
  24. EBD11ED8ADFB-7A - 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
  25. EBD11ED8ADFB-7B - 1GB Unbuffered DDR SDRAM DIMM (128M words x72 bits, 2 Ranks)
  26. EBD11UD8ABDA -
  27. EBD11UD8ABDA-6B -
  28. EBD11UD8ABDA-7A -
  29. EBD11UD8ABDA-7B -
  30. EBD11UD8ABFB - 1gb Unbuffered Ddr Sdram Dimm
  31. EBD11UD8ABFB-6B - 1GB Unbuffered DDR SDRAM DIMM
  32. EBD11UD8ABFB-7A - 1GB Unbuffered DDR SDRAM DIMM
  33. EBD11UD8ABFB-7B - 1GB Unbuffered DDR SDRAM DIMM
  34. EBD11UD8ADDA - 1gb Ddr Sdram So-dimm (128m Words X64 Bits, 2 Ranks)
  35. EBD11UD8ADDA-6B - 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
  36. EBD11UD8ADDA-6B-E - 1gb Ddr Sdram So-dimm (128m Words X64 Bits, 2 Ranks)
  37. EBD11UD8ADDA-7A - 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
  38. EBD11UD8ADDA-7A-E - 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
  39. EBD11UD8ADDA-7B - 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
  40. EBD11UD8ADDA-7B-E - 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
  41. EBD11UD8ADDA-E - 1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
  42. EBD11UD8ADFB - 1gb Unbuffered Ddr Sdram Dimm (128m Words X64 Bits, 2 Ranks)
  43. EBD11UD8ADFB-5 - 1gb Unbuffered Ddr Sdram Dimm (128m Words X64 Bits, 2 Ranks)
  44. EBD11UD8ADFB-5B - 1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)
  45. EBD11UD8ADFB-5C - 1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)
  46. EBD11UD8ADFB-6B - 1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)
  47. EBD11UD8ADFB-7A - 1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)
  48. EBD11UD8ADFB-7B - 1GB Unbuffered DDR SDRAM DIMM (128M words x64 bits, 2 Ranks)
  49. EBD21RD4ABNA - 2gb Registered Ddr Sdram Dimm
  50. EBD21RD4ABNA-10 - 2GB Registered DDR SDRAM DIMM
  51. EBD21RD4ABNA-6B -
  52. EBD21RD4ABNA-7A - 2GB Registered DDR SDRAM DIMM
  53. EBD21RD4ABNA-7B - 2GB Registered DDR SDRAM DIMM
  54. EBD21RD4ADNA - 2gb Registered Ddr Sdram Dimm (256m Words X72 Bits, 2 Ranks)
  55. EBD21RD4ADNA-6B - 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)
  56. EBD21RD4ADNA-6B-E - 2gb Registered Ddr Sdram Dimm (256m Words X72 Bits, 2 Ranks)
  57. EBD21RD4ADNA-7A - 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)
  58. EBD21RD4ADNA-7A-E - 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)
  59. EBD21RD4ADNA-7B - 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)
  60. EBD21RD4ADNA-7B-E - 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)
  61. EBD21RD4ADNA-E - 2GB Registered DDR SDRAM DIMM (256M words X72 bits, 2 Ranks)
  62. EBD25EC8AKFA -
  63. EBD25EC8AKFA-5 - 256mb Unbuffered Ddr Sdram Dimm (32m Words X72 Bits, 1 Rank)
  64. EBD25EC8AKFA-5B - 256MB Unbuffered DDR SDRAM DIMM (32M words X72 bits, 1 Rank)
  65. EBD25EC8AKFA-5C - 256MB Unbuffered DDR SDRAM DIMM (32M words X72 bits, 1 Rank)
  66. EBD25UC8AKFA -
  67. EBD25UC8AKFA-5 - 256mb Unbuffered Ddr Sdram Dimm (32m Words X 64 Bits, 1 Rank)
  68. EBD25UC8AKFA-5B - 256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)
  69. EBD25UC8AKFA-5B-E - 256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)
  70. EBD25UC8AKFA-5C - 256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)
  71. EBD25UC8AKFA-5C-E - 256MB Unbuffered DDR SDRAM DIMM (32M words X 64 bits, 1 Rank)
  72. EBD25UC8AKFA-5-E - 256mb Unbuffered Ddr Sdram Dimm (32m Words X 64 Bits, 1 Rank)
  73. EBD26UC6AKSA - 256mb Ddr Sdram So Dimm (32m Words X 64 Bits, 2 Banks)
  74. EBD26UC6AKSA-6B - 256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)
  75. EBD26UC6AKSA-6B-E - 256mb Ddr Sdram So-dimm (32m Words X 64 Bits, 2 Ranks)
  76. EBD26UC6AKSA-7A - 256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)
  77. EBD26UC6AKSA-7A-E - 256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)
  78. EBD26UC6AKSA-7B - 256MB DDR SDRAM SO DIMM (32M words x 64 bits, 2 Banks)
  79. EBD26UC6AKSA-7B-E - 256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)
  80. EBD26UC6AKSA-E - 256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)
  81. EBD51RC4AKFA - 512mb Registered Ddr Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  82. EBD51RC4AKFA-6B - 512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank)
  83. EBD51RC4AKFA-6B-E - 512mb Registered Ddr Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  84. EBD51RC4AKFA-7A - 512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank)
  85. EBD51RC4AKFA-7A-E - 512MB Registered DDR SDRAM DIMM (64M words x 72 bits, 1 Rank)
  86. EBD51RC4AKFA-7B - 512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank)
  87. EBD51RC4AKFA-7B-E - 512MB Registered DDR SDRAM DIMM (64M words x 72 bits, 1 Rank)
  88. EBD51RC4AKFA-E - 512MB Registered DDR SDRAM DIMM (64M words x 72 bits, 1 Rank)
  89. EBD52EC8AKFA -
  90. EBD52EC8AKFA-5 - 512mb Unbuffered Ddr Sdram Dimm (64m Words X 72 Bits, 2 Ranks)
  91. EBD52EC8AKFA-5B - 512MB Unbuffered DDR SDRAM DIMM (64M words x 72 bits, 2 Ranks)
  92. EBD52EC8AKFA-5C - 512MB Unbuffered DDR SDRAM DIMM (64M words x 72 bits, 2 Ranks)
  93. EBD52UC8AKDA - 512mb Ddr Sdram So Dimm (64m Words X 64 Bits, 2 Ranks)
  94. EBD52UC8AKDA-6B - 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)
  95. EBD52UC8AKDA-7A - 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)
  96. EBD52UC8AKDA-7B - 512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)
  97. EBD52UC8AKFA -
  98. EBD52UC8AKFA-5 - 512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)
  99. EBD52UC8AKFA-5B - 512mb Unbuffered Ddr Sdram Dimm (64m Words X 64 Bits, 2 Ranks)
  100. EBD52UC8AKFA-5B-E - 512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)
  101. EBD52UC8AKFA-5C - 512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)
  102. EBD52UC8AKFA-5C-E - 512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)
  103. EBD52UC8AKFA-5-E - 512mb Unbuffered Ddr Sdram Dimm (64m Words X 64 Bits, 2 Ranks)
  104. EBD52UD6ADSA - 512mb Ddr Sdram So-(64m Words X 64 Bits, 2 Ranks)
  105. EBD52UD6ADSA-6B - 512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
  106. EBD52UD6ADSA-6B-E - 512mb Ddr Sdram So-dimm (64m Words X 64 Bits, 2 Ranks)
  107. EBD52UD6ADSA-7A - 512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
  108. EBD52UD6ADSA-7A-E - 512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  109. EBD52UD6ADSA-7B - 512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
  110. EBD52UD6ADSA-7B-E - 512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  111. EBD52UD6ADSA-E - 512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  112. EBE10AD4AGFA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  113. EBE10AD4AGFA-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  114. EBE10AD4AGFA-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  115. EBE10AD4AGFA-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  116. EBE10RD4ABFA - 1gb Registered Ddr2 Sdram Dimm (128m Words X 72 Bits, 1 Rank)
  117. EBE10RD4ABFA-4A -
  118. EBE10RD4ABFA-4A-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  119. EBE10RD4ABFA-4C -
  120. EBE10RD4ABFA-5C -
  121. EBE10RD4ABFA-5C-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  122. EBE10RD4AEFA - 1gb Registered Ddr2 Sdram Dimm (128m Words X 72 Bits, 1 Rank)
  123. EBE10RD4AEFA-4A-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  124. EBE10RD4AEFA-5C-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  125. EBE10RD4AGFA - 1gb Registered Ddr2 Sdram Dimm (128m Words X 72 Bits, 1 Rank)
  126. EBE10RD4AGFA-4A-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  127. EBE10RD4AGFA-5C-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  128. EBE10RD4AGFA-6E-E - 1GB Registered DDR2 SDRAM DIMM (128M words x 72 bits, 1 Rank)
  129. EBE11ED8ABFA - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 72 Bits, 2 Ranks)
  130. EBE11ED8ABFA-4A-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  131. EBE11ED8ABFA-5C-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  132. EBE11ED8AEFA - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 72 Bits, 2 Ranks)
  133. EBE11ED8AEFA-4A-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  134. EBE11ED8AEFA-5C-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  135. EBE11ED8AEFA-6 - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 72 Bits, 2 Ranks)
  136. EBE11ED8AEFA-6E-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  137. EBE11ED8AGFA - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 72 Bits, 2 Ranks)
  138. EBE11ED8AGFA-4A-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  139. EBE11ED8AGFA-5C-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  140. EBE11ED8AGFA-6E-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 72 bits, 2 Ranks)
  141. EBE11UD8ABFA - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
  142. EBE11UD8ABFA-4A -
  143. EBE11UD8ABFA-4A-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  144. EBE11UD8ABFA-4C -
  145. EBE11UD8ABFA-5C -
  146. EBE11UD8ABFA-5C-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  147. EBE11UD8AEFA - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
  148. EBE11UD8AEFA-4A-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  149. EBE11UD8AEFA-5C-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  150. EBE11UD8AEFA-6 - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
  151. EBE11UD8AEFA-6E-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  152. EBE11UD8AESA - 1gb Ddr2 Sdram So-dimm (128m Words X 64 Bits, 2 Ranks)
  153. EBE11UD8AESA-4A-E - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
  154. EBE11UD8AESA-5C-E - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
  155. EBE11UD8AESA-6E-E - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
  156. EBE11UD8AGFA - 1gb Unbuffered Ddr2 Sdram Dimm (128m Words X 64 Bits, 2 Ranks)
  157. EBE11UD8AGFA-4A-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  158. EBE11UD8AGFA-5C-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  159. EBE11UD8AGFA-6E-E - 1GB Unbuffered DDR2 SDRAM DIMM (128M words x 64 bits, 2 Ranks)
  160. EBE11UD8AGSA - 1gb Ddr2 Sdram So-dimm (128m Words X 64 Bits, 2 Ranks)
  161. EBE11UD8AGSA-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  162. EBE11UD8AGSA-5C-E - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
  163. EBE11UD8AGSA-6E-E - 1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)
  164. EBE20AE4ABFA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  165. EBE20AE4ABFA-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  166. EBE20RE4AAFA - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 1 Rank)
  167. EBE20RE4AAFA-4A-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
  168. EBE20RE4AAFA-5C-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 1 Rank)
  169. EBE20RE4ABFA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  170. EBE20RE4ABFA-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  171. EBE20RE4ABFA-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  172. EBE20RE4ABFA-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  173. EBE21AD4AGFB - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  174. EBE21AD4AGFB-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  175. EBE21AD4AGFB-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  176. EBE21AD4AGFB-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  177. EBE21RD4ABHA - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  178. EBE21RD4ABHA-4A-E - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 2 Ranks)
  179. EBE21RD4ABHA-5C-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  180. EBE21RD4AEFA - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 2 Ranks)
  181. EBE21RD4AEFA-4A-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  182. EBE21RD4AEFA-5C-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  183. EBE21RD4AGFA - 2gb Registered Ddr2 Sdram Dimm (256m Words X 72 Bits, 2 Ranks)
  184. EBE21RD4AGFA-4A-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  185. EBE21RD4AGFA-5C-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  186. EBE21RD4AGFA-6E-E - 2GB Registered DDR2 SDRAM DIMM (256M words x 72 bits, 2 Ranks)
  187. EBE21RD4AGFB - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  188. EBE21RD4AGFB-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  189. EBE21RD4AGFB-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  190. EBE21RD4AGFB-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  191. EBE41RE4AAHA - 4gb Registered Ddr2 Sdram Dimm (512m Words X 72 Bits, 2 Ranks)
  192. EBE41RE4AAHA-4A-E - 4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
  193. EBE41RE4AAHA-5C-E - 4GB Registered DDR2 SDRAM DIMM (512M words x 72 bits, 2 Ranks)
  194. EBE41RE4ABHA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  195. EBE41RE4ABHA-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  196. EBE41RE4ABHA-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  197. EBE41RE4ABHA-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  198. EBE51AD8AGFA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  199. EBE51AD8AGFA-4A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  200. EBE51AD8AGFA-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  201. EBE51AD8AGFA-6E-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive
  202. EBE51ED8ABFA - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  203. EBE51ED8ABFA-4A-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  204. EBE51ED8ABFA-5C-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  205. EBE51ED8AEFA - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  206. EBE51ED8AEFA-4A-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  207. EBE51ED8AEFA-5C-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  208. EBE51ED8AEFA-6 - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  209. EBE51ED8AEFA-6E-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  210. EBE51ED8AGFA - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  211. EBE51ED8AGFA-4A-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  212. EBE51ED8AGFA-5C-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  213. EBE51ED8AGFA-6E-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  214. EBE51RD8ABFA - 512mb Registered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  215. EBE51RD8ABFA-4A-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  216. EBE51RD8ABFA-5C-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  217. EBE51RD8AEFA - 512mb Registered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  218. EBE51RD8AEFA-4A-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  219. EBE51RD8AEFA-5C-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  220. EBE51RD8AGFA - 512mb Registered Ddr2 Sdram Dimm (64m Words X 72 Bits, 1 Rank)
  221. EBE51RD8AGFA-4A-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  222. EBE51RD8AGFA-5C-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  223. EBE51RD8AGFA-6E-E - 512MB Registered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
  224. EBE51UD8ABFA - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 64 Bits, 1 Rank)
  225. EBE51UD8ABFA-4A -
  226. EBE51UD8ABFA-4A-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  227. EBE51UD8ABFA-4C -
  228. EBE51UD8ABFA-5C -
  229. EBE51UD8ABFA-5C-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  230. EBE51UD8AEFA - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 64 Bits, 1 Rank)
  231. EBE51UD8AEFA-4A-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  232. EBE51UD8AEFA-5C-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  233. EBE51UD8AEFA-6 - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 64 Bits, 1 Rank)
  234. EBE51UD8AEFA-6E-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  235. EBE51UD8AGFA - 512mb Unbuffered Ddr2 Sdram Dimm (64m Words X 64 Bits, 1 Rank)
  236. EBE51UD8AGFA-4A-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  237. EBE51UD8AGFA-5C-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  238. EBE51UD8AGFA-6E-E - 512MB Unbuffered DDR2 SDRAM DIMM (64M words x 64 bits, 1 Rank)
  239. EBE52UC8AAFA -
  240. EBE52UD6ABSA - 512mb Ddr2 Sdram So-dimm (64m Words X 64 Bits, 2 Ranks)
  241. EBE52UD6ABSA-4A-E - 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  242. EBE52UD6ABSA-5C-E - 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  243. EBE52UD6AFSA - 512mb Ddr2 Sdram So-dimm (64m Words X 64 Bits, 2 Ranks)
  244. EBE52UD6AFSA-4A-E - 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  245. EBE52UD6AFSA-5C-E - 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  246. EBE52UD6AFSA-6E-E - 512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
  247. EBR12EC8ABFD -
  248. EBR12EC8ABFD-8C -
  249. EBR12EC8ABFD-AD -
  250. EBR12EC8ABFD-AE -
  251. EBR12EC8ABFD-AEP -
  252. EBR12UC8ABFD -
  253. EBR12UC8ABFD-8C -
  254. EBR12UC8ABFD-AD -
  255. EBR12UC8ABFD-AE -
  256. EBR12UC8ABFD-AEP -
  257. EBR25EC8ABFD -
  258. EBR25EC8ABFD-8C -
  259. EBR25EC8ABFD-AD -
  260. EBR25EC8ABFD-AE -
  261. EBR25EC8ABFD-AEP -
  262. EBR25UC8ABFD -
  263. EBR25UC8ABFD-8C -
  264. EBR25UC8ABFD-AD -
  265. EBR25UC8ABFD-AE -
  266. EBR25UC8ABFD-AEP -
  267. EBR51EC8ABFD -
  268. EBR51EC8ABFD-8C -
  269. EBR51EC8ABFD-AD -
  270. EBR51EC8ABFD-AE -
  271. EBR51EC8ABFD-AEP -
  272. EBR51UC8ABFD -
  273. EBR51UC8ABFD-8C -
  274. EBR51UC8ABFD-AD -
  275. EBR51UC8ABFD-AE -
  276. EBR51UC8ABFD-AEP -
  277. EBS11RC4ACNA - 1 Gb Registered Sdram Dimm
  278. EBS11RC4ACNA-75 - 1 GB Registered SDRAM DIMM
  279. EBS11RC4ACNA-7A - 1 GB Registered SDRAM DIMM
  280. EBS12UC6APS - 128mb Sdram S.o.dimm
  281. EBS12UC6APS-75 - 128MB SDRAM S.O.DIMM
  282. EBS12UC6APS-75L - 128MB SDRAM S.O.DIMM
  283. EBS12UC6APS-7A - 128MB SDRAM S.O.DIMM
  284. EBS12UC6APS-7AL - 128MB SDRAM S.O.DIMM
  285. EBS12UC6APS-80 - 128MB SDRAM S.O.DIMM
  286. EBS12UC6APS-80L - 128MB SDRAM S.O.DIMM
  287. EBS21RC2ACNA - 2gb Registered Sdram Dimm
  288. EBS21RC2ACNA-75 - 2GB Registered SDRAM DIMM
  289. EBS21RC2ACNA-7A - 2GB Registered SDRAM DIMM
  290. EBS25EC8APFA - 256mb Unbuffered Sdram Dimm
  291. EBS25EC8APFA-75 - 256MB Unbuffered SDRAM DIMM
  292. EBS25EC8APFA-7A - 256MB Unbuffered SDRAM DIMM
  293. EBS25EC8APSA - 256mb Sdram S.o.dimm
  294. EBS25EC8APSA-75 - 256MB SDRAM S.O.DIMM
  295. EBS25EC8APSA-75L - 256MB SDRAM S.O.DIMM
  296. EBS25EC8APSA-7A - 256MB SDRAM S.O.DIMM
  297. EBS25EC8APSA-7AL - 256MB SDRAM S.O.DIMM
  298. EBS25EC8APSA-80 - 256MB SDRAM S.O.DIMM
  299. EBS25EC8APSA-80L - 256MB SDRAM S.O.DIMM
  300. EBS25UC8APFA - 256mb Unbuffered Sdram Dimm
  301. EBS25UC8APFA-75 - 256MB Unbuffered SDRAM DIMM
  302. EBS25UC8APFA-7A - 256MB Unbuffered SDRAM DIMM
  303. EBS25UC8APMA - 256mb Sdram Micro Dimm
  304. EBS25UC8APMA-75 - 256MB SDRAM Micro DIMM
  305. EBS25UC8APMA-75L - 256MB SDRAM Micro DIMM
  306. EBS25UC8APMA-7A - 256MB SDRAM Micro DIMM
  307. EBS25UC8APMA-7AL - 256MB SDRAM Micro DIMM
  308. EBS25UC8APMA-80 - 256MB SDRAM Micro DIMM
  309. EBS25UC8APMA-80L - 256MB SDRAM Micro DIMM
  310. EBS26UC6APS - 256mb Sdram S.o.dimm
  311. EBS26UC6APS-75 - 256MB SDRAM S.O.DIMM
  312. EBS26UC6APS-75L - 256MB SDRAM S.O.DIMM
  313. EBS26UC6APS-7A - 256MB SDRAM S.O.DIMM
  314. EBS26UC6APS-7AL - 256MB SDRAM S.O.DIMM
  315. EBS26UC6APS-80 - 256MB SDRAM S.O.DIMM
  316. EBS26UC6APS-80L - 256MB SDRAM S.O.DIMM
  317. EBS51RC4ACFC - 512mb Registered Sdram Dimm
  318. EBS51RC4ACFC-75 - 512MB Registered SDRAM DIMM
  319. EBS51RC4ACFC-7A - 512MB Registered SDRAM DIMM
  320. EBS52EC8APFA - 512mb Unbuffered Sdram Dimm
  321. EBS52EC8APFA-75 - 512MB Unbuffered SDRAM DIMM
  322. EBS52EC8APFA-7A - 512MB Unbuffered SDRAM DIMM
  323. EBS52UC8APFA - 512mb Unbuffered Sdram Dimm
  324. EBS52UC8APFA-75 - 512MB Unbuffered SDRAM DIMM
  325. EBS52UC8APFA-7A - 512MB Unbuffered SDRAM DIMM
  326. EBS52UC8APSA - 512mb Sdram S.o.dimm
  327. EBS52UC8APSA-75 - 512MB SDRAM S.O.DIMM
  328. EBS52UC8APSA-75L - 512MB SDRAM S.O.DIMM
  329. EBS52UC8APSA-7A - 512MB SDRAM S.O.DIMM
  330. EBS52UC8APSA-7AL - 512MB SDRAM S.O.DIMM
  331. EDD1216AASE - 128m Bits Ddr Sdram (8m Words X 16 Bits)
  332. EDD1216AASE-6B-E - 128M bits DDR SDRAM (8M words x 16 bits)
  333. EDD1216AASE-7A-E - 128M bits DDR SDRAM (8M words x 16 bits)
  334. EDD1216AATA - 128m Bits Ddr Sdram (8m Words X 16 Bits)
  335. EDD1216AATA-5 - 128m Bits Ddr Sdram (8m Words X 16 Bits, Ddr400)
  336. EDD1216AATA-5B-E - 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
  337. EDD1216AATA-5C-E - 128M bits DDR SDRAM (8M words x 16 bits, DDR400)
  338. EDD1216AATA-6B-E - 128M bits DDR SDRAM (8M words x 16 bits)
  339. EDD1216AATA-7A-E - 128M bits DDR SDRAM (8M words x 16 bits)
  340. EDD1216AATA-7B-E - 128M bits DDR SDRAM (8M words x 16 bits)
  341. EDD1232AABH - 128m Bits Ddr Sdram (4m Words X 32 Bits)
  342. EDD1232AABH-6B-E - 128M bits DDR SDRAM (4M words x 32 bits)
  343. EDD1232AABH-7A-E - 128M bits DDR SDRAM (4M words x 32 bits)
  344. EDD1232AAFA - 128m Bits Ddr Sdram (4m Words X 32 Bits)
  345. EDD1232AAFA-6B-E - 128M bits DDR SDRAM (4M words x 32 bits)
  346. EDD1232AAFA-7A-E - 128M bits DDR SDRAM (4M words x 32 bits)
  347. EDD2504AKTA - 256m Bits Ddr Sdram (64m Words X 4 Bits)
  348. EDD2504AKTA-6B - 256M bits DDR SDRAM (64M words x 4 bits)
  349. EDD2504AKTA-6B-E - 256m Bits Ddr Sdram (64m Words X 4 Bits)
  350. EDD2504AKTA-7A - 256M bits DDR SDRAM (64M words x 4 bits)
  351. EDD2504AKTA-7A-E - 256M bits DDR SDRAM (64M words x 4 bits)
  352. EDD2504AKTA-7B - 256M bits DDR SDRAM (64M words x 4 bits)
  353. EDD2504AKTA-7B-E - 256M bits DDR SDRAM (64M words x 4 bits)
  354. EDD2504AKTA-E - 256M bits DDR SDRAM (64M words x 4 bits)
  355. EDD2508AETA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  356. EDD2508AETA-5B-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  357. EDD2508AETA-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  358. EDD2508AETA-6B-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  359. EDD2508AETA-7A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  360. EDD2508AKTA -
  361. EDD2508AKTA-5 - 256m Bits Ddr Sdram (32m Words X 8 Bits, Ddr400)
  362. EDD2508AKTA-5B - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
  363. EDD2508AKTA-5B-E - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
  364. EDD2508AKTA-5C - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
  365. EDD2508AKTA-5C-E - 256M bits DDR SDRAM (32M words x 8 bits, DDR400)
  366. EDD2508AKTA-5-E - 256m Bits Ddr Sdram (32m Words X 8 Bits, Ddr400)
  367. EDD2516AETA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  368. EDD2516AETA-5B-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  369. EDD2516AETA-5C-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  370. EDD2516AETA-6B-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  371. EDD2516AETA-7A-E - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  372. EDD2516AKTA -
  373. EDD2516AKTA-5C-E - 256M bits DDR SDRAM (16M words x16 bits, DDR400)
  374. EDD2516AKTA-5-E - 256m Bits Ddr Sdram (16m Words X16 Bits, Ddr400)
  375. EDD2516AKTA-6B -
  376. EDD2516AKTA-6B-E - 256m Bits Ddr Sdram (16m Words X 16 Bits)
  377. EDD2516AKTA-7A -
  378. EDD2516AKTA-7A-E - 256M bits DDR SDRAM (16M words x 16 bits)
  379. EDD2516AKTA-7B -
  380. EDD2516AKTA-7B-E - 256M bits DDR SDRAM (16M words x 16 bits)
  381. EDD2516AKTA-E - 256M bits DDR SDRAM (16M words x 16 bits)
  382. EDD5104ABTA - 512m Bits Ddr Sdram
  383. EDD5104ABTA-6B - 512M bits DDR SDRAM
  384. EDD5104ABTA-7A - 512M bits DDR SDRAM
  385. EDD5104ABTA-7B - 512M bits DDR SDRAM
  386. EDD5104ADTA - 512m Bits Ddr Sdram
  387. EDD5104ADTA-6B - 512M bits DDR SDRAM
  388. EDD5104ADTA-6B-E - 512m Bits Ddr Sdram
  389. EDD5104ADTA-6BL - 512M bits DDR SDRAM
  390. EDD5104ADTA-6BL-E - 512M bits DDR SDRAM
  391. EDD5104ADTA-7A - 512M bits DDR SDRAM
  392. EDD5104ADTA-7A-E - 512M bits DDR SDRAM
  393. EDD5104ADTA-7AL - 512M bits DDR SDRAM
  394. EDD5104ADTA-7AL-E - 512M bits DDR SDRAM
  395. EDD5104ADTA-7B - 512M bits DDR SDRAM
  396. EDD5104ADTA-7B-E - 512M bits DDR SDRAM
  397. EDD5104ADTA-7BL - 512M bits DDR SDRAM
  398. EDD5104ADTA-7BL-E - 512M bits DDR SDRAM
  399. EDD5104ADTA-E - 512M bits DDR SDRAM
  400. EDD5108ABTA - 512M bits DDR SDRAM
  401. EDD5108ABTA-6B - 512M bits DDR SDRAM
  402. EDD5108ABTA-7A - 512M bits DDR SDRAM
  403. EDD5108ABTA-7B - 512M bits DDR SDRAM
  404. EDD5108ADTA - 512M bits DDR SDRAM
  405. EDD5108ADTA-5C - 512m Bits Ddr Sdram
  406. EDD5108ADTA-6B - 512M bits DDR SDRAM
  407. EDD5108ADTA-6B-E - 512M bits DDR SDRAM
  408. EDD5108ADTA-6BL - 512M bits DDR SDRAM
  409. EDD5108ADTA-6BL-E - 512M bits DDR SDRAM
  410. EDD5108ADTA-7A - 512M bits DDR SDRAM
  411. EDD5108ADTA-7A-E - 512M bits DDR SDRAM
  412. EDD5108ADTA-7AL - 512M bits DDR SDRAM
  413. EDD5108ADTA-7AL-E - 512M bits DDR SDRAM
  414. EDD5108ADTA-7B - 512M bits DDR SDRAM
  415. EDD5108ADTA-7B-E - 512M bits DDR SDRAM
  416. EDD5108ADTA-7BL - 512M bits DDR SDRAM
  417. EDD5108ADTA-7BL-E - 512M bits DDR SDRAM
  418. EDD5108ADTA-E - 512M bits DDR SDRAM
  419. EDD5108AFTA - 512m Bits Ddr Sdram
  420. EDD5108AFTA-5 - 512m Bits Ddr Sdram
  421. EDD5108AFTA-5B-E - 512M bits DDR SDRAM
  422. EDD5108AFTA-5C-E - 512M bits DDR SDRAM
  423. EDD5108AFTA-6B-E - 512M bits DDR SDRAM
  424. EDD5108AFTA-7A-E - 512M bits DDR SDRAM
  425. EDD5108AFTA-7B-E - 512M bits DDR SDRAM
  426. EDD5116ADTA - 512M bits DDR SDRAM
  427. EDD5116ADTA-5C - 512M bits DDR SDRAM
  428. EDD5116ADTA-6B - 512M bits DDR SDRAM
  429. EDD5116ADTA-6B-E - 512M bits DDR SDRAM
  430. EDD5116ADTA-6BL - 512M bits DDR SDRAM
  431. EDD5116ADTA-6BL-E - 512M bits DDR SDRAM
  432. EDD5116ADTA-7A - 512M bits DDR SDRAM
  433. EDD5116ADTA-7A-E - 512M bits DDR SDRAM
  434. EDD5116ADTA-7AL - 512M bits DDR SDRAM
  435. EDD5116ADTA-7AL-E - 512M bits DDR SDRAM
  436. EDD5116ADTA-7B - 512M bits DDR SDRAM
  437. EDD5116ADTA-7B-E - 512M bits DDR SDRAM
  438. EDD5116ADTA-7BL - 512M bits DDR SDRAM
  439. EDD5116ADTA-7BL-E - 512M bits DDR SDRAM
  440. EDD5116ADTA-E - 512M bits DDR SDRAM
  441. EDD5116AFTA - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
  442. EDD5116AFTA-5 - 512M bits DDR SDRAM
  443. EDD5116AFTA-5B-E - 512M bits DDR SDRAM
  444. EDD5116AFTA-5C-E - 512M bits DDR SDRAM
  445. EDD5116AFTA-6B-E - 512M bits DDR SDRAM
  446. EDD5116AFTA-7A-E - 512M bits DDR SDRAM
  447. EDD5116AFTA-7B-E - 512M bits DDR SDRAM
  448. EDE1104AASE - 1g Bits Ddr2 Sdram Organized As 33,554,432 Words X 8 Banks.
  449. EDE1104AASE-4A-E - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  450. EDE1104AASE-5C-E - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  451. EDE1104AASE-6E-E - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  452. EDE1108AASE - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  453. EDE1108AASE-4A-E - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  454. EDE1108AASE-5C-E - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  455. EDE1108AASE-6E-E - 1G bits DDR2 SDRAM organized as 33,554,432 words x 8 banks.
  456. EDE2508ABSE - 256m Bits Ddr2 Sdram
  457. EDE2508ABSE-5C-E - 256M bits DDR2 SDRAM
  458. EDE2508ABSE-6C-E - 256M bits DDR2 SDRAM
  459. EDE2508ABSE-6E-E - 256M bits DDR2 SDRAM
  460. EDE2508ABSE-GE - 256m Bits Ddr2 Sdram For Hyper Dimm
  461. EDE2508ABSE-GE-E - 256M bits DDR2 SDRAM for HYPER DIMM
  462. EDE2516ABSE - 256M bits DDR2 SDRAM
  463. EDE2516ABSE-5C-E - 256M bits DDR2 SDRAM
  464. EDE2516ABSE-6C-E - 256M bits DDR2 SDRAM
  465. EDE2516ABSE-6E-E - 256M bits DDR2 SDRAM
  466. EDE2516ABSE-GE - 256M bits DDR2 SDRAM for HYPER DIMM
  467. EDE2516ABSE-GE-E - 256M bits DDR2 SDRAM for HYPER DIMM
  468. EDE5104ABSE - 512m Bits Ddr2 Sdram
  469. EDE5104ABSE-4A-E - 512M bits DDR2 SDRAM
  470. EDE5104ABSE-4C-E -
  471. EDE5104ABSE-5C-E - 512M bits DDR2 SDRAM
  472. EDE5104AESK - 512m Bits Ddr2 Sdram
  473. EDE5104AESK-4A-E - 512M bits DDR2 SDRAM
  474. EDE5104AESK-5C-E - 512M bits DDR2 SDRAM
  475. EDE5104AESK-6E-E - 512M bits DDR2 SDRAM
  476. EDE5104AGSE - 512m Bits Ddr2 Sdram
  477. EDE5104AGSE-4A-E - 512M bits DDR2 SDRAM
  478. EDE5104AGSE-5C-E - 512M bits DDR2 SDRAM
  479. EDE5104AGSE-6C-E - 512M bits DDR2 SDRAM
  480. EDE5104AGSE-6E-E - 512M bits DDR2 SDRAM
  481. EDE5104GBSA - 512m Bits Ddr-ii Sdram
  482. EDE5104GBSA-4A-E - 512M bits DDR-II SDRAM
  483. EDE5104GBSA-5A-E - 512M bits DDR-II SDRAM
  484. EDE5108ABSE - 512M bits DDR2 SDRAM
  485. EDE5108ABSE-4A-E - 512M bits DDR2 SDRAM
  486. EDE5108ABSE-4C-E -
  487. EDE5108ABSE-5C-E - 512M bits DDR2 SDRAM
  488. EDE5108AESK - 512M bits DDR2 SDRAM
  489. EDE5108AESK-4A-E - 512M bits DDR2 SDRAM
  490. EDE5108AESK-5C-E - 512M bits DDR2 SDRAM
  491. EDE5108AESK-6E-E - 512M bits DDR2 SDRAM
  492. EDE5108AGSE - 512M bits DDR2 SDRAM
  493. EDE5108AGSE-4A-E - 512M bits DDR2 SDRAM
  494. EDE5108AGSE-5C-E - 512M bits DDR2 SDRAM
  495. EDE5108AGSE-6C-E - 512M bits DDR2 SDRAM
  496. EDE5108AGSE-6E-E - 512M bits DDR2 SDRAM
  497. EDE5108GBSA - 512M bits DDR-II SDRAM
  498. EDE5108GBSA-4A-E - 512M bits DDR-II SDRAM
  499. EDE5108GBSA-5A-E - 512M bits DDR-II SDRAM
  500. EDE5116ABSE - 512M bits DDR2 SDRAM