EDD5116AFTA (Elpida) - * Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions, 512 Mb

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EDD5116AFTA (Elpida)

Electronic component documentation (datasheet) «EDD5116AFTA» (512 Mb), manufacturer Elpida. Download datasheet file:

Datasheet EDD5116AFTA manufacturer Elpida

Partname	EDD5116AFTA
Description	* Double-data-rate architecture; two data transfers per clock cycle * The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outputs, and DM are synchronized with DQS * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions
Functional	512 Mb
Manufacturer	Elpida Memory
Site	www.elpida.com

Size	Pages: 52, 616.25Kb
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