V-Data
VDABA2404
PC-133/CL2 SDRAM Unbuffered DIMM
8Mx64bits SDRAM DIMM based on 8Mx16, 4Bank, 4K Refresh, 3.3V SDRAM
General Description
The VDABA2404 is 8Mx64 bits Synchronous DRAM
Modules, The modules are composed of four 8Mx16
bits CMOS Synchronous DRAMs in TSOP-II 400mil
54pin package and one 2Kbit EEPROM in 8pin
TSSOP(TSOP) package on a 168pin glassepoxy
printed circuit board.
The V-Data is a Dual In-line Memory Module and is
intended for mounting onto 168-pins edge connector
sockets. Fully synchronous operation referenced to
the positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock.
The data paths are internally pipelined to achieve very
high bandwidth.
Features
PC-133/CL2 support
Auto refresh and self refresh
4096 refresh cycles / 64ms
Single 3.30.3V power supply
All device pins are compatible with LVTTL
interface
Data mask function by DQM
Serial Presence Detect with EEPROM
Module bank : one physical bank
PCB : B6666RB,Height (23.88mm),single
sided component, Four layers
Ordering Information.
Part No.
Frequency
Bank
Ref.
Package
VDABA2404
133Mhz/CL2
4 Banks
4K
TSOP II
Pin Assignment
FRONT SIDE
BACK SIDE
PIN NAME PIN
NAME
PIN
NAME
PIN NAME PIN NAME PIN NAME PIN NAME
PIN
NAME
1 VSS 22 NC 43 VSS 64
VSS
85
VSS 106
NC 127 VSS 148 VSS
2 DQ0 23 VSS 44 NC 65 DQ21 86 DQ32 107 VSS 128 CKE0
149
DQ53
3 DQ1 24 NC 45 /CS2 66 DQ22 87 DQ33 108
NC 129
NC 150
DQ54
4 DQ2 25 NC 46
DQM2
67 DQ23 88 DQ34 109
NC 130 DQM6
151
DQ55
5 DQ3 26 VCC 47 DQM3 68
VCC
89 DQ35 110 VCC 131 DQM7
152 VCC
6 VCC 27 /WE 48 NC 69 DQ24 90
VCC 111 /CAS 132
NC 153
DQ56
7 DQ4 28 DQM0 49 VCC 70 DQ25 91 DQ36 112 DQM4 133 VCC 154 DQ57
8 DQ5 29 DQM1 50 NC 71 DQ26 92 DQ37 113 DQM5 134
NC 155 DQ58
9 DQ6 30 /CS0 51 NC 72 DQ27 93 DQ38 114
NC 135
NC 156 DQ59
10 DQ7 31 NC 52 NC 73
VCC
94 DQ39 115 /RAS 136
NC 157 VCC
11 DQ8 32 VSS 53 NC 74 DQ28 95 DQ40 116 VSS 137
NC 158
DQ60
12 VSS 33 A0 54 VSS 75 DQ29 96
VSS 117
A1 138 VSS 159
DQ61
13 DQ9 34 A2 55 DQ16 76 DQ30 97 DQ41 118
A3 139 DQ48
160
DQ62
14 DQ10 35 A4 56 DQ17 77 DQ31 98 DQ42 119
A5 140 DQ49 161 DQ63
15 DQ11 36 A6 57 DQ18 78
VSS
99 DQ43 120
A7 141 DQ50 162 VSS
16 DQ12 37 A8 58 DQ19 79
CK2 100 DQ44 121
A9 142 DQ51 163 CK3
17 DQ13 38 A10/AP 59 VCC 80
NC 101 DQ45 122 BA0 143 VSS 164 NC
18 VCC 39 BA1 60 DQ20 81
WP
102 VCC 123
A11
144 DQ52 165 SA0
19 DQ14 40 VCC 61 NC 82
SDA 103 DQ46 124 VCC 145
NC 166 SA1
20 DQ15 41 VCC 62 NC 83
SCL 104 DQ47 125 CK1 146
NC 167 SA2
21 NC 42 CK0 63 NC 84
VCC 105
NC 126
NC 147
NC 168
VCC
Rev 1 April, 2001
1
V-Data
VDABA2404
Pin Description
PIN NAME
FUNCTION
CK0~3
System Clock
Active on the positive edge to sample all inputs.
CKE0~1 Clock
Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS0~3 Chip Select
Disables or Enables device operation by masking or enabling all input
except CK, CKE and L(U)DQM
A0~A11 Address
Row / Column address are multiplexed on the same pins.
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ63 Data
Data inputs / outputs are multiplexed on the same pins.
DQM0~7 Data Mask
Makes data output Hi-Z,
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
SDA
Serial data I/O
EEPROM serial data I/O
SCL
Serial clock
EEPROM clock input
SA0~2
Address in EEPROM
EEPROM address input
WP
Write Protect for EEPROM
Write Protect for Serial Presence Detect on DIMM
NC
No Connection
This pin is recommended to be left No Connection on the device.
Rev 1 April, 2001
2
V-Data
VDABA2404
Block Diagram
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
/CS
/CS
LDQM
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CS
LDQM
UDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
/CS
LDQM
UDQM
LDQM
UDQM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQM4
DQM3
DQM6
DQM7
DQM1
DQM2
DQM0
/RAS
VSS
VCC
/WE
/CAS
/RAS : D0 ~D3
/WE : D0 ~D3
/CAS : D0 ~D3
A0~A11
BA0/BA1:D0~D3
BA0/BA1
A0~A11:D0~D3
D0~D3
D0~D3
CKE : D0~D3
CKE0
D0
D1
D3
D2
SCL
SPD
47K Ohms
SA0 SA1 SA2
A0 A1 A2
SDA
WP
CK : 2 SDRAMs
CK : 2 SDRAMs
CK2
CK3
CK0
3.3 pF
10 Ohm
10 Ohm
CK1
10 Ohm
10 Ohm
Rev 1 April, 2001
3
V-Data
VDABA2404
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
out
-1.0
~
4.6
V
Voltage on VDD supply relative to Vss
V
DD
, V
DDQ
-1.0
~
4.6
V
Storage temperature
T
STG
-55 ~ +150
Power dissipation
P
D
4
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0 3.3 3.6
V
Input logic high voltage
V
IH
2.0 3.0
V
DD
+0.3 V
1
Input logic low voltage
V
IL
-0.3 0 0.8
V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
=-2mA
Output logic low voltage
V
OL
- - 0.4
V
I
OL
=2mA
Input leakage current
I
IL
-5 - 5
uA
3
Output leakage current
I
OL
-5 - 5
uA
4
Note : 1. V
IH
(max)=4.6V AC for pulse width 10ns acceptable.
2.V
IL
(min)=-1.5V AC for pulse width 10ns acceptable.
3.Any
input
0V
V
IN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V V
OUT
V
DD
.
AC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Value
Unit
Note
AC input high / low level voltage
V
IH
/ V
IL
2.4 / 0.4
V
Input timing measurement reference level voltage
Vtrip
1.4
V
Input rise / fall time
TR / tF
1
Ns
Output timing measurement reference level
Voutfef
1.4
V
Output load capacitance for access time measurement
CL
50
pF
2
Note: 1. 3.15V V
DD
3.6V
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1 April, 2001
4
V-Data
VDABA2404
Capacitance
TA=25, f-=1Mhz, VDD=3.3V
Parameter Pin
Symbol
Min
Max
Unit
CLK Cl1
25
40
pF
Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2 40
55
pF
Data input / output capacitance DQM
CI/O
5
15
pF
Output load circuit
V
OH
(DC) = 2.4V,I
OH
= -2mA
V
OL
(DC) = 0.4V,I
OL
= 2mA
3.3 V
1200 ohms
870 ohms
50 pF
Output
DC Characteristics I
Parameter Symbol
Min
Max
Unit
Note
Input leakage current
I
LI
-1
1
uA
1
Output leakage current
I
LO
-1
1
uA
2
Output high voltage
V
OH
2.4
-
V
I
OH
= -4mA
Output low voltage
V
OL
-
0.4
V
I
OL
= 4mA
Note : 1.V
IN
= 0 TO 3.6V, All other pins are not tested under V
IN
= 0V.
2.D
OUT
is disabled, V
OUT
= 0 to 3.6.
Rev 1 April, 2001
5
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