V-Data
VDECB1608
DDR SDRAM 200pin DIMM
16Mx64bits DDR SDRAM 200pin SODIMM based on 16Mx8
Performance range
General Description
The VDECB1608 is 16Mx64 bits Double Data Rate
SDRAM Modules, The modules are composed of
eight 16Mx8 bits CMOS Double Data Rate SDRAMs
in TSOP-II 400mil 66pin package and one 2Kbit
EEPROM in 8pin TSSOP(TSOP) package on a
200pin glassepoxy printed circuit board.
The V-Data is a Dual In-line Memory Module and is
intended for mounting onto 200-pins edge connector
sockets. Synchronous design allows precise cycle
control with the use of system clock. Data I/O
transactions are possible on both edges of DQS.
Range of operating frequencies, programmable
latencies and burst lengths allow the same device to
be useful for a variety of high bandwidth, high
performance memory system applications.
Features
DLL aligns DQ and DQS transition with CK
transition
Double-data-rate architecture.
Bi-directional data strobe (DQS)
Differential clock inputs(CK and /CK)
Auto refresh and self refresh
4096 refresh cycles / 64ms
Power supply: Vdd,Vddq:2.5V0.2V
Programmable Burst length (2,4,8)
Serial Presence Detect with EEPROM
Module bank : one physical bank
PCB : SO200RCB,Height (12.5mm),single
sided component, Six layers
Part No.
Max Freq.
Interface
VDECB1608-75B
133MHz (7.5ns /CL=2.5)
SSTL_2
Pin Assignment
FRONT SIDE
BACK SIDE
PIN NAME PIN
NAME
PIN
NAME
PIN NAME PIN NAME PIN NAME PIN NAME
PIN
NAME
1 VREF 26 DM1 51 VSS 76
VSS 101
A9 126
VSS 151 DQ42
176
DQ55
2 VREF 27 VSS 52 VSS 77 DQS8 102
A8 127 DQ32 152 DQ46 177 DQ56
3 VSS 28 VSS 53 DQ19 78
DM8 103 VSS 128 DQ36 153 DQ43 178 DQ60
4 VSS 29 DQ10 54 DQ23 79
CB2 104 VSS 129 DQ33 154 DQ47 179 VDD
5 DQ0 30 DQ14 55 DQ24 80
CB6 105
A7 130 DQ37 155 VDD 180 VDD
6 DQ4 31 DQ11 56 DQ28 81
VDD 106
A6 131 VDD 156 VDD 181 DQ57
7 DQ1 32 DQ15 57 VDD 82
VDD 107
A5 132 VDD 157 VDD 182 DQ61
8 DQ5 33 VDD 58 VDD 83 VBS3 108
A4 133 DQS4 158 /CK1 183
DQS7
9 VDD 34 VDD 59 DQ25 84
CB7 109
A3 134 DM4 159 VSS 184 DM7
10 VDD 35 CK0 60 DQ29 85
DU 110
A2 135 DQ34 160 CK1 185 VSS
11 DQS0 36 VDD 61 DQS3 86
DU 111
A1 136 DQ38 161 VSS 186 VSS
12 DM0 37 /CK0 62 DM3 87
VSS 112
A0 137 VSS 162 VSS 187 DQ58
13 DQ2 38 VSS 63 VSS 88
VSS 113 VDD 138 VSS 163 DQ48
188
DQ62
14 DQ6 39 VSS 64 VSS 89
CK2
114 VDD 139 DQ35 164 DQ52 189 DQ59
15 VSS 40 VSS 65 DQ26 90
VSS 115
A10
140 DQ39 165 DQ49 190 DQ63
16 VSS 41 DQ16 66 DQ30 91
/CK2 116
BA1 141 DQ40 166 DQ53 191 VDD
17 DQ3 42 DQ20 67 DQ27 92
VDD 117
BA0 142 DQ44 167 VDD 192 VDD
18 DQ7 43 DQ17 68 DQ31 93
VDD 118 /RAS 143 VDD 168 VDD 193 SDA
19 DQ8 44 DQ21 69 VDD 94
VDD 119 /WE 144 VDD 169 DQS6
194 SA0
20 DQ12 45 VDD 70 VDD 95 CKE1 120 /CAS 145 DQ41 170 DM6 195 SCL
21 VDD 46 VDD 71 CB0 96 CKE0 121
/S0 146 DQ45 171 DQ50 196 SA1
22 VDD 47 DQS2 72 CB4 97
DU 122
/S1 147 DQS5 172 DQ54 197
VDDS
23 DQ9 48 DM2 73 CB3 98
DU 123
DU 148 DM5 173 VSS 198 SA2
24 DQ13 49 DQ18 74 CB5 99
A12 124
DU 149 VSS 174 VSS 199 VDDI
25 DQS1 50 DQ22 75 VSS 100
A11
125 VSS 150 VSS 175 DQ51 200 DU
Rev 2 Apr. 2002
2
V-Data
VDECB1608
Pin Description
PIN NAME
FUNCTION
CK0~CK2,/CK0~/CK02 System Clock
Active on the positive edge to sample all inputs.
CKE0 Clock
Enable
Masks system clock to freeze operation from the next clock
cycle. CKE should be enabled at least on cycle prior new
command. Disable input buffers for power down in standby
/CS0
Chip Select
Disables or Enables device operation by masking or enabling all
input except CK, CKE and L(U)DQM
A0~A11
Address
Row / Column address are multiplexed on the same pins.
BA0~BA1
Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ63
Data
Data inputs / outputs are multiplexed on the same pins.
DQS0~DQS7
Data Strobe
Bi-directional Data Strobe
DM0~7
Data Mask
Makes data output Hi-Z,
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with
/RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with
/CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS
Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ
Power Supply
Power Supply for DQS
VREF
Power Supply reference
Power Supply for reference
VDDS
SPD Power Supply
Serial EEPROM power Supply
SDA
Serial data I/O
EEPROM serial data I/O
SCL
Serial clock
EEPROM clock input
SA0~2
Address in EEPROM EEPROM
address input
VDDID
VDD identification
VDD identification flag
NC
No Connection
This pin is recommended to be left No Connection on the device.
Rev 2 Apr. 2002
3
V-Data
VDECB1608
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
out
-0.5~3.6
V
Voltage on VDD supply relative to Vss
V
DD
-1.0~3.6
V
Voltage on VDDQ supply relative to Vss
V
DDQ
-0.5~3.6
V
Storage temperature
T
STG
-55~+150
Power dissipation
P
D
8
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Min Max
Unit Note
Supply voltage
V
DD
, V
DDQ
2.3
2.7
V
Reference voltage
V
REF
V
DDQ
/2-50mV
V
DDQ
/2+50mV
V 1
Termination voltage
V
TT
V
REF-
0.04 V
REF
+0.04
2
Input logic high voltage
V
IH
V
REF
+0.15 V
DDQ
+0.3 V
3
Input logic low voltage
V
IL
-0.3
V
REF-
0.15 V
3
Output logic high voltage
V
OH
V
TT
+0.84 - V
I
OH
=-16.8mA
Output logic low voltage
V
OL
- V
TT-
0.84 V I
OL
=16.8mA
Input voltage Level
V
IN
-0.3
V
DDQ
+0.3 V
Input Differential Voltage
V
ID
0.3
V
DDQ
+0.6 V
4
Input crossing point voltage
V
IX
1.15 1.35 V
5
Input leakage current
I
IL
-2 2 uA
Output leakage current
I
OL
-5 5 uA
Note : 1. Includes25mV margin for DC offset on V
REF
, and a combined total of 50mV margin for all AC noise and
DC offset on V
REF
, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
REF
and internal DRAM noise coupled TO V
REF
, both of which may result in V
REF
noise. V
REF
should be
de-coupled with an inductance of 3nH.
2.V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected
to be set equal to V
REF
, and must track variations in the DC level of V
REF
3.These parameters should be tested at the pin on actual components and may be checked at either the pin or
the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been
bandwidth limited to 200MHz.
4.V
ID
is the magnitude of the difference between the input level on CK and the input level on /CK.
5.The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC
level of the same.
Rev 2 Apr. 2002
5
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