Document Outline

• 40MX and 42MX FPGA Families
  • Features
  • High Capacity
  • High Performance
  • HiRel Features
  • Ease of Integration
  • Plastic Device Resources
  • Temperature Grade Offerings
  • Speed Grade Offerings
• 40MX and 42MX FPGA Families
  • General Description
  • MX Architectural Overview
    • Logic Modules
      • Figure 1-1 . 40MX Logic Module
      • Figure 1-2 . 42MX C-Module Implementation
      • Figure 1-3 . 42MX S-Module Implementation
    • Dual-Port SRAM Modules
      • Figure 1-4 . A42MX24 and A42MX36 D-Module Implementation
      • Figure 1-5 . A42MX36 Dual-Port SRAM Block
    • Routing Structure
      • Figure 1-6 . MX Routing Structure
    • Clock Networks
      • Figure 1-7 . Clock Networks of 42MX Devices
      • Figure 1-8 . Quadrant Clock Network of A42MX36 Devices
    • MultiPlex I/O Modules
      • Figure 1-9 . 42MX I/O Module
      • Figure 1-10 . PCI Output Structure of A42MX24 and A42MX36 Devices
  • Other Architectural Features
    • Performance
    • User Security
      • Figure 1-11 . Fuselock
    • Programming
    • Power Supply
      • Table 1 . Voltage Support of MX Devices
    • Power-Up/Down in Mixed-Voltage Mode
    • Low Power Mode
  • Power Dissipation
    • General Power Equation
    • Static Power Component
    • Active Power Component
    • Equivalent Capacitance
    • CEQ Values for Actel MX FPGAs
    • Test Circuitry and Silicon Explorer II Probe
      • Figure 1-12 . Silicon Explorer II Setup with 40MX
      • Figure 1-13 . Silicon Explorer II Setup with 42MX
      • Table 2 . Device Configuration Options for Probe Capability
    • Design Consideration
    • IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
      • Figure 1-14 . 42MX IEEE 1149.1 Boundary Scan Circuitry
      • Table 3 . Test Access Port Descriptions
      • Table 4 . Supported BST Public Instructions
    • JTAG Mode Activation
      • Figure 1-15 . Device Selection Wizard
      • Table 5 . Boundary Scan Pin Configuration and Functionality
    • TRST Pin and TAP Controller Reset
    • Boundary Scan Description Language (BSDL) File
  • Development Tool Support
  • Related Documents
    • Application Notes
    • User�s Guides and Manuals
    • Miscellaneous
  • 5.0V Operating Conditions
    • Table 6 . Absolute Maximum Ratings for 40MX Devices*
    • Table 7 . Absolute Maximum Ratings for 42MX Devices*
    • Table 8 . Recommended Operating Conditions
  • 5V TTL Electrical Specifications
    • Table 9 . 5V TTL Electrical Specifications
  • 3.3V Operating Conditions
    • Table 10 . Absolute Maximum Ratings for 40MX Devices*
    • Table 11 . Absolute Maximum Ratings for 42MX Devices*
    • Table 12 . Recommended Operating Conditions
  • 3.3V LVTTL Electrical Specifications
    • Table 13 . 3.3V LVTTL Electrical Specifications
  • Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only)
    • Table 14 . Absolute Maximum Ratings*
    • Table 15 . Recommended Operating Conditions
  • Mixed 5.0V/3.3V Electrical Specifications
    • Table 16 . Mixed 5.0V/3.3V Electrical Specifications
  • Output Drive Characteristics for 5.0V PCI Signaling
    • Table 17 . DC Specification (5.0V PCI Signaling)1
    • Table 18 . AC Specifications (5.0V PCI Signaling)*
  • Output Drive Characteristics for 3.3V PCI Signaling
    • Table 19 . DC Specification (3.3V PCI Signaling)1
    • Table 20 . AC Specifications for (3.3V PCI Signaling)*
    • Figure 1-16 . Typical Output Drive Characteristics (Based Upon Measured Data)
  • Junction Temperature (TJ)
  • Package Thermal Characteristics
    • Table 21 . Package Thermal Characteristics
  • Timing Models
    • Figure 1-17 . 40MX Timing Model*
    • Figure 1-18 . 42MX Timing Model*
    • Figure 1-19 . 42MX Timing Model (Logic Functions Using Quadrant Clocks)
    • Figure 1-20 . 42MX Timing Model (SRAM Functions)
  • Parameter Measurement
    • Figure 1-21 . Output Buffer Delays
    • Figure 1-22 . AC Test Loads
    • Figure 1-23 . Input Buffer Delays
    • Figure 1-24 . Module Delays
  • Sequential Module Timing Characteristics
    • Figure 1-25 . Flip-Flops and Latches
  • Sequential Timing Characteristics
    • Figure 1-26 . Input Buffer Latches
    • Figure 1-27 . Output Buffer Latches
  • Decode Module Timing
    • Figure 1-28 . Decode Module Timing
  • SRAM Timing Characteristics
    • Figure 1-29 . SRAM Timing Characteristics
  • Dual-Port SRAM Timing Waveforms
    • Figure 1-30 . 42MX SRAM Write Operation
    • Figure 1-31 . 42MX SRAM Synchronous Read Operation
    • Figure 1-32 . 42MX SRAM Asynchronous Read Operation-Type 1 (Read Address Controlled)
    • Figure 1-33 . 42MX SRAM Asynchronous Read Operation-Type 2 (Write Address Controlled)
  • Predictable Performance: Tight Delay Distributions
  • Timing Characteristics
    • Critical Nets and Typical Nets
    • Long Tracks
    • Timing Derating
  • Temperature and Voltage Derating Factors
    • Table 22 . 42MX Temperature and Voltage Derating Factors
    • Figure 1-34 . 42MX Junction Temperature and Voltage Derating Curves
    • Table 23 . 40MX Temperature and Voltage Derating Factors
    • Figure 1-35 . 40MX Junction Temperature and Voltage Derating Curves
    • Table 24 . 42MX Temperature and Voltage Derating Factors
    • Figure 1-36 . 42MX Junction Temperature and Voltage Derating Curves
    • Table 25 . 40MX Temperature and Voltage Derating Factors
    • Figure 1-37 . 40MX Junction Temperature and Voltage Derating Curves
  • PCI System Timing Specification
  • PCI Models
    • Table 26 . Clock Specification for 33 MHz PCI
    • Table 27 . Timing Parameters for 33 MHz PCI
  • Timing Characteristics
    • Table 28 . A40MX02 Timing Characteristics (Nominal 5.0V Operation) (Continued)
    • Table 29 . A40MX02 Timing Characteristics (Nominal 3.3V Operation) (Continued)
    • Table 30 . A40MX04 Timing Characteristics (Nominal 5.0V Operation) (Continued)
    • Table 31 . A40MX04 Timing Characteristics (Nominal 3.3V Operation) (Continued)
    • Table 32 . A42MX09 Timing Characteristics (Nominal 5.0V Operation) (Continued)
    • Table 33 . A42MX09 Timing Characteristics (Nominal 3.3V Operation) (Continued)
    • Table 34 . A42MX16 Timing Characteristics (Nominal 5.0V Operation) (Continued)
    • Table 35 . A42MX16 Timing Characteristics (Nominal 3.3V Operation) (Continued)
    • Table 36 . A42MX24 Timing Characteristics (Nominal 5.0V Operation) (Continued)
    • Table 37 . A42MX24 Timing Characteristics (Nominal 3.3V Operation) (Continued)
    • Table 38 . A42MX36 Timing Characteristics (Nominal 5.0V Operation)
    • Table 39 . A42MX36 Timing Characteristics (Nominal 3.3V Operation) (Continued)
  • Pin Descriptions
    • Table 40 . Configuration of Unused I/Os
• Package Pin Assignments
  • 44-Pin PLCC
    • Figure 2-1 . 44-Pin PLCC
  • 68-Pin PLCC
    • Figure 2-2 . 68-Pin PLCC
  • 84-Pin PLCC
    • Figure 2-3 . 84-Pin PLCC
  • 100-Pin PQFP Package
    • Figure 2-4 . 100-Pin PQFP Package (Top View)
  • 160-Pin PQFP Package
    • Figure 2-5 . 160-Pin PQFP Package (Top View)
  • 208-Pin PQFP Package
    • Figure 2-6 . 208-Pin PQFP Package (Top View)
  • 240-Pin PQFP Package
    • Figure 2-7 . 240-Pin PQFP Package (Top View)
  • 80-Pin VQFP
    • Figure 2-8 . 80-Pin VQFP
  • 100-Pin VQFP Package
    • Figure 2-9 . 100-Pin VQFP Package (Top View)
  • 176-Pin TQFP Package
    • Figure 2-10 . 176-Pin TQFP Package (Top View)
  • 208-Pin CQFP
    • Figure 2-11 . 208-Pin CQFP (Top View)
  • 256-Pin CQFP
    • Figure 2-12 . 256-Pin CQFP (Top View)
  • 272-Pin BGA Package
    • Figure 2-13 . 272-Pin BGA Package (Top View)
• Datasheet Information
  • List of Changes
  • Datasheet Categories
    • Product Brief
    • Advanced
    • Unmarked (production)
    • Datasheet Supplement