Document Outline

• SX-A Family FPGAs
  • Leading-Edge Performance
  • Specifications
  • Features
    • Table 1 . SX-A Product Profile
  • Ordering Information
  • Device Resources
• General Description
  • Introduction
  • SX-A Family Architecture
    • Figure 1-1 . SX-A Family Interconnect Elements
    • Logic Module Design
    • Module Organization
      • Figure 1-2 . R-Cell
      • Figure 1-3 . C-Cell
    • Routing Resources
      • Figure 1-4 . Cluster Organization
      • Figure 1-5 . DirectConnect and FastConnect for Type 1 SuperClusters
      • Figure 1-6 . DirectConnect and FastConnect for Type 2 SuperClusters
    • Clock Resources
      • Table 1-1 . SX-A Clock Resources
      • Figure 1-7 . SX-A HCLK Clock Buffer
      • Figure 1-8 . SX-A Routed Clock Buffer
      • Figure 1-9 . SX-A QCLK Architecture
      • Figure 1-10 . A54SX72A Routed Clock and QCLK Buffer
  • Other Architectural Features
    • Technology
    • Performance
    • User Security
      • Figure 1-11 . FuseLock
    • I/O Modules
    • Power-Up/Down and Hot Swapping
      • Table 1-2 . I/O Features
      • Table 1-3 . I/O Characteristics for All I/O Configurations
      • Table 1-4 . Power-Up Time at which I/Os Become Active
    • Boundary-Scan Testing (BST)
      • Figure 1-12 . Device Selection Wizard
      • Table 1-5 . Reserve Pin Definitions
      • Table 1-6 . Boundary-Scan Pin Configurations and Functions
    • JTAG Instructions
      • Table 1-7 . JTAG Instruction Code
      • Table 1-8 . JTAG Instruction Code
    • Probing Capabilities
      • Table 1-9 . Device Configuration Options for Probe Capability (TRST Pin Reserved)
    • Design Considerations
      • Figure 1-13 . Probe Setup
    • Design Environment
  • Programming
  • Related Documents
    • Application Notes
    • Datasheets
  • Pin Description
• Detailed Specifications
  • Operating Conditions
    • Table 2-1 . Absolute Maximum Ratings
    • Table 2-2 . Recommended Operating Conditions
  • Typical SX-A Standby Current
    • Table 2-3 . Typical Standby Current for SX-A at 25C with VCCA = 2.5 V
    • Table 2-4 . Supply Voltages
  • Electrical Specifications
    • Table 2-5 . 3.3 V LVTTL and 5 V TTL Electrical Specifications
    • Table 2-6 . 2.5 V LVCMOS2 Electrical Specifications
  • PCI Compliance for the SX-A Family
    • Table 2-7 . DC Specifications (5 V PCI Operation)
    • Table 2-8 . AC Specifications (5 V PCI Operation)
    • Figure 2-1 . 5 V PCI V/I Curve for SX-A Family
    • Table 2-9 . DC Specifications (3.3 V PCI Operation)
    • Table 2-10 . AC Specifications (3.3 V PCI Operation)
    • Figure 2-2 . 3.3 V PCI V/I Curve for SX-A Family
    • Power Dissipation
      • Table 2-11 . CEQ Values for SX-A Devices
  • Thermal Characteristics
    • Introduction
      • Table 2-12 . Package Thermal Characteristics
    • Theta-JA
    • Theta-JC
    • Calculation for Heat Sink
  • SX-A Timing Model
    • Figure 2-3 . SX-A Timing Model
  • Sample Path Calculations
    • Hardwired Clock
    • Routed Clock
  • Output Buffer Delays
    • Figure 2-4 . Output Buffer Delays
  • AC Test Loads
    • Figure 2-5 . AC Test Loads
  • Input Buffer Delays
    • Figure 2-6 . Input Buffer Delays
  • C-Cell Delays
    • Figure 2-7 . C-Cell Delays
  • Cell Timing Characteristics
    • Figure 2-8 . Flip-Flops
  • Timing Characteristics
    • Critical Nets and Typical Nets
    • Long Tracks
    • Timing Derating
  • Temperature and Voltage Derating Factors
    • Table 2-13 . Temperature and Voltage Derating Factors
  • Timing Characteristics
    • Table 2-14 . A54SX08A Timing Characteristics (Continued)
    • Table 2-15 . A54SX08A Timing Characteristics
    • Table 2-16 . A54SX08A Timing Characteristics
    • Table 2-17 . A54SX08A Timing Characteristics
    • Table 2-18 . A54SX08A Timing Characteristics
    • Table 2-19 . A54SX08A Timing Characteristics
    • Table 2-20 . A54SX08A Timing Characteristics
    • Table 2-21 . A54SX16A Timing Characteristics (Continued)
    • Table 2-22 . A54SX16A Timing Characteristics
    • Table 2-23 . A54SX16A Timing Characteristics
    • Table 2-24 . A54SX16A Timing Characteristics
    • Table 2-25 . A54SX16A Timing Characteristics
    • Table 2-26 . A54SX16A Timing Characteristics
    • Table 2-27 . A54SX16A Timing Characteristics
    • Table 2-28 . A54SX32A Timing Characteristics (Continued)
    • Table 2-29 . A54SX32A Timing Characteristics
    • Table 2-30 . A54SX32A Timing Characteristics
    • Table 2-31 . A54SX32A Timing Characteristics
    • Table 2-32 . A54SX32A Timing Characteristics
    • Table 2-33 . A54SX32A Timing Characteristics
    • Table 2-34 . A54SX32A Timing Characteristics
    • Table 2-35 . A54SX72A Timing Characteristics (Continued)
    • Table 2-36 . A54SX72A Timing Characteristics (Continued)
    • Table 2-37 . A54SX72A Timing Characteristics (Continued)
    • Table 2-38 . A54SX72A Timing Characteristics (Continued)
    • Table 2-39 . A54SX72A Timing Characteristics
    • Table 2-40 . A54SX72A Timing Characteristics
    • Table 2-41 . A54SX72A Timing Characteristics
• Package Pin Assignments
  • 208-Pin PQFP
    • Figure 3-1 . 208-Pin PQFP (Top View)
  • 100-Pin TQFP
    • Figure 3-2 . 100-Pin TQFP
  • 144-Pin TQFP
    • Figure 3-3 . 144-Pin TQFP (Top View)
  • 176-Pin TQFP
    • Figure 3-4 . 176-Pin TQFP (Top View)
  • 329-Pin PBGA
    • Figure 3-5 . 329-Pin PBGA (Top View)
  • 144-Pin FBGA
    • Figure 3-6 . 144-Pin FBGA (Top View)
  • 256-Pin FBGA
    • Figure 3-7 . 256-Pin FBGA (Top View)
  • 484-Pin FBGA
    • Figure 3-8 . 484-Pin FBGA (Top View)
• Datasheet Information
  • List of Changes
  • Datasheet Categories
    • Product Brief
    • Advanced
    • Unmarked (production)
    • Datasheet Supplement
  • International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR)