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Электронный компонент: AD10242TZ/883B

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REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
AD10242
FEATURES
Two Matched ADCs with Input Signal Conditioning
Selectable Bipolar Input Voltage Range
( 0.5 V, 1.0 V, 2.0 V)
Full MIL-STD-883B Compliant
80 dB Spurious-Free Dynamic Range
Trimmed Channel-Channel Matching
APPLICATIONS
Radar Processing
Communications Receivers
FLIR Processing
Secure Communications
Any I/Q Signal Processing Application
The AD10242 operates with
5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion. Each channel is completely independent, allowing
operation with independent encode or analog inputs. The AD10242
also offers the user a choice of analog input signal ranges to mini-
mize additional signal conditioning required for multiple functions
within a single system. The heart of the AD10242 is the AD9042,
which is designed specifically for applications requiring wide
dynamic range.
The AD10242 is manufactured by Analog Devices on our
MIL-PRF-38534 MCM line and is completely qualified. Units
are packaged in a custom cofired ceramic 68-lead gull wing
package and specified for operation from 55
C to +125C.
Contact the factory for additional custom options including those
which allow the user to ac couple the ADC directly, bypassing
the front end amplifier section. Also see the AD9042 data sheet
for additional details on ADC performance.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 40 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals @ 80 dBc for 1 dBFS input signals.
3. Low power dissipation: <2 W off
5.0 V supplies.
4. User defined input amplitude.
5. Packaged in 68-lead ceramic leaded chip carrier.
PRODUCT DESCRIPTION
The AD10242 is a complete dual signal chain solution including
onboard amplifiers, references, ADCs, and output buffering pro-
viding unsurpassed total system performance. Each channel is
laser trimmed for gain and offset matching and provides channel-
to-channel crosstalk performance better than 80 dB. The AD10242
utilizes two each of the AD9632, OP279, and AD9042 in a cus-
tom MCM to gain space, performance, and cost advantages over
solutions previously available.
FUNCTIONAL BLOCK DIAGRAM
OP279
OP279
AD9042
AD9632
9
12
TIMING
A
IN
3
A
IN
2
A
IN
1
D11B (MSB)
D10B
D9B
D8B
D7B
D0B
(LSB)
D1B
D2B
D3B
D4B
D5B
D6B
D9A
D10A
D11A
(MSB)
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
ENC
AD10242
5
V
REF
OUTPUT BUFFERING
UNEG
UCOM
UPOS
OP279
OP279
AD9042
AD9632
7
12
TIMING
A
IN
2
A
IN
1
V
REF
OUTPUT BUFFERING
A
IN
3
UPOS
UNEG
UCOM
ENC
ENC
ENC
Dual, 12-Bit, 40 MSPS MCM A/D Converter
with Analog Input Signal Conditioning
a
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
REV. B
2
AD10242SPECIFICATIONS
Electrical Characteristics
(AV
CC
= 5 V; AV
EE
= 5.0 V; DV
CC
= 5 V; applies to each ADC unless otherwise noted.)
Test
Mil
AD10242BZ/TZ
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC ACCURACY
No Missing Codes
Full
VI
1, 2, 3
Guaranteed
Offset Error
25
C
I
1
0.5
0.05
+0.5
% FS
Full
VI
2, 3
2.0
1.0
+2.0
% FS
Offset Error Channel Match
Full
V
0.1
%
Gain Error
1
25
C
I
1
1.0
0.5
+1.0
% FS
Full
VI
2, 3
1.5
0.8
+1.5
% FS
Gain Error Channel Match
Full
V
0.1
%
ANALOG INPUT (A
IN
)
Input Voltage Range
A
IN
1
Full
I
0.5
V
A
IN
2
Full
I
1.0
V
A
IN
3
Full
I
2
V
Input Resistance
A
IN
1
Full
IV
12
99
100
101
A
IN
2
Full
IV
12
198
200
202
A
IN
3
Full
IV
12
396
400
404
Input Capacitance
2
25
C
IV
12
0
4.0
7.0
pF
Analog Input Bandwidth
3
Full
V
60
MHz
ENCODE INPUT
4, 5
Logic Compatibility
TTL/CMOS
Logic "1" Voltage
Full
I
1, 2, 3
2.0
5.0
V
Logic "0" Voltage
Full
I
1, 2, 3
0
0.8
V
Logic "1" Current (V
INH
= 5 V)
Full
I
1, 2, 3
625
800
A
Logic "0" Current (V
INL
= 0 V)
Full
I
1, 2, 3
400
300
A
Input Capacitance
25
C
V
12
7.0
pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
6
Full
VI
4, 5, 6
40
50
MSPS
Minimum Conversion Rate
6
Full
V
12
5
MSPS
Aperture Delay (t
A
)
25
C
V
1.0
ns
Aperture Delay Matching
25
C
V
2.0
ns
Aperture Uncertainty (Jitter)
25
C
V
1
ps rms
ENCODE Pulsewidth High
25
C
IV
12
12
10
ns
ENCODE Pulsewidth Low
25
C
IV
12
10
41
ns
Output Delay (t
OD
)
Full
IV
12
10
12
14
ns
SNR
7
Analog Input @ 1.2 MHz
25
C
V
68
dB
@ 4.85 MHz
25
C
I
4
63
66
dB
Full
II
5, 6
62
66
dB
@ 9.9 MHz
25
C
I
4
63
65
dB
Full
II
5, 6
62
65
dB
@ 19.5 MHz
25
C
I
4
60
63
dB
Full
II
5, 6
59
62
dB
SINAD
8
Analog Input @ 1.2 MHz
25
C
V
67
dB
@ 4.85 MHz
25
C
I
4
62
65
dB
Full
II
5, 6
61
64
dB
@ 9.9 MHz
25
C
I
4
60
64
dB
Full
II
5, 6
60
63
dB
@ 19.5 MHz
25
C
I
4
58
61
dB
Full
II
5, 6
58
60
dB
Test
Mil
AD10242BZ/TZ
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
9
Analog Input @ 1.2 MHz
25
C
I
81
dBFS
@ 4.85 MHz
25
C
I
4
70
80
dBFS
Full
II
5, 6
70
79
dBFS
@ 9.9 MHz
25
C
I
4
63
70
dBFS
Full
II
5, 6
63
69
dBFS
@ 19.5 MHz
25
C
I
4
60
67
dBFS
Full
II
5, 6
60
66
dBFS
TWO-TONE IMD REJECTION
10
F1, F2 @ 7 dBFS
Full
II
4, 5, 6
70
76
dBc
CHANNEL-TO-CHANNEL ISOLATION
11
25
C
IV
12
75
80
dB
TRANSIENT RESPONSE
25
C
V
10
ns
LINEARITY
Differential Nonlinearity
25
C
IV
12
0.3
1.0
LSB
(Encode = 20 MHz)
Full
IV
12
0.5
1.25
LSB
Integral Nonlinearity
25
C
V
0.3
LSB
(
Encode
= 20 MHz)
Full
V
0.5
LSB
OVERVOLTAGE RECOVERY TIME
12
V
IN
= 2.0
FS
Full
IV
12
50
100
ns
V
IN
= 4.0
FS
Full
IV
12
75
200
ns
DIGITAL OUTPUTS
Logic Compatibility
CMOS
Logic "1" Voltage
13
Full
I
1, 2, 3
3.5
4.2
V
Logic "0" Voltage
14
Full
I
1, 2, 3
0.45
0.65
V
Output Coding
Two's Complement
POWER SUPPLY
AV
CC
Supply Voltage
Full
VI
5.0
V
I (AV
CC
) Current
Full
V
260
mA
AV
EE
Supply Voltage
Full
VI
5.0
V
I (AV
EE
) Current
Full
V
55
mA
DV
CC
Supply Voltage
Full
VI
5.0
V
I (DV
CC
) Current
Full
V
25
mA
I
CC
(Total) Supply Current
Full
I
1, 2, 3
350
400
mA
Power Dissipation (Total)
Full
I
1, 2, 3
1.75
2.0
W
Power Supply Rejection Ratio (PSRR)
Full
I
7, 8
0.01
0.02
% FSR/% V
S
Pass Band Ripple to 10 MHz
Full
IV
12
0.2
dB
NOTES
1
Gain tests are performed on A
IN
3 over specified input voltage range.
2
Input capacitance specifications combine AD9632 die capacitance and ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
ENCODE driven by single-ended source;
ENCODE bypassed to ground through 0.01
F capacitor.
5
ENCODE may also be driven differentially in conjunction with
ENCODE; see Encoding the AD10242 section for details.
6
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
5%.
7
Analog Input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 40.0 MSPS.
8
Analog Input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 40.0 MSPS.
9
Analog Input signal equal 1 dBFS; SFDR is ratio of converter full scale to worst spur.
10
Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 10.0 MHz
100 kHz, 50 kHz f1 f2 300 kHz.
11
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel (A
IN
1).
12
Input driven to 2
and 4 A
IN
1 range for >4 clock cycles. Output recovers inband in specified time with Encode = 40 MSPS. No foldover guaranteed.
13
Outputs are sourcing 10
A.
14
Outputs are sinking 10
A.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
AD10242
3
REV. B
AD10242
4
REV. B
ABSOLUTE MAXIMUM RATINGS
1
Parameter
Min
Max
Unit
ELECTRICAL
V
CC
Voltage
0
7
V
V
EE
Voltage
7
0
V
Analog Input Voltage
V
EE
V
CC
V
Analog Input Current
10
+10
mA
Digital Input Voltage (ENCODE)
0
V
CC
V
ENCODE,
ENCODE Differential Voltage
4
V
Digital Output Current
40
+40
mA
ENVIRONMENTAL
2
Operating Temperature (Case)
55
+125
C
Maximum Junction Temperature
175
C
Lead Temperature (Soldering, 10 sec)
300
C
Storage Temperature Range (Ambient)
65
+150
C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances for "Z" package:
JC
= 11
C/W;
JA
= 30
C/W.
Table I. Output Coding
MSB LSB
Base 10
Input
0111111111111
2047
+FS
0000000000001
+1
0000000000000
0
0.0 V
1111111111111
1
1000000000000
2048
FS
EXPLANATION OF TEST LEVELS
Test Level
I
100% Production Tested.
II 100% production tested at 25
C, and sample tested at
specified temperatures. AC testing done on sample basis.
III Sample Tested Only.
IV Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI All devices are 100% production tested at 25
C; sample
tested at temperature extremes.
ORDERING GUIDE
M
odel
Temperature Range
Package Description
Package Option
AD10242BZ
40
C to +85C (Case)
68-Lead Ceramic Leaded Chip Carrier
Z-68A
AD10242TZ
55
C to +125C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
AD10242TZ/883B
55
C to +125C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
5962-9581501HXA
55
C to +125C (Case) 68-Lead Ceramic Leaded Chip Carrier Z-68A
AD10242/PCB
25
C
Evaluation Board with AD10242BZ
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD10242
5
REV. B
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SHIELD
Internal Ground Shield between Channels.
2, 5, 911, 2627
GNDA
A Channel Ground. A and B grounds should be connected as close to the device as possible.
3
UNEGA
Unipolar Negative.
4
UCOMA
Unipolar Common.
6
A
IN
A1
Analog Input for A Side ADC (Nominally
0.5 V).
7
A
IN
A2
Analog Input for A Side ADC (Nominally
1.0 V).
8
A
IN
A3
Analog Input for A Side ADC (Nominally
2.0 V).
12
UPOSA
Unipolar Positive.
13
AV
EE
Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V).
14
AV
CC
Analog Positive Supply Voltage (Nominally +5.0 V).
1516
NC
No Connect.
1725, 3133
D0AD11A
Digital Outputs for ADC A. D0 (LSB).
28
ENCODEA
ENCODE is complement of ENCODE.
29
ENCODEA
Data conversion initiated on rising edge of ENCODE input.
30
DV
CC
Digital Positive Supply Voltage (Nominally +5.0 V).
3435
NC
No Connect.
3642, 4549
D0BD11B
Digital Outputs for ADC B. D0 (LSB).
4344, 5354
GNDB
B Channel Ground. A and B grounds should be connected as close to the device
5861, 65, 68
as possible.
50
DV
CC
Digital Positive Supply Voltage (Nominally +5.0 V).
51
ENCODEB
Data conversion initiated on rising edge of
ENCODE input.
52
ENCODEB
ENCODE is complement of ENCODE.
55
UCOMB
Unipolar Common.
56
UNEGB
Unipolar Negative.
57
UPOSB
Unipolar Positive.
62
A
IN
B1
Analog Input for B Side ADC (Nominally
0.5 V).
63
A
IN
B2
Analog Input for B Side ADC (Nominally
1.0 V).
64
A
IN
B3
Analog Input for B Side ADC (Nominally
2.0 V).
66
AV
CC
Analog Positive Supply Voltage (Nominally +5.0 V).
67
AV
EE
Analog Negative Supply Voltage (Nominally 5.0 V or 5.2 V).
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27
43
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9
61
8
7
6
5
67 66 65 64 63 62
4
3
2
1
68
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
NC = NO CONNECT
AD10242
GNDA
GNDA
UPOSA
AV
EE
AV
CC
NC
NC
(LSB) D0A
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
GNDA
GNDA
ENCODEA
ENCODEA
DV
CC
D9A
D10A
(MSB) D11A
NC
NC
(LSB) D0B
D1B
D2B
D3B
D4B
D5B
D6B
GNDB
GNDB
GNDB
GNDB
UPOSB
UNEGB
UCOMB
GNDB
GNDB
ENCODEB
ENCODEB
DV
CC
D11B (MSB)
D10B
D9B
D8B
D7B
GNDB
GNDA
A
IN
A3
A
IN
A2
A
IN
A1
GNDA
UCOMA
UNEGA
GNDA
SHIELD
GNDB
AV
EE
AV
CC
GNDB
A
IN
B3
A
IN
B2
A
IN
B1
GNDB
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier