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Электронный компонент: AD10465PCB

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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD10465
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
Dual Channel, 14-Bit, 65 MSPS A/D Converter
with Analog Input Signal Conditioning
FEATURES
Dual, 65 MSPS Minimum Sample Rate
Channel-to-Channel Matching, 0.5% Gain Error
Channel-to-Channel Isolation, >90 dB
DC-Coupled Signal Conditioning Included
Selectable Bipolar Input Voltage Range
( 0.5 V, 1.0 V, 2.0 V)
Gain Flatness up to 25 MHz: < 0.2 dB
80 dB Spurious-Free Dynamic Range
Two's Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
1.75 W per Channel
Industrial and Military Grade
APPLICATIONS
Phased Array Receivers
Communications Receivers
FLIR Processing
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
FUNCTIONAL BLOCK DIAGRAM
VREF
DROUT
OUTPUT BUFFERING
TIMING
A
IN
A3 A
IN
A2 A
IN
A1
REF A
3
11
14
VREF
DROUT
A
IN
B2 A
IN
B1
14
A
IN
B3
ENC
ENC
D11A D12A D13A (MSB)
OUTPUT BUFFERING
D0B (LSB)
D1B
D3B
D2B
D4B
D5B
D6B D7B
D8B
TIMING
D9B
9
5
ENC
ENC
DRBOUT
D10B
D11B
D12B
D13B
REF B
D0A (LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
AD10465
DRAOUT
PRODUCT DESCRIPTION
The AD10465 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and fully
matched channel-to-channel performance. The module includes
two wide dynamic range AD6644 ADCs. Each AD6644 has a dc-
coupled amplifier front end including an AD8037 low distortion,
high bandwidth amplifier, providing a high input impedance
and gain, and driving the AD8138 single-to-differential ampli-
fier. The AD6644s have on-chip track-and-hold circuitry and
utilize an innovative multipass architecture to achieve 14-bit,
65 MSPS performance. The AD10465 uses innovative high-
density circuit design and laser-trimmed thin-film resistor networks
to achieve exceptional matching and performance, while still
maintaining excellent isolation and providing for significant
board area savings.
The AD10465 operates with
5.0 V for the analog signal condi-
tioning with a separate 5.0 V supply for the analog-to-digital
conversion and 3.3 V digital supply for the output stage. Each
channel is completely independent, allowing operation with
independent encode and analog inputs. The AD10465 also
offers the user a choice of analog input signal ranges to fur-
ther minimize additional external signal conditioning, while
still remaining general-purpose.
The AD10465 is packaged in a 68-lead Ceramic Gull Wing
package, footprint-compatible with the earlier generation AD10242
(12-bit, 40 MSPS) and AD10265 (12-bit, 65 MSPS). Manufac-
turing is done on Analog Devices, Inc. Mil-38534 Qualified
Manufacturers Line (QML) and components are available up to
Class-H (40
C to +85C). The AD6644 internal components
are manufactured on Analog Devices, Inc. high-speed comple-
mentary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 65 MSPS.
2. Input amplitude options, user configurable.
3. Input signal conditioning included; both channels matched
for gain.
4. Fully tested/characterized performance.
5. Footprint compatible family; 68-lead LCC.
REV. 0
2
AD10465SPECIFICATIONS
Test
Mil
AD10465AZ/BZ/QML-H
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
RESOLUTION
14
Bits
DC ACCURACY
No Missing Codes
Full
VI
1, 2, 3
Guaranteed
Offset Error
25
C
I
1
2.2
0.02
+2.2
% FS
Full
VI
2, 3
2.2
1.0
+2.2
% FS
Offset Error Channel Match
Full
V
1
1.0
+1
%
Gain Error
1
25
C
I
1
3
1.0
+1
% FS
Full
VI
2, 3
5
2.0
+5
% FS
Gain Error Channel Match
25
C
I
1
1.5
0.5
+1.5
%
Max
I
2
3
1.0
+3
%
Min
I
3
5
+5
%
ANALOG INPUT (A
IN
)
Input Voltage Range
A
IN
1
Full
V
0.5
V
A
IN
2
Full
V
1.0
V
A
IN
3
Full
V
2
V
Input Resistance
A
IN
1
Full
IV
12
99
100
101
A
IN
2
Full
IV
12
198
200
202
A
IN
3
Full
IV
12
396
400
404
Input Capacitance
2
25
C
IV
12
0
4.0
7.0
pF
Analog Input Bandwidth
3
Full
V
100
MHz
ENCODE INPUT (ENC,
ENC)
4
Differential Input Voltage
17
Full
IV
0.4
V p-p
Differential Input Resistance
25
C
V
10
k
Differential Input Capacitance
25
C
V
2.5
pF
SWITCHING PERFORMANCE
Maximum Conversion Rate
5
Full
VI
4, 5, 6
65
MSPS
Minimum Conversion Rate
5
Full
V
12
20
MSPS
Aperture Delay (t
A
)
25
C
V
1.5
ns
Aperture Delay Matching
25
C
IV
12
250
500
ps
Aperture Uncertainty (Jitter)
25
C
V
0.3
ps rms
ENCODE Pulsewidth High
25
C
IV
12
6.2
7.7
9.2
ns
ENCODE Pulsewidth Low
25
C
IV
12
6.2
7.7
9.2
ns
Output Delay (t
OD
)
Full
V
6.8
ns
Encode, Rising to Data Ready, Rising Delay (T
E_DR
)
Full
11.5
ns
SNR
6
Analog Input @ 4.98 MHz
25
C
V
70
dBFS
Analog Input @ 9.9 MHz
25
C
I
4
69
70
dBFS
Full
II
5, 6
68
70
dBFS
Analog Input @ 19.5 MHz
25
C
I
4
68
70
dBFS
Full
II
5, 6
67
70
dBFS
Analog Input @ 32.1 MHz
25
C
I
4
67
69
dBFS
Full
II
5, 6
67
69
dBFS
SINAD
7
Analog Input @ 4.98 MHz
25
C
V
70
dB
Analog Input @ 9.9 MHz
25
C
I
4
67.5
69
dB
Full
II
5, 6
67.5
69
dB
Analog Input @ 19.5 MHz
25
C
I
4
65
68
dB
Full
II
5, 6
65
68
dB
Analog Input @ 32.1 MHz
25
C
I
4
60
63
dB
Full
II
5, 6
58
61
dB
(AV
CC
= +5 V; AV
EE
= 5 V; DV
CC
= 3.3 V applies to each ADC unless otherwise noted.)
REV. 0
3
AD10465
Test
Mil
AD10465AZ/BZ/QML-H
Parameter
Temp
Level
Subgroup
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
8
Analog Input @ 4.98 MHz
25
C
V
85
dBFS
Analog Input @ 9.9 MHz
25
C
I
4
73
82
dBFS
Full
II
5, 6
70
82
dBFS
Analog Input @ 19.5 MHz
25
C
I
4
72
78
dBFS
Full
II
5, 6
70
78
dBFS
Analog Input @ 32.1 MHz
25
C
I
4
62
68
dBFS
Full
II
5, 6
60
66
dBFS
TWO-TONE IMD REJECTION
9
f
IN
= 10 MHz and 11 MHz
25
C
I
4
78
87
dBFS
f
1
and f
2
are 7 dB
II
5, 6
78
f
IN
= 31 MHz and 32 MHz
25
C
I
4
68
70
dBFS
f
1
and f
2
Are 7 dB
Full
II
5, 6
60
CHANNEL-TO-CHANNEL ISOLATION
10
25
C
IV
12
90
dB
TRANSIENT RESPONSE
25
C
V
15.3
ns
OVERVOLTAGE RECOVERY TIME
11
VIN = 2.0
f
S
Full
IV
12
40
100
ns
VIN = 4.0
f
S
Full
IV
12
150
200
ns
DIGITAL OUTPUTS
12
Logic Compatibility
CMOS
DV
CC
= 3.3 V
Logic "1" Voltage
Full
I
1, 2, 3
2.5
DV
CC
0.2
V
Logic "0" Voltage
Full
I
1, 2, 3
0.2
0.5
V
DV
CC
= 5 V
Logic "1" Voltage
Full
V
DV
CC
0.3
V
Logic "0" Voltage
Full
V
0.35
V
Output Coding
Two's Complement
POWER SUPPLY
AV
CC
Supply Voltage
13
Full
VI
4.85
5.0
5.25
V
I (AV
CC
) Current
Full
I
270
308
mA
AV
EE
Supply Voltage
13
Full
VI
5.25
5.0
4.75
V
I (AV
EE
) Current
Full
V
38
49
mA
DV
CC
Supply Voltage
13
Full
VI
3.135
3.3
3.465
V
I (DV
CC
) Current
Full
V
30
46
mA
I
CC
(Total) Supply Current per Channel
Full
I
1, 2, 3
338
403
mA
Power Dissipation (Total)
Full
I
1, 2, 3
3.5
3.9
W
Power Supply Rejection Ratio (PSRR)
Full
V
0.02
% FSR/% V
S
Passband Ripple to 10 MHz
V
0.1
dB
Passband Ripple to 25 MHz
V
0.2
dB
NOTES
1
Gain tests are performed on A
IN
1 input voltage range.
2
Input Capacitance spec. combines AD8037 die capacitance and ceramic package capacitance.
3
Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4
All ac specifications tested by driving
ENCODE and ENCODE differentially.
5
Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50%
5%.
6
Analog input signal power at 1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR
is reported in dBFS, related back to converter full power.
7
Analog input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS.
8
Analog input signal power swept from 1 dBFS to 60 dBFS; SFDR is ratio of converter full scale to worst spur.
9
Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
10
Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.
11
Input driven to 2
and 4 A
IN
1 range for > four clock cycles. Output recovers inband in specified time with Encode = 65 MSPS.
12
Digital output logic levels: DV
CC
= 3.3 V, C
LOAD
= 10 pF. Capacitive loads > 10 pF will degrade performance.
13
Supply voltage recommended operating range. AV
CC
may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AV
CC
= 5.0 V to 5.25 V.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. 0
AD10465
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10465 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
Parameter
Min Max Units
ELECTRICAL
V
CC
Voltage
0
7
V
V
EE
Voltage
7
0
V
Analog Input Voltage
V
EE
V
CC
V
Analog Input Current
10
+10
mA
Digital Input Voltage (ENCODE)
0
V
CC
V
ENCODE,
ENCODE Differential Voltage
4
V
Digital Output Current
10
+10
mA
ENVIRONMENTAL
2
Operating Temperature (Case)
40
+85
C
Maximum Junction Temperature
174
C
Lead Temperature (Soldering, 10 sec)
300
C
Storage Temperature Range (Ambient)
65
+150
C
NOTES
1
Absolute maximum ratings are limiting values applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is
not necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedance for "ES" package:
JC
= 2.2
C/W;
JA
= 24.3
C/W.
TEST LEVEL
I.
100% Production Tested.
II. 100% Production Tested at 25
C, and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample Tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at temperature at 25
C, sample
tested at temperature extremes.
ORDERING GUIDE
Model
Temperature Range
Package Description
AD10465AZ
25
C to +85C (Case) 68-Lead Ceramic Leaded Chip Carrier
AD10465BZ
40
C to +85C (Case) 68-Lead Ceramic Leaded Chip Carrier
5962-9961601HXA
40
C to +85C (Case) 68-Lead Ceramic Leaded Chip Carrier
AD10465/PCB
25
C
Evaluation Board with AD10465AZ
REV. 0
AD10465
5
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Function
1
SHIELD
Internal Ground Shield between channels.
2, 4, 5, 911
AGNDA
A Channel Analog Ground. A and B grounds should be connected as close to the device
as possible.
3
REF_A
A Channel Internal Voltage Reference.
6
A
IN
A1
Analog Input for A side ADC (nominally
0.5 V).
7
A
IN
A2
Analog Input for A side ADC (nominally
1.0 V).
8
A
IN
A3
Analog Input for A side ADC (nominally
2.0 V).
12
DRAOUT
Data Ready A Output.
13
AV
EE
Analog Negative Supply Voltage (nominally 5.0 V or 5.2 V).
14
AV
CC
Analog Positive Supply Voltage (nominally 5.0 V).
26, 27
DGNDA
A Channel Digital Ground.
1525, 3133
D0AD13A
Digital Outputs for ADC A. D0 (LSB).
28
ENCODEA
ENCODE is complement of ENCODE.
29
ENCODEA
Data conversion initiated on rising edge of ENCODE input.
30
DV
CC
Digital Positive Supply Voltage (nominally 5.0 V/3.3 V).
43, 44
DGNDB
B Channel Digital Ground.
3442, 4549
D0B-D13B
Digital Outputs for ADC B. D0 (LSB).
5354, 5761, 65, 68
AGNDB
B Channel Analog Ground. A and B grounds should be connected as close to the device
as possible.
50
DV
CC
Digital Positive Supply Voltage (nominally 5.0 V/3.3 V).
51
ENCODEB
Data conversion initiated on rising edge of ENCODE input.
52
ENCODEB
ENCODE is complement of ENCODE.
55
DRBOUT
Data Ready B Output.
56
REF_B
B Channel Internal Voltage Reference.
62
A
IN
B1
Analog Input for B side ADC (nominally
0.5 V).
63
A
IN
B2
Analog Input for B side ADC (nominally
1.0 V).
64
A
IN
B3
Analog Input for B side ADC (nominally
2.0 V).
66
AV
CC
Analog Positive Supply Voltage (nominally 5.0 V).
67
AV
EE
Analog Negative Supply Voltage (nominally 5.0 V or 5.2 V).
.
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier
10
11
12
13
14
15
16
17
18
19
20
22
23
24
25
26
21
27
43
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
9
61
8
7
6
5
68 67 66 65 64 63 62
4
3
2
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AD10465
AGNDB
AGNDB
AGNDB
AGNDB
REF B
DRBOUT
AGNDB
D12A
DGNDA
ENCODEA
ENCODEA
DV
CC
D11A
D13A(MSBA)
AGNDA
AGNDA
DRAOUT
AV
EE
D0A(LSBA)
D1A
D2A
D3A
D4A
D5A
AGNDB
ENCODEB
ENCODEB
DV
CC
D0B(LSBB)
D1B
D2B
D3B
AGNDA
AGNDA
A
IN
A3
AGNDA
AGNDA
REF
A
AV
EE
A
IN
B3
AV
CC
AGNDB
AGNDB
A
IN
A1
A
IN
A2
AGNDB
SHIELD
A
IN
B1
A
IN
B2
D4B
D5B
D6B
D7B
D8B
DGNDB
D6A
D7A
D8A
D9A
D10A
DGNDA
D13B(MSBB)
D12B
D11B
D10B
D9B
DGNDB
AV
CC