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Электронный компонент: AD12401KWSX

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12-Bit, 400 MSPS A/D Converter
AD12401
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.


One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Up to 400 MSPS sample rate
SNR of 63 dBFS @128 MHz
SFDR of 70 dBFS @128 MHz
VSWR of 1:1.5
Wideband ac-coupled input signal conditioning
Enhanced spurious-free dynamic range
Single-ended or differential encode signal
LVDS output levels
Twos complement output data
APPLICATIONS
Communications test equipment
Radar and satellite subsystems
Phased array antennas, digital beam
Multichannel, multimode receivers
Secure communications
Wireless and wired broadband communications
Wideband carrier frequency systems
GENERAL DESCRIPTION
The AD12401 is a 12-bit analog-to-digital converter (ADC)
with a transformer-coupled analog input and digital post-
processing for enhanced SFDR. The product operates at up
to 400 MSPS conversion rate with outstanding dynamic
performance in wideband carrier systems.
The AD12401 requires a 3.7 V analog supply and 3.3 V and
1.5 V digital supplies, and provides a flexible encode signal that
can be differential or single-ended. No external reference is
required.
The AD12401 package style is an enclosed 2.9" 2.6" 0.6"
module. Performance is rated over a 0C to 60C case
temperature range.
FUNCTIONAL BLOCK DIAGRAM
005649-001
ADC
A
DATA
READY
A
DATA
READY
B
DA0DA11
DR_EN
CLK DISTRIBUTION
AD12401
POST-
PROCESSING
ADC
B
A
IN
CLOCK DISTRIBUTION
DIVIDE BY 2
ENC
ENC
OROUT
DB0DB11
Figure 1.
PRODUCT HIGHLIGHTS
1.
Guaranteed sample rate up to 400 MSPS.
2.
Input signal conditioning with optimized dynamic
performance to 175 MHz.
3.
Additional performance options available (sample rates
> 400 MSPS or second Nyquist zone operation); contact
factory.
4.
Proprietary Advanced Filter Bank (AFBTM) digital post-
processing from V Corp Technologies, Inc.
AD12401
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications--Encode = 400 MSPS.................................. 4
AC Specifications--Encode = 360 MSPS.................................. 5
AC Specifications--Encode = 326 MSPS.................................. 6
Absolute Maximum Ratings............................................................ 7
Explanation of Test Levels ........................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 12
Typical Performance Characteristics ........................................... 14
Theory of Operation ...................................................................... 17
Time-Interleaving ADCs........................................................... 17
Analog Input ............................................................................... 17
Clock Input ................................................................................. 17
Digital Outputs ........................................................................... 18
Power Supplies ............................................................................ 18
Start-Up and RESET .................................................................. 18
DR_EN......................................................................................... 18
Overrange.................................................................................... 18
Thermal Considerations............................................................ 19
Package Integrity/Mounting Guidelines ................................. 19
AD12401 Evaluation Kit ........................................................... 20
Layout Guidelines........................................................................... 25
PCB Interface .............................................................................. 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
7/05--Revision 0: Initial Version
AD12401
Rev. 0 | Page 3 of 28
SPECIFICATIONS
DC SPECIFICATIONS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, 0C T
CASE
60C, unless otherwise noted.
Table 1.
AD12401-xxxKWS
Parameter
Case Temp
Test Level
Min
Typ
Max
Unit
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
Full
IV
Guaranteed
Offset Error
Full
I
-12
+12
LSB
Gain Error @ 10 MHz
Full
I
-10
+10
%FS
Differential Nonlinearity (DNL)
60C
V
0.3
LSB
Integral Nonlinearity (INL)
60C
V
0.5
LSB
TEMPERATURE DRIFT
Gain Error
60C
V
0.02
%/C
ANALOG INPUT (AIN)
Full-Scale Input Voltage Range
60C
V
3.2
V p-p
Flatness (10 MHz to 175 MHz)
Full
IV
0.5
1
dB
Input VSWR (50 )
(300 kHz to 175 MHz)
60C V
1.5
Analog Input Bandwidth
60C
V
480
MHz
POWER SUPPLY
1
Supply Voltage
VA Full
IV
3.6
3.8
V
VC Full
IV
3.2
3.4
V
VD Full
IV
1.45
1.55
V
Supply Current
I
VA
(VA = 3.7 V)
Full
I
0.95
1.2
A
I
VC
(VC = 3.3 V)
Full
I
400
500
mA
I
VD
(VD = 1.5 V)
Full
I
0.8
1.2
A
Total Power Dissipation
Full
I
5.7
6.8
W
ENCODE INPUTS
Differential Inputs (ENC, ENC)
Input Voltage
Full
IV
0.4
V
Input Resistance
60C
V
100
Input Capacitance
60C
V
35
pF
Common-Mode Voltage
60C
V
3
V
Single-Ended Inputs (ENC)
Input Voltage
Full
IV
0.4
2
V p-p
Input Resistance
60C
V
50
LOGIC INPUTS (RESET)
2
Logic 1 Voltage
Full
IV
2.0
V
Logic 0 Voltage
Full
IV
0.8
V
Source I
IH
60C
IV
3.4
6
mA
Sink I
IL
60C
IV
0.9
1
mA
LOGIC INPUTS (DR_EN)
Logic 1 Voltage
Full
IV
1.7
V
Logic 0 Voltage
Full
IV
0.7
V
Source I
IH
60C
IV
20
50
A
Sink I
IL
60C
IV
30
160
A
LOGIC OUTPUTS
(DRA, DRB, Output Bits)
3
Differential Output Voltage
Full
IV
247
350
454
mV
Output Common-Mode Voltage
Full
IV
1.125
1.25
1.375
V
Output High Voltage
60C
IV
1.602
V
Output Low Voltage
60C
IV
0.898
V
1
Tested using input frequency of 70 MHz. See Figure 17.
2
Refer to Table 7 for logic convention on all logic inputs.
3
Digital output logic levels: VC = 3.3 V, C
LOAD
= 8 pF, 2.5 V LVDS, R
T
= 100 .
AD12401
Rev. 0 | Page 4 of 28
AC SPECIFICATIONS
1
--ENCODE = 400 MSPS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, encode = 400 MSPS, 0C T
CASE
60C, unless otherwise noted.
Table 2.
AD12401-400KWS
Parameter
Case Temp
Test Level
Min
Typ
Max
Unit
DYNAMIC
PERFORMANCE
SNR
Analog Input 10 MHz
Full
I
62
64
dBFS
@ -1.0 dBFS 70 MHz
Full
I
61.5
63.5
dBFS
128
MHz
Full
I
60 63
dBFS
175 MHz
Full
I
60
62.5
dBFS
SINAD
2
Analog Input 10 MHz
Full
I
59
63.5
dBFS
@ -1.0 dBFS 70 MHz
Full
I
58.5
63
dBFS
128
MHz
Full
I
57.5 61.5
dBFS
175
MHz
Full
I
55 60
dBFS
Spurious-Free Dynamic Range
3
Analog Input 10 MHz
Full
I
69
85
dBFS
@ -1.0 dBFS 70 MHz
Full
I
69
80
dBFS
128
MHz
Full
I
66 72
dBFS
175
MHz
Full
I
62 68
dBFS
Image Spur
4
Analog Input 10 MHz
Full
I
60
75
dBFS
@ -1.0 dBFS 70 MHz
Full
I
60
72
dBFS
128
MHz
Full
I
60 66
dBFS
175
MHz
Full
I
57 63
dBFS
Offset Spur
4
Analog Input @ -1.0 dBFS
60C
V
65
dBFS
Two-Tone IMD
5
F1, F2 @ -6 dBFS
60C
V
-75
dBc
Analog Input
Frequency Range
Full
IV
10
175
MHz
Digital Input (DR_EN)
Minimum Time (Low)
Full
IV
5.0
ns
SWITCHING
SPECIFICATIONS
Conversion Rate
6
Full
IV
396 400 404 MSPS
Encode Pulse Width High (t
EH
)
1
60C V
1.25
ns
Encode Pulse Width Low (t
EL
)
1
60C V
1.25
ns
DIGITAL OUTPUT PARAMETERS
Valid Time (t
V
) Full
IV
3.9
ns
Propagation Delay (t
PD
) 60C
V
8.7
ns
Rise Time (t
R
) (20% to 80%)
60C
V
0.3
ns
Fall Time (t
F
) (20% to 80%)
60C
V
0.3
ns
DR Propagation Delay (t
EDR
) 60C
V
11.2
ns
Data to DR Skew (t
EDR
- t
PD
) 60C
V
2.5
ns
Pipeline Latency
7
Full IV
74
Cycles
Start-Up Time
Full
IV
2.9
44
87
ms
Postprocessing
Configuration
Time
Full
IV
2.8
sec
APERTURE DELAY (t
A
) 60C
V
2.3
ns
APERTURE UNCERTAINTY (Jitter, t
J
) 60C
V
0.4
ps
rms
1
All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating.
2
The image spur is included in the SINAD measurement.
3
The image spur is not included in the SFDR specification.
4
The image spur is at f
S
/2
A
IN
; the offset spur is at f
S
/2.
5
F1 = 70 MHz, F2 = 73 MHz.
6
Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 400 MSPS 1%.
7
Pipeline latency is exactly 74 cycles with an additional t
PD
required for data to emerge.
AD12401
Rev. 0 | Page 5 of 28
AC SPECIFICATIONS
1
--ENCODE = 360 MSPS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, encode = 360 MSPS, 0C T
CASE
60C, unless otherwise noted.
Table 3.
AD12401-360KWS
Parameter
Case Temp
Test Level
Min
Typ
Max
Unit
DYNAMIC
PERFORMANCE
SNR
Analog Input 10 MHz
Full
I
62
64
dBFS
@ -1.0 dBFS 70 MHz
Full
I
61.5
63.5
dBFS
128
MHz
Full
I
60 63
dBFS
SINAD
2
Analog Input 10 MHz
Full
I
59
63.5
dBFS
@ -1.0 dBFS 70 MHz
Full
I
58.5
63
dBFS
128
MHz
Full
I
57.5 61.5
dBFS
Spurious-Free Dynamic Range
3
Analog Input 10 MHz
Full
I
69
85
dBFS
@ -1.0 dBFS 70 MHz
Full
I
69
80
dBFS
128
MHz
Full
I
66 72
dBFS
Image Spur
4
Analog Input 10 MHz
Full
I
60
75
dBFS
@ -1.0 dBFS 70 MHz
Full
I
60
72
dBFS
128
MHz
Full
I
60 66
dBFS
Offset Spur
4
Analog Input @ -1.0 dBFS
60C
V
65
dBFS
Two-Tone IMD
5
F1, F2 @ -6 dBFS
60C
V
-75
dBc
Analog
Input
Frequency Range
Full
IV
10
160
MHz
Digital Input (DR_EN)
Minimum Time (Low)
Full
IV
5.6
ns
SWITCHING
SPECIFICATIONS
Conversion Rate
6
Full
IV
356 360 364 MSPS
Encode Pulse Width High (t
EH
)
1
60C V
1.38
ns
Encode Pulse Width Low (t
EL
)
1
60C V
1.38
ns
DIGITAL OUTPUT PARAMETERS
Valid Time (t
V
) Full
IV
4.5
ns
Propagation Delay (t
PD
) 60C
V
8.7
ns
Rise Time (t
R
) (20% to 80%)
60C
V
0.3
ns
Fall Time (t
F
) (20% to 80%)
60C
V
0.3
ns
DR Propagation Delay (t
EDR
) 60C
V
11.5
ns
Data to DR Skew (t
EDR
- t
PD
) 60C
V
2.8
ns
Pipeline Latency
7
Full IV
74
Cycles
Start-Up
Time
Full
IV
29 44 87 ms
Postprocessing
Configuration
Time
Full
IV
3.1
sec
APERTURE DELAY (t
A
) 60C
V
2.3
ns
APERTURE UNCERTAINTY (Jitter, t
J
) 60C
V
0.4
ps
rms
1
All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating.
2
The image spur is included in the SINAD specification.
3
The image spur is not included in the SFDR specification.
4
The image spur is at f
S
/2
A
IN
; the offset spur is at f
S
/2.
5
F1 = 70 MHz, F2 = 73 MHz.
6
Parts are tested with 360 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 360 MSPS 1%.
7
Pipeline latency is exactly 74 cycles with an additional t
PD
required for data to emerge.
AD12401
Rev. 0 | Page 6 of 28
AC SPECIFICATIONS
1
--ENCODE = 326 MSPS
VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, encode = 326 MSPS, 0C T
CASE
60C, unless otherwise noted.
Table 4.
AD12401-326KWS
Parameter
Case Temp
Test Level
Min
Typ
Max
Unit
DYNAMIC
PERFORMANCE
SNR
Analog Input 10 MHz
Full
I
62
64
dBFS
@ -1.0 dBFS 70 MHz
Full
I
61.5
63.5
dBFS
128
MHz
Full
I
60 63
dBFS
SINAD
2
Analog Input 10 MHz
Full
I
59
63.5
dBFS
@ -1.0 dBFS 70 MHz
Full
I
58.5
63
dBFS
128
MHz
Full
I
57.5 61.5
dBFS
Spurious-Free Dynamic Range
3
Analog Input 10 MHz
Full
I
69
85
dBFS
@ -1.0 dBFS 70 MHz
Full
I
69
80
dBFS
128
MHz
Full
I
66 72
dBFS
Image Spur
4
Analog Input 10 MHz
Full
I
60
75
dBFS
@ -1.0 dBFS 70 MHz
Full
I
60
72
dBFS
128
MHz
Full
I
60 66
dBFS
Offset Spur
5
Analog Input @ -1.0 dBFS
60C
V
65
dBFS
Two-Tone IMD
5
F1, F2 @ -6 dBFS
60C
V
-75
dBc
Analog
Input
Frequency Range
Full
IV
10
140
MHz
Digital Input (DR_EN)
Minimum Time (Low)
Full
IV
6.2
ns
SWITCHING
SPECIFICATIONS
Conversion Rate
6
Full
IV
323 326 329 MSPS
Encode Pulse Width High (t
EH
)
1
60C V
1.53
ns
Encode Pulse Width Low (t
EL
)
1
60C V
1.53
ns
DIGITAL OUTPUT PARAMETERS
Valid Time (t
V
) Full
IV
5.0
ns
Propagation Delay (t
PD
) 60C
V
8.7
ns
Rise Time (t
R
) (20% to 80%)
60C
V
0.3
ns
Fall Time (t
F
) (20% to 80%)
60C
V
0.3
ns
DR Propagation Delay (t
EDR
) 60C
V

11.8
ns
Data to DR Skew (t
EDR
- t
PD
) 60C
V
3.1
ns
Pipeline Latency
7
Full IV
74
Cycles
Start-Up
Time
Full
IV
29 44 87 ms
Postprocessing
Configuration
Time
Full
IV
3.4
sec
APERTURE DELAY (t
A
) 60C
V
2.3
ns
APERTURE UNCERTAINTY (Jitter, t
J
) 60C
V
0.4
ps
rms
1
All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating.
2
The image spur is included in the SINAD measurement.
3
The image spur is not included in the SFDR specification.
4
The image spur is at f
S
/2
A
IN
; the offset spur is at f
S
/2.
5
F1 = 70 MHz, F2 = 73 MHz.
6
Parts are tested with 326 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design
for encode 326 MSPS 1%.
7
Pipeline latency is exactly 74 cycles with an additional t
PD
required for data to emerge.
AD12401
Rev. 0 | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Value
VA to AGND
5 V
VC to DGND
4 V
VD to DGND
1.6 V max
Analog Input Voltage
6 V (dc)
Analog Input Power
18 dBm (ac)
Encode Input Voltage
6 V (dc)
Encode Input Power
12 dBm (ac)
Logic Inputs
-0.3 V to +4 V
Storage Temperature Range, Ambient
-65C to +150C
Operating Temperature Range Case
0C to 60C
EXPLANATION OF TEST LEVELS
Level Description
I
100% production tested.
II
100% production tested at 25C and sample tested at
specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI
100% production tested at 25C; guaranteed by design
and characterization testing for industrial temperature
range; 100% production tested at temperature
extremes for military devices.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD12401
Rev. 0 | Page 8 of 28
Table 6. Output Coding (Twos Complement)
Code A
IN
(V)
Digital Output
4095
+1.6
0111 1111 1111
. .
.
. .
.
. .
.
2048
0
0000 0000 0000
2047
-0.000781
1111 1111 1111
. .
.
. .
.
0
-1.6
1000 0000 0000
Table 7. Option Pin List with Necessary Associated Circuitry
Pin
Name
Active
High
Logic
Level
Type
Default
Level
Associated Circuitry
Within Part
RESET
Low
LVTTL
High
3.74 k Pull-Up
DR_EN High
LVTTL High
Weak Pull-Up (>16 k)
05649-002
ENCODE
100
100
100
100
3.3V
3.3V
PECL
DRIVER
ENCODE
Figure 2. Encode Equivalent Circuit

ENC
400MHZ
DRA
DRB
DRB
DRA
DATA OUT B
DR_EN
DATA OUT A
N 74
N 1
N 73
N
N
N + 2
N + 1
N + 1
N + 2
N + 3
N + 3
N + 5
N + 7
N + 4
N + 6
N + 8
1/f
S
t
EL
t
EH
1
1
74 CLOCK CYCLES
05649-003
1. DATA LOST DUE TO ASSERTION OF DR_EN. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID.
2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS
THE 50% POINT AND APPLY THE SAME TIMING INFORMATION.
3. THE DR_EN PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES.
THE DR_EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401. IF APPLIED
ASYNCHRONOUSLY, DR_EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION.
THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE DR_EN PIN IS SET HIGH AGAIN. DRA AND DRB RESUME
ON THE NEXT VALID DRA AFTER DR_EN IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS
PIN TO 3.3V THROUGH A 3.74k
RESISTOR OR LEAVE IT FLOATING.
NOTES
Figure 3. Timing Diagram
05649-004
t
PD
t
VD
ENC
DATA OUT
DR
ENC
DR
t
EDR
Figure 4. Highlighted Timing Diagram
AD12401
Rev. 0 | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05649-005
SAMTEC CONNECTOR
QTE-060-01-L-D-A-K-TR
BOTTOM VIEW
LEFT SIDE VIEW
AIN
ENC
BOARD
NOTE:
1. FOR MATING CONNECTOR, USE SAMTEC, INC.
PART NO. QSE-60-01-L-D-A-K.
INTEGRAL GROUND PLANE CONNECTIONS.
SECTION A = DGND, PINS 121124.
SECTION B = DGND, PINS 125128.
SECTION C = AGND, PINS 129132.
ENC
2-56 STUDS 4
JOHNSON SMA-50
CONNECT NO. 142-0711-821
END VIEW
TOP VIEW
PIN 1
AIN
ENC
ENC
DB0
DB0
DB2
DB2
DB4
DB4
DB6
DB6
DB8
DB8
DB10
DB10
OROUT
OROUT
DRB
DRB
DNC
DNC
VC
VC
DB1
DB1
DB3
DB3
DB5
DB5
DB7
DB7
DB9
DB9
DB11
DB11
DNC
DNC
DNC
DNC
DNC
RESET
VC
VC
1
DRA
DRA
DA0
DA0
DA2
DA2
DA4
DA4
DA6
DA6
DA8
DA8
DA10
DA10
DNC
DNC
VD
VD
VD
VD
DNC
LEAD/LAG
DA1
DA1
DA3
DA3
DA5
DA5
DA7
DA7
DA9
DA9
DA11
DA11
DNC
DNC
VD
VD
VD
VD
PIN 120
PIN 2
PIN 40
A
B
C
PIN 1
PIN 119
1
VA
VA
VA
VA
AGND
AGND
DNC
DNC
DNC
DNC
DNC
DNC
DNC
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VA
VA
VA
VA
AGND
AGND
DNC
DNC
DNC
DNC
DNC
DNC
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
1
PIN 80
PIN 79
PIN 39
Figure 5. Pin Configuration
AD12401
Rev. 0 | Page 10 of 28
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
VC
Digital Supply, 3.3 V.
5
RESET
LVTTL. 0 = device reset. Minimum width = 200 ns. Device resumes operation after 600 ms maximum.
6 to 9, 11, 13 ,15, 49 to 52,
79, 96 to 108
DNC
Do Not Connect.
10
DRB
Channel B Data Ready. Complement output.
12
DRB
Channel B Data Ready. True output.
14
OROUT
Overrange. Complement output.
16
OROUT
Overrange. True Output 1 = overranged, 0 = normal operation.
17
DB11
Channel B Data Bit 11. Complement output bit.
18
DB10
Channel B Data Bit 10. Complement output bit.
19
DB11
Channel B Data Bit 11. True output bit.
20
DB10
Channel B Data Bit 10. True output bit.
21
DB9
Channel B Data Bit 9. Complement output bit.
22
DB8
Channel B Data Bit 8. Complement output bit.
23
DB9
Channel B Data Bit 9. True output bit.
24
DB8
Channel B Data Bit 8. True output bit.
25
DB7
Channel B Data Bit 7. Complement output bit.
26
DB6
Channel B Data Bit 6. Complement output bit.
27
DB7
Channel B Data Bit 7. True output bit.
28
DB6
Channel B Data Bit 6. True output bit.
29
DB5
Channel B Data Bit 5. Complement output bit.
30
DB4
Channel B Data Bit 4. Complement output bit.
31
DB5
Channel B Data Bit 5. True output bit.
32
DB4
Channel B Data Bit 4. True output bit.
33
DB3
Channel B Data Bit 3. Complement output bit.
34
DB2
Channel B Data Bit 2. Complement output bit.
35
DB3
Channel B Data Bit 3. True output bit.
36
DB2
Channel B Data Bit 2. True output bit.
37
DB1
Channel B Data Bit 1. Complement output bit.
38
DB1
Channel B Data Bit 0. Complement output bit. DB0 is LSB.
39
DB1
Channel B Data Bit 1. True output bit.
40
DB0
Channel B Data Bit 0. True output bit. DB0 is LSB.
41 to 48
VD
Digital Supply, 1.5 V.
53
DA11
Channel A Data Bit 11. Complement output bit.
54
DA10
Channel A Data Bit 10. Complement output bit.
55
DA11
Channel A Data Bit 11. True output bit.
56
DA10
Channel A Data Bit 10. True output bit.
57
DA9
Channel A Data Bit 9. Complement output bit.
58
DA8
Channel A Data Bit 8. Complement output bit.
59
DA9
Channel A Data Bit 9. True output bit.
60
DA8
Channel A Data Bit 8. True output bit.
61
DA7
Channel A Data Bit 7. Complement output bit.
62
DA6
Channel A Data Bit 6. Complement output bit.
63
DA7
Channel A Data Bit 7. True output bit.
64
DA6
Channel A Data Bit 6. True output bit.
65
DA5
Channel A Data Bit 5. Complement output bit.
66
DA4
Channel A Data Bit 4. Complement output bit.
67
DA5
Channel A Data Bit 5. True output bit.
68
DA4
Channel A Data Bit 4. True output bit.
69
DA3
Channel A Data Bit 3. Complement output bit.
70
DA2
Channel A Data Bit 2. Complement output bit.
71
DA3
Channel A Data Bit 3. True output bit.
72
DA2
Channel A Data Bit 2. True output bit.
73
DA1
Channel A Data Bit 1. Complement output bit.
74
DA0
Channel A Data Bit 0. Complement output bit. DA0 is LSB.
75
DA1
Channel A Data Bit 1. True output bit.
AD12401
Rev. 0 | Page 11 of 28
Pin No.
Mnemonic
Description
76
DA0
Channel A Data Bit 0. True output bit. DA0 is LSB.
77
DR_EN
Data Ready Enable, Typically DNC. See the DR_EN section.
78
DRA
Channel A Data Ready. Complement output.
80
DRA
Channel A Data Ready. True output.
81 to 95, 109 to 112,
129 to 132
1
AGND Analog
Ground.
113 to 120
VA
Analog Supply, 3.7 V.
121 to 128
1
DGND Digital
Ground.
1
Internal ground plane connections: Section A = DGND, Pin 121 to Pin 124; Section B = DGND, Pin 125 to Pin 128; Section C = AGND, Pin 129 to Pin 132.
AD12401
Rev. 0 | Page 12 of 28
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point on the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Analog Input VSWR (50 )
VSWR is a ratio of the transmitted and reflected signals. The
VSWR can be related to input impedance
= (Z
L
- Z
S
)/(Z
L
+ Z
S
)
where:
Z
L
= actual load impedance.
Z
S
= reference impedance.
VSWR = (1 - ||)/(1 +||)
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Distortion, Image Spur
The ratio of the rms signal amplitude to the rms signal ampli-
tude of the image spur, reported in dBFS. The image spur, a
result of gain and phase errors between two time-interleaved
conversion channels, is located at f
S
/2 f
AIN
.
Distortion, Offset Spur
The ratio of the rms signal amplitude to the rms signal ampli-
tude of the offset spur, reported in dBFS. The offset spur, a
result of offset errors between two time-interleaved conversion
channels, is located at f
S
/2.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
02
6
dB
76
1
.
.
SNR
ENOB
MEASURED
-
=
Encode Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time the ENCODE
pulse should be left in Logic 1 state to achieve rated perform-
ance; pulse width low is the minimum time the ENCODE pulse
should be left in low state.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
POWER
Full-Scale
= 10 log ((V
2
Full-Scale
rms
)/(|Z
INPUT
| 0.001))
Full-Scale Input Voltage Range
The maximum peak-to-peak input signal magnitude that results
in a full-scale response, 0 dBFS on a single-tone input signal
case. Any magnitude increase from this value results in an
overrange condition.
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBFS.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBFS.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Maximum Conversion Rate
The maximum ENCODE rate at which the image spur
calibration degrades no more than 1 dB (when the image
spur is 70 dB).
Minimum Conversion Rate
The minimum ENCODE rate at which the image spur
calibration degrades no more than 1 dB (when the image
spur is 70 dB).
Offset Error
The dc offset imposed on the input signal by the ADC, reported
in LSB (codes).
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE (or zero crossing of a single-ended ENCODE).
Pipeline Latency
The number of clock cycles the output data lags the correspond-
ing clock cycle.
Power Supply Rejection Ratio (PSRR)
The ratio of power supply voltage change to the resulting ADC
output voltage change.
AD12401
Rev. 0 | Page 13 of 28
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc and image spur.
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral compo-
nents, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component, except the image spur.
The peak spurious component may or may not be an harmonic.
It can be reported in dBc (that is, degrades as signal level is
lowered) or dBFS (always related back to converter full-scale).
Total Noise
Calculated as
)
(
.
Z
V
Signal
SNR
FS
NOISE
dBc
dBm
10
dBFS
10
001
0
-
-
=
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value of the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale. This value includes both thermal and quantization
noise.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product; reported
in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It can be reported in dBc
(that is, degrades as signal level is lowered) or in dBFS (always
related back to converter full-scale).
AD12401
Rev. 0 | Page 14 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
1
05649-006
FREQUENCY (MHz)
dB
SNR = 63.26dB
SFDR = 76.77dBc
SINAD = 62.97dB
IMAGE SPUR = 76.69dBc
2
3
4
5
6
X
N
Figure 6. FFT: f
S
= 400 MSPS, A
IN
= 10.123 MHz @ 1.0 dBFS;
X = Image Spur, N = Interleaved Offset Spur
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
05649-007
FREQUENCY (MHz)
dB
1
2
3
5
6
X
4
N
SNR = 62.61dB
SFDR = 78.03dBc
SINAD = 62.41dB
IMAGE SPUR = 86.28dBc
Figure 7. FFT: f
S
= 400 MSPS, A
IN
= 70.123 MHz @ 1.0 dBFS;
X = Image Spur, N = Interleaved Offset Spur
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
05649-008
FREQUENCY (MHz)
dB
N
5
2
1
4
X
6
3
SNR = 61.54dB
SFDR = 74.03dBc
SINAD = 60.92dB
IMAGE SPUR = 75.09dBc
Figure 8. FFT: f
S
= 400 MSPS, A
IN
= 128.123 MHz @ 1.0 dBFS;
X = Image Spur, N = Interleaved Offset Spur
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
05649-009
FREQUENCY (MHz)
dB
N
1
6
3
4
5
2
X
SNR = 60.74dB
SFDR = 71.57dBc
SINAD = 60.29dB
IMAGE SPUR = 82.52dBc
Figure 9. FFT: f
S
= 400 MSPS, A
IN
= 175.123 MHz @ 1.0 dBFS;
X = Image Spur, N = Interleaved Offset Spur
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
05649-010
FREQUENCY (MHz)
dB
12
2F2

F1
F2 + F1
2F1

F2
2F2 +
F1
2F1 +
F2
F2

F1
Figure 10. Two-Tone Intermodulation Distortion
(25.1 MHz and 28.1 MHz; f
S
= 400 MSPS);
X = Image Spur, N = Interleaved Offset Spur
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
05649-011
FREQUENCY (MHz)
dB
12
F2 + F1
F2 + F1
2F2
F1
2F2 +
F1
2F1 +
F2
2F1
F2
Figure 11. Two-Tone Intermodulation Distortion
(70.1 MHz and 73.1 MHz; f
S
= 400 MSPS);
X = Image Spur, N = Interleaved Offset Spur
AD12401
Rev. 0 | Page 15 of 28
0
10
20
30
40
50
60
70
80
90
100
110
0
20
40
60
80
100
120
140
160
180
200
05649-012
FREQUENCY (MHz)
dB
12
F2

F1
F2 + F1
2F1 +
F2
2F2 +
F1
2F1
F2
2F2
F1
Figure 12. Two-Tone Intermodulation Distortion
(172.1 MHz and 175.1 MHz; f
S
= 400 MSPS), SFDR = 70 dBc;
X = Image Spur, N = Interleaved Offset Spur
05649-040
FREQUENCY (MHz)
GAIN (
d
B)
0.4
0.5
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
10.7
35.0
59.3 83.6
108
132
157
181
205
229
Figure 13. Interleaved Gain Flatness
05649-041
ANALOG INPUT LEVEL (dB)
DISTORTION (
d
BFS)
60
95
90
85
80
75
70
65
100
0
50
40
30
20
10
70
60
THIRD HARMONIC
SECOND HARMONIC
IMAGE SPUR
Figure 14. Second/Third Harmonics and Image Spur vs. Analog Input Level;
f
S
= 400 MSPS, A
IN
= 70 MHz
05649-042
ANALOG INPUT FREQUENCY (MHz)
HARMONICS
(dBc
)
60
65
70
75
80
85
90
95
0
20
40
60
80
100
120
140
160
180
SECOND HARMONIC
THIRD HARMONIC
IMAGE SPUR
Figure 15. Harmonics vs. Analog Input Frequency
64.5
64.0
63.5
63.0
62.5
62.0
61.5
61.0
60.5
60.0
59.5
200
150
100
50
0
ANALOG INPUT FREQUENCY (MHz)
S
NR (dBFS
)
05649-016
Figure 16. SNR vs. Analog Input Frequency
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
80
60
40
20
0
INPUT FREQUENCY (MHz)
V
D
S
U
P
P
LY
CURRE
NT (A)
180
160
140
120
100
200
05649-017
Figure 17. VD Supply Current vs. A
IN
Frequency
AD12401
Rev. 0 | Page 16 of 28
05649-043
ANALOG INPUT FREQUENCY
A
N
A
L
OG IN
PU
T LEVEL
4.78
5.20
4.36
3.94
3.52
3.10
2.68
2.26
1.84
1.42
1.00
0.100 0.530 0.960 1.390 1.820 2.250 2.680 3.110 3.540 3.970 4.400
Figure 18. Low Frequency Gain Flatness
AD12401
Rev. 0 | Page 17 of 28
THEORY OF OPERATION
The AD12401 uses two high speed, 12-bit ADCs in a time-
interleaved configuration to double the sample rate, while
maintaining a high level of dynamic range performance. The
digital output of each ADC channel is calibrated using a
proprietary digital postprocessing technique, Advanced Filter
Bank (AFB). AFB is implemented using a state-of-the-art field
programmable gate array (FPGA) and provides a wide
bandwidth and wide temperature match for any gain, phase,
and clock timing errors between each ADC channel.
TIME-INTERLEAVING ADCS
When two ADCs are time-interleaved, gain and/or phase
mismatches between each channel produce an image spur
at f
S
/2 - f
AIN
and an offset spur as shown in Figure 19. These
mismatches can be the result of any combination of device
tolerance, temperature, and frequency deviations.
.
120
110
100
90
80
70
60
50
40
30
20
10
0
05649-018
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
dB
IMAGE SPUR
1
2
3
4
5
6
N
OFFSET SPUR
X
Figure 19. Image Spur Due to Mismatches Between Two Interleaved ADCs
(No AFB Digital Postprocessing)
Figure 20 shows the performance of a similar converter with
on-board AFB postprocessing implemented. The 44 dBFS
image spur has been reduced to 77 dBFS and, as a result,
the dynamic range of this time-interleaved ADC is no longer
limited by the channel matching.
05649-019
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (MHz)
dB
120
110
100
90
80
70
60
50
40
30
20
10
0
IMAGE SPUR
OFFSET SPUR
1
2
3
4
5
6
N
X
Figure 20. AD12401 with AFB Digital Postprocessing
The relationship between image spur and channel mismatches
is captured in Table 9 for specific conditions.
Table 9. Image Spur vs. Channel Mismatch
Gain Error (%)
Aperture Delay Error (ps)
Image Spur
(dBc)
1 15
40
0.25 2.7
54
0.2 1.1
62
0.025 0.5
70
For a more detailed description of time-interleaving in ADCs
and a design example using the AD12401, refer to "Advanced
Digital Postprocessing Techniques Enhance Performance in
Time Interleaved ADC Systems," published in the August, 2003
edition of Analog Dialogue. This article can be found at
http://www.analog.com/analogDialogue.
ANALOG INPUT
The AD12401 analog input is ac-coupled using a proprietary
transformer front-end circuit that provides 1 dB of gain flatness
over the first Nyquist zone and a 3 dB bandwidth of 480 MHz.
This front-end circuit provides a VSWR of 1.5 (50 ) over the
first Nyquist zone, and the typical full-scale input is 3.2 V p-p.
The Mini-Circuits HELA-10 amplifier module can be used to
drive the input at these power levels.
CLOCK INPUT
The AD12401 requires a 400 MSPS encode that is divided
by 2 and distributed to each ADC channel, 180 out of phase
from each other. Internal ac-coupling and bias networks
provide the framework for flexible clock input requirements
that include single-ended sine wave, single-ended PECL, and
differential PECL. While the AD12401 is tested and calibrated
using a single-ended sine wave, properly designed PECL
circuits that provide fast slew rates (>1 V/ns) and minimize
ringing result in comparable dynamic range performance.
Aperture jitter and harmonic content are two major factors
to consider when designing the input clock circuit for the
AD12401. The relationship between aperture jitter and SNR
can be characterized using the following equation. The equation
assumes a full-scale, single-tone input signal.
SNR =
(
)


+
+
+
-
2
2
2
2
2
2
2
1
5
1
1
0
20
log
20
N
NOISErms
N
JRMS
A
V
.
t
f
where:
f
A
= input frequency.
t
JRMS
= aperture jitter.
N = ADC resolution (bits).
= ADCDNL (LSB).
V
NOISE
= ADC input noise (LSBrms).
AD12401
Rev. 0 | Page 18 of 28
Figure 21 displays the application of this relationship to a full-
scale, single-tone input signal on the AD12401, where the DNL
was assumed to be 0.4 LSB, and the input noise was assumed to
be 0.8 LSBrms. The vertical marker at 0.4 ps displays the SNR
at the jitter level present in the AD12401 evaluation system,
including the jitter associated with the AD12401 itself.
57
58
59
60
61
62
63
64
65
05649-020
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
APERTURE JITTER (ps rms)
S
NR (dB)
A
IN
= 10MHz
A
IN
= 65MHz
A
IN
= 128MHz
A
IN
= 180MHz
Figure 21. SNR vs. Aperture Jitter
In addition to jitter, the harmonic content of the single-ended
sine wave clock sources must be controlled. The clock source
used in the test and calibration process has an harmonic per-
formance that is better than 60 dBc. Also, when using PECL or
other square-wave clock sources, unstable behavior, such as
overshoot and ringing, can affect phase matching and degrade
the image spur performance.
DIGITAL OUTPUTS
The AD12401's digital postprocessing circuit provides two
parallel, 12-bit, 200 MSPS data output buses. By providing two
output busses that operate at one half the conversion rate, the
AD12401 eliminates the need for large, expensive, high power
demultiplexing circuits. The output data format is twos com-
plement, maintaining the standard set by other high speed
ADCs, such as the AD9430 and AD6645. Data-ready signals
are provided for facilitating proper timing in the data capture
circuit.
POWER SUPPLIES
The AD12401 requires three different supply voltages: a 1.5 V
supply for the digital postprocessing circuit, a 3.3 V supply to
facilitate digital I/O through the system, and a 3.8 V supply for
the analog conversion and clock distribution circuits. The
AD12401 incorporates two key features that result in solid
PSRR performance. First, on-board linear regulators are used
to provide an extra level of power supply rejection for the
analog circuits. The linear regulator used to supply the ADCs
provides an additional 60 dB of rejection at 100 kHz. Second,
in order to address higher frequency noise (where the linear
regulators' rejection degrades), the AD12401 incorporates high
quality ceramic decoupling capacitors.
While this product has been designed to provide good PSRR
performance, system designers need to be aware of the risks
associated with switching power supplies and consider using
linear regulators in their high speed ADC systems. Switching
power supplies typically produces both conducted and radiated
energy that result in common-/differential-mode EMI currents.
Any system that requires 12-bit performance has very little
room for errors associated with power supply EMI. For exam-
ple, a system goal of 74 dB dynamic range performance on the
AD12401 requires noise currents that are less than 4.5 A and
noise voltages of less than 225 V in the analog input path.
START-UP AND RESET
The AD12401's FPGA configuration is stored in the on-board
EPROM and loaded into the FPGA when power is applied to
the device. The RESET pin (active low) allows the user to reload
the FPGA in case of a low digital supply voltage condition or a
power supply glitch. Pulling the RESET pin low pulls the data
ready and output bits high until the FPGA is reloaded. The
RESET pin should remain low for a minimum of 200 ns. On
the rising edge of the reset pulse, the AD12401 starts loading
the configuration into the FPGA. The reload process requires
a maximum of 87 ms to complete. Valid signals on the data
ready pins indicate the reset process is complete. Also, system
designers must be aware of the thermal conditions of the
AD12401 at startup. If large thermal imbalances are present,
the AD12401 may require additional time to stabilize before
providing specified image spur performance.
DR_EN
The DR_EN pin is used to synchronize the collection of data
into external buffer memories. DR_EN must be held low for a
minimum amount of time (see AC Specifications tables for each
encode rate) to ensure correct operation. The function shuts off
DRA and DRB until the DR_EN pin is set high again. DRA and
DRB resumes on the next valid DRA after DR_EN is released.
If this feature is not required, tie this pin to 3.3 V through
a 3.74 k.
OVERRANGE
The differential OROUT pins are used to determine if the
AD12401 input is overranged. OROUT timing is identical to
the Channel B data. If the OROUT pin is high, then the
Channel B data coincident with the overrange indication or the
Channel A data immediately preceding it resulted from an
overrange input. If the OROUT pin is low, the operation is
normal.
AD12401
Rev. 0 | Page 19 of 28
THERMAL CONSIDERATIONS
The module is rated to operate over a case temperature of 0C
to 60C. To maintain the tight channel matching and reliability
of the AD12401, care must be taken to ensure that proper
thermal and mechanical considerations have been made and
addressed to ensure case temperature is kept within this range.
Each application requires evaluation of the thermal manage-
ment as applicable to the system design. This section provides
information that should be used in the evaluation of the
AD12401's thermal management for each specific use.
In addition to the radiation of heat into its environment, the
AD12401 module enables the flow of heat through the
mounting studs and standoffs as they contact the motherboard.
As described in the Package Integrity/Mounting Guidelines
section, the module should be secured to the motherboard
using 2-56 nuts (washer use is optional). The torque on the nuts
should not exceed 32-inch ounces. Using a thermal grease at the
standoffs results in better thermal coupling between the board
and module. Depending on the ambient conditions, airflow can
be necessary to ensure the components in the module do not
exceed their maximum operating temperature. For reliability,
the most sensitive component has a maximum junction
temperature rating of 125C.
Figure 22 and Figure 23 provide a basic guideline for two key
thermal management decisions: the use of thermal interface
material between the module bottom cover/mother board and
airflow. Figure 21 characterizes the typical thermal profile of an
AD12401 that is not using thermal interface material. Figure 22
provides the same information for a configuration that uses
gap-filling thermal interface material. In this case, Thermagon
T-flex 600 Series
TM
, 0.040" thickness was used. These profiles
show that the maximum die temperature is reduced by
approximately 2C when thermal interface material is used.
Figure 22 and Figure 23 also provide a guideline for
determining the airflow requirements for given ambient condi-
tions. For example, a goal of 120C die temperature in a 40C
ambient environment without the use of thermal interface
material requires an airflow of 100 LFM.
From a channel-matching perspective, the most important
consideration is external thermal influences. It is possible for
thermal imbalances in the end application to adversely affect
the dynamic performance. Due to the temperature dependence
of the image spur, substantial deviation from the factory cali-
bration conditions can have a detrimental effect. Unbalanced
thermal influences can cause gradients across the module, and
performance degradation may result. Examples of unbalanced
thermal influences may include large heat dissipating elements
near one side of the AD12401, or obstructed airflow that does
not flow uniformly across the module. The thermal sensitivity
of the module can be affected by a change in thermal gradient
across the module of 2C.
05649-021
AIRFLOW CONDITION
TE
MP
E
RATURE
(
C)
20
30
40
50
60
70
80
90
100
110
TYPICAL JUNCTION
CASE
AMBIENT
NO AIRFLOW
100 LFM
300 LFM
Figure 22. Typical Temperature vs. Airflow with No Module/Board
Interface Material (Normalized to 60C Module Case Temperature)
TYPICAL JUNCTION
CASE
AMBIENT
05649-022
AIRFLOW CONDITION
TE
MP
E
RATURE
(
C)
20
30
40
50
60
70
80
90
100
110
NO AIRFLOW
100 LFM
300 LFM
Figure 23. Typical Temperature vs. Airflow with T-flex Module/Board
Interface Material (Normalized to 60C Module Case Temperature Ambient)
PACKAGE INTEGRITY/MOUNTING GUIDELINES
The AD12401 is a printed circuit board (PCB)-based module
designed to provide mechanical stability and support the
intricate channel-to-channel matching necessary to achieve
high dynamic range performance. The module should be
secured to the motherboard using 2-56 nuts (washer use is
optional). The torque on the nuts should not exceed 32-inch
ounces.
The SMA edge connectors (AIN and ENC/ENC) are surface
mounted to the board in order to achieve minimum height of
the module. When attaching and routing the cables, one must
ensure they are stress-relieved and do not apply stress to the
SMA connector/board. The presence of stress on the cables may
degrade electrical performance and mechanical integrity of the
module. In addition to the routing precautions, the smallest
torque necessary to achieve consistent performance should be
used to secure the system cable to the AD12401's SMA
connectors. The torque should never exceed 5-inch pounds.
AD12401
Rev. 0 | Page 20 of 28
Any disturbances to the AD12401 structure, including
removing the covers or mounting screws, invalidates the
calibration and results in degraded performance. Refer to the
Outline Dimensions section for mounting stud dimensions.
Refer to Figure 37 for PCB interface locations. Mounting stud
length typically accommodates a PCB thickness of 0.093".
Consult the factory if board thickness requirements exceed this
dimension.
AD12401 EVALUATION KIT
The AD12401/KIT offers an easy way to evaluate the AD12401.
The AD12401/KIT includes the AD12401 mounted on an
adapter card, the AD12401 evaluation board, the power supply
cables, a 225 MHz buffer memory FIFO board, and the Dual
Analyzer software. The user must supply a clock source, an
analog input source, a 1.5 V power supply, a 3.3 V power supply,
a 5 V power supply, and a 3.8 V power supply. The clock source
and analog input source connect directly to the AD12401. The
power supply cables (included) and a parallel port cable (not
included) connect to the evaluation board. The AD12401 works
on the same evaluation board as the AD12400 and the
AD12500: GS08054.
Power Connector
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks).
Table 10. Power Connector
Supply Description
VA 3.7 V
Analog supply for the ADC (950 mA typ)
VC 3.3 V
Digital supply for the ADC outputs (400 mA typ)
VD 1.5 V
1
Digital supply for the FPGA (1.25 A max, 0.7 A typ)
VB 5.0 V
Digital supply for the buffer memory board
(400 mA typ)
1
The power supply cable has an approximately 100 mV drop. The VD supply
current is dependent on the analog input frequency. Refer to Figure 17.
Analog Input
The analog input source connects directly to an SMA on the
AD12401.
Encode
The single-ended or differential encode signal connects directly
to SMA connector(s) on the AD12401. A single-ended sine
wave at 10 dBm connected to the encode SMA is recommended.
A low jitter clock source (<0.5 ps) is recommended to properly
evaluate the AD12401.
Data Outputs
The AD12401xxxKWS digital outputs are available at the
80-pin connector, P2, on the evaluation board. The
AD12401/KIT comes with a buffer memory FIFO board
connected to P2, which provides the interface to the parallel
port of a PC. The Dual Analyzer software is compatible with
Windows 95, Windows 98, Windows 2000, and Windows NT.
The buffer memory FIFO board can be removed, and an
external logic analyzer or other data acquisition module can
be connected to this connector, if required.
Adapter Card
The AD12401 is attached to an adapter card that interfaces to
the evaluation board through a 120-pin connector, P1, which is
on the top side of the evaluation board.
Digital Postprocessing Control
The evaluation board has a 2-pin jumper, labeled AFB that
allows the user to enable/disable the digital postprocessing. The
digital postprocessing is active when the AFB jumper
is applied. When the jumper is removed, the FPGA is set to a
passthrough mode, which demonstrates to the user the perform-
ance of the AD12401 without the digital postprocessing.
RESET
The AD12401's FPGA configuration is stored in an EEPROM
and loaded into the FPGA when power is applied to the
AD12401. The RESET switch, SW1 (active low), allows the user
to reload the FPGA in case of a low voltage condition or a
power supply glitch. Depressing the RESET switch pulls the
data ready and output bits high. The RESET switch should
remain low for a minimum of 200 ns. On the rising edge of the
RESET pulse, the AD12401 starts loading the configuration into
the on-module FPGA. The reload process requires a maximum
of 600 ms to complete. Valid signals on the data-ready pins
indicate the reset process is complete.
The AD12401 is not compatible with the HSC-ADC-EVAL-
DC/SC hardware or software.
Table 11. Evaluation Board Bill of Materials (BOM)
Item No.
Quantity
REF-DES
Device
Package
Value
1
2
C3, C5
Capacitors
603
0.1 F, 25 V
2
2
C4, C6
Capacitors
805
10 F, 6.3 V
3
1
R9
Resistor
603
4.02 k, 1%
4
1
AFB
2-Pin Header/Jumper
Pin Strip
Molex/GC/Weldon
5
1
P2
80-Pin Dual Connector Assemble
Surface-Mount
Post Header AMP
6
1
SW1
Switch Push Button SPST
6 MM
Panasonic
7
3
J2, J3, J4
4-Pin Header Power Connecters
Pin Strip
Wieland
8
1
P1
60-Pin Dual-Socket Assembly
Surface-Mount
SAMTEC
9
1
PCB
AD12401 Interface Bd GS08054
PCB
AD12401
Rev. 0 | Page 21 of 28
05649-023
AFB
3.3VC
PASS
H/L_GAIN
3.3VC
H/L_GAIN
NYQ
3.3VC
NYQ
DITHER
JP2
E12
JP3
E13
SPARE1
E14
SPARE2
E18
3.3VC
OTHER
SPARE1
SPARE2
DGND
1.5VD
DIGITAL
J3
1
2
3
4
DGND
+VA
AGND
ANALOG
J2
1
2
3
4
DIGITAL
J4
3.3VC
3.8V
DGND
1
2
3
4
5V
C4
10
F
C3
0.1
F
DGND
DGND
5V
5V
C6
10
F
C5
0.1
F
3.3VC
DGND
DGND
3.3VD
3.3VD
SELECT D
JP4
E17
SELECT D
RESET
1.5V SENSE
E22
DGND
EVQ-PAC85R
1
2
3
4
E1
R8
4.02k
R9
4.02k
R10
4.02k
R11
4.02k
Figure 24. Evaluation Board
AD12401
Rev. 0 | Page 22 of 28
05649-024
DRB
DNC
3.3VC
DNC
DNC
3.3VC
DNC
RESET
DNC
DNC
DB8
DB9
DB10
DB11
DB4
DB5
DB6
DB7
DB2
DB3
DB0
DB1
14
16
18
20
22
24
26
28
30
32
34
36
38
40
122
124
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
121
123
4
6
8
10
12
P1:A
DGND
QSE6001LDAK
DGND
DRB
DNC
DB8
DB6
DB4
DB2
DB0
GND
GND
GND
GND
DB11
DB9
DB7
DB5
DB3
DB1
DB11
PASS
1.5VD
1.5VD
DA10
DA11
DNC
DA8
DA7
DA10
DA9
DA4
DA3
DA6
DA5
DA2
DA1
DA0
DRA
DR_EN
54
56
58
60
62
64
66
68
70
72
74
76
78
80
126
128
42
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
125
127
44
46
48
50
52
P1:B
DGND
QSE6001LDAK
DGND
DNC
DA8
DA6
DA4
DA2
DA0
DRA
GND
GND
GND
GND
DA11
DA9
DA7
DA5
DA3
DA1
DNC
DNC
AGND
AGND
3.3VC
DNC
DNC
DNC
WP
94
96
98
100
102
104
106
108
110
112
114
116
118
120
130
132
82
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
129
131
84
86
88
90
92
P1:C
AGND
AGND
QSE6001LDAK
AGND
AGND
DNC
GND
GND
GND
E2
E19
DNC
DNC
DNC
DNC
DNC
+VA
+VA
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DGND
P2:C
AMP104655-9
DRA
DA11
DA10
DRA
DA11
DA10
DA9
DA9
DA8
DA8
DA7
DA7
DA6
DA6
DA5
DA5
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P2:D
AMP104655-9
DA3
DA1
DA0
DA3
DA2
DA2
DA4
DA4
DA1
DA0
OR
OR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
DGND
P2:A
AMP104655-9
DRB
DB11
DB10
DRB
DB11
DB10
DB9
DB9
DB8
DB8
DB7
DB7
DB6
DB6
DB5
DB5
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P2:B
AMP104655-9
DB3
DB1
DB0
DB3
DB2
DB2
DB4
DB4
DB1
DB0
OR
OR
AD1240X
DB10
OROUT
OROUT
Figure 25. Evaluation Board
AD12401
Rev. 0 | Page 23 of 28
05649-025
Figure 26. Power Plane 1
05649-026
Figure 27. Power Plane 2
05649-027
Figure 28. First Ground Plane
05649-028
Figure 29. Second Ground Plane
05649-029
Figure 30. Top Side Copper
05649-030
Figure 31. Bottom Side Copper
AD12401
Rev. 0 | Page 24 of 28
05649-034
05649-031
Figure 32. Top Mask
Figure 35. Evaluation Adapter Board, Top Silkscreen
05649-035
05649-032
Figure 36. Evaluation Adapter Board, Analog and Digital Layers
Figure 33. Top Silkscreen
05649-037
05649-033
Figure 34. Bottom Silkscreen
Figure 37. Evaluation Adapter Board, Bottom Silkscreen
AD12401
Rev. 0 | Page 25 of 28
LAYOUT GUIDELINES
The AD12401 requires a different approach to traditional high
speed ADC system layouts. While the AD12401's internal PCB
isolates digital and analog grounds, these planes are tied
together through the product's aluminum case structure.
Therefore, the decision of isolating the analog and digital
grounds on the system PCB has additional factors to consider.
For example, if the AD12401 is attached with conductive
thermal interface material to the system PCB, there is
essentially no benefit to keeping the analog and digital ground
planes separate. If neither thermal interface material nor
nonconductive interface material is used, system architects
must consider the ground loop that is created if analog and
digital planes are tied together directly under the AD12401.
This EMI-based decision must be considered on a case-by-case
basis and is largely dependent on the other sources of EMI in
the system. One critical consideration is that a 12-bit perform-
ance requirement (74 dBc) requires keeping conducted EMI
currents (referenced to the input of the AD12401) below 4.5 A.
All the characterization and testing of the AD12401 is performed
using a system that isolated these ground planes.
If thermal interface material is used in the final system design,
the following layout factors need to be considered: open solder
mask on the area that contacts the interface material and the
thickness of the ground plane. While this should be analyzed in
each specific system design, the use of solder mask may negate
any advantage achieved by using the thermal interface material,
and its use should be carefully considered. The ground plane
thickness does not have a major impact on the thermal per-
formance, but if design margin is slight, additional thickness
can yield incremental improvements.
PCB INTERFACE
Figure 38 provides the mounting hole footprint for assembling
the AD12401 to the second-level assembly. The diagram is
referenced to the center of the mating QTE connector. Refer
to the QTE/QSE series connector documentation at
www.samtec.com for the SMT footprint of the mating
connector.
The top view of the second-level assembly footprint provides a
diagram of the second-level assembly locating tab locations for
mating the SAMTEC QTE-060-01-L-A-K-TR terminal strip on
the AD12401 to a QSE-060-01-L-A-K-TR socket on the second-
level assembly. The diagram is referenced to the center of the
QTE terminal strip on the AD12401 and the mounting holds
for the screws, which holds the AD12401 to the second-level
assembly board. The relationship of these locating tabs is based
on information provided by SAMTEC (connector supplier) and
should be verified with SAMTEC by the customer.
Mating and unmating forces--the knifing or peeling action of
applying force to one end or one side--must be avoided to
prevent damage to the connector and guidepost.
AD12401
Rev. 0 | Page 26 of 28
05649-038
1.184 [30.0673]
1.184 [30.0673]
R.0470[R1.19] 6
1.025 [26.0164] 2
0.105 [
2.6670]
2
0.396 [
10.0456]
2
2.159 [
54.8258]
2
1.025 [26.0164] 2
.000 [.0000]
0.000 [
.
0000]
0, 0 DATUM = CENTER OF CONNECTOR
Figure 38. Top View of Interface PCB Assembly
AD12401
Rev. 0 | Page 27 of 28
OUTLINE DIMENSIONS
TOP VIEW
SIDE VIEW
3.190 TYP
PIN 1
AIN
ENC
ENC
2.890 MAX
BOARD
2.328 TYP
0.856 TYP
0.256 TYP
0.267 TYP
SAMTEC CONNECTOR
QTE-060-01-L-D-A-K-TR
BOTTOM VIEW
1.773
1.753
2.060
2.040
0.270 2
0.505 TYP 2
0.700 MAX
0.175 TYP
0.200 TYP
2-56 STUDS 4
0.600 MAX
JOHNSON SMA-50 OHM CONNECT NO. 142-0711-821
2.590 MAX
2.060
2.040
Figure 39. Outline Dimensions
Dimensions shown in inches
Tolerances: 0.xxx = 5 mils
ORDERING GUIDE
Model
Temperature Range
Package Description
AD12401-326KWS
0C to 60C (Case)
2.9" 2.6" 0.6" Module
AD12401-360KWS
0C to 60C (Case)
2.9" 2.6" 0.6" Module
AD12401-400KWS
0C to 60C (Case)
2.9" 2.6" 0.6" Module
AD12401/KIT
Evaluation
Kit
AD12401
Rev. 0 | Page 28 of 28
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05649-0-7/05(0)