ChipFind - документация

Электронный компонент: AD1317KZ

Скачать:  PDF   ZIP

Document Outline

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD1317
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
Ultrahigh Speed
Window Comparator with Latch
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Full Window Comparator
2.0 pF max Input Capacitance
9 V max Differential Input Voltage
2.5 ns Propagation Delays
Low Dispersion
Low Input Bias Current
Independent Latch Function
Input Inhibit Mode
80 dB CMRR
APPLICATIONS
High Speed Pin Electronic Receiver
High Speed Triggers
Threshold Detectors
Peak Detectors
PRODUCT DESCRIPTION
The AD1317 is an ultrahigh speed window comparator with a
latch. It uses a high speed monolithic process to provide high dc
accuracy without sacrificing input voltage range. The AD1317
guarantees a 2.8 ns maximum propagation delay.
On-chip connection of the common input eliminates the contri-
butions of a second bonding pad and package pin to the input
capacitance, resulting in a maximum input capacitance of 2 pF.
The dispersion, or variation in propagation delay with input
overdrive levels and slew rates, is typically 350 ps for 5 V signals
and 200 ps for 1 V inputs.
The AD1317 employs a high precision differential input stage
with a common-mode range of 9 V. Its complementary digital
outputs are ECL compatible. The output stage is capable of
driving a 50
line terminated to 2 V. The AD1317 also pro-
vides a latch function, allowing operation in a sample-hold
mode. The latch inputs can also be used to generate hysteresis.
The comparator input can be switched into a high impedance
state through the inhibit mode feature, electrically removing the
comparator from the circuit. The bias current in inhibit mode is
typically 50 pA.
The AD1317 is available in a small 16-lead, hermetically sealed
"gull-wing" surface mount package and operates over the com-
mercial temperature range, 0
C to +70
C.
2
REV. A
AD1317SPECIFICATIONS
(All specifications at +25 C, free air. Outputs terminated into 50 to 2 V,
with + V
S
= +10 V, V
S
= 5.2 V unless otherwise noted)
AD1317KZ
Parameter
Symbol
Min
Typ
Max
Units
Comments
DC INPUT CHARACTERISTICS
Offset Voltage
V
OS
10
10
mV
CMV = 0 V
Offset Drift
dV
OS
/dT
20
V/
C
VINA/B Bias Currents
2 V to +7 V
Active
Ibca
10
33
A
Inhibit
Ibci
50
pA
VINA, VINB Bias Currents
2 V to +7 V
Active
Ibsa
5
16.5
A
Inhibit
Ibsi
50
pA
VINA/B Resistance
Rinc
4
M
VINA, VINB Resistance
Rins
8
M
Capacitance VINA/B, VINA, VINB
C
IN
1.5
2.0
pF
Voltage Range
V
CM
2
7
Volts
See Note 5
Differential Voltage
V
DIFF
9
Volts
Common-Mode Rejection Ratio
CMRR
70
80
dB
2 V to +7 V
LATCH ENABLE INPUTS
Input Voltage, Any Input
2.0
5.0
Volts
Differential Voltage
0.4
4
Volts
Logic "1" Current
I
IH
10
A
Logic "0" Current
I
IL
200
A
Capacitance
4
pF
INPUT ENABLE CURRENTS
Input Voltage, Any Input
2.0
5.0
Volts
Differential Voltage
0.4
4
Volts
Logic "1" Current
I
IH
20
A
Logic "0" Current
I
IL
200
A
Capacitance
4
pF
DIGITAL OUTPUTS
Logic "l" Voltage
V
OH
0.98
Volts
Logic "0" Voltage
V
OL
1.50
Volts
SWITCHING PERFORMANCE
See Figure 3
Propagation Delays
Input to Output
t
PDR
, t
PDF
1.8
2.8
ns
See Note 1
Latch Enable to Output
t
LO
2.0
2.5
ns
See Note 1
Active to Inhibit
t
IN
2.5
ns
See Note 2
Inhibit to Active
t
IE
15
ns
See Note 3
Propagation Delay T.C.
5
ps/
C
Dispersion
See Note 4
5 V Signal
See Figure 1
All Edges
450
600
ps
Rising Edge
350
ps
Falling Edge
350
ps
1 V Signal
See Figure 2
All Edges
250
400
ps
Rising Edge
200
ps
Falling Edge
200
ps
LATCH TIMING
Input Pulse Width
t
PW
2.5
1.0
ns
Setup Time
t
S
1.5
0.4
ns
Hold Time
t
H
0
ns
POWER SUPPLIES
V
S
to +V
S
Range
15.2
15.6
See Note 5
Positive Supply
+V
S
8.0
10.0
11.0
Volts
Negative Supply
V
S
7.2
5.2
4.2
Volts
Positive Supply Current
I+
50
70
mA
Negative Supply Current
I
100
70
mA
PSRR
65
75
dB
Measured at
2.5% of +V
S
and V
S
NOTES
1
P
ropagation Delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and
Q crossing.
2
Propagation Delay is measured from the input crossing of IE and
IE to when the input bias currents drop to 10% of their nominal value.
3
Propagation Delay is measured from the input crossing of IE and
IE to when the input bias currents rise to 90% of their nominal value.
4
Dispersion is measured with input slew rates of 0.5 V/ns and 2.5 V/ns for 5 V swings, 0.5 V/ns and 1 V/ns for 1 V swings.
5
The comparator input voltage range is specified for 2 V to +7 V for typical power supply values of -5.2 V and +10.0 V but can be offset for different input ranges such as 1 V to
+8 V with power supplies of 4.2 V and +11 V, as long as the required headroom of 3 V is maintained between both V
H
and +V
S
and V
L
and +V
S
.
Specifications subject to change without notice.
AD1317
3
REV. A
ABSOLUTE MAXIMUM RATINGS
1
Power Supply Voltage
+V
S
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V
V
S
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V
Difference from +V
S
to V
S
. . . . . . . . . . . . . . . . . . . . +16 V
Inputs
VINA/B, VINA, VINB . . . . . . . +V
S
13.5 V, V
S
+ 13.7 V
LEA, LEA, LEB, LEB . . . . . . . . . . +V
S
14 V, V
S
+ 12 V
IE,
IE . . . . . . . . . . . . . . . . . . . . . . +V
S
14 V, V
S
+ 10.3 V
Outputs
2
QA,
QA, QB, QB . . . . . . . . . . GND 0.5 V, GND + 3.5 V
Operating Temperature Range . . . . . . . . . . . . . 0
C to +70
C
Storage Temperature Range
After Soldering . . . . . . . . . . . . . . . . . . . . . 65
C to + 125
C
Lead Temperature Range (Soldering 20 sec)
3
. . . . . . . +300
C
NOTES
1
Stresses above those limits under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Limits apply for shorted output.
3
To ensure lead coplanarity (
0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in an environment at
24
C
5
C (75
F
10
F) with relative humidity not to exceed 65%.
WINDOW COMPARATOR PIN ASSIGNMENT
Pin No.
Description
1
VINA
Noninverting Comparator A Input
2
VINA/B
Window Comparator Common Input
3
VINB
Inverting Comparator B Input
4
IE
Input Enable
5
IE
Input Enable
6
V
S
Negative Supply, 5.2V
7
GND
Ground
8
+V
S
Positive Supply, +10 V
9
LEB
Latch Enable B
10
LEB
Latch Enable B
11
QB
Comparator B Output
12
QB
Comparator B Output
13
QA
Comparator A Output
14
QA
Comparator A Output
15
LEA
Latch Enable A
16
LEA
Latch Enable A
ORDERING GUIDE
Temperature
Package
Model
Range
Description
Option*
Quantity
AD1317KZ
0
C to +70
C
16-Lead
Z-16A
1-24
Gull Wing
2599
100+
*Z = Ceramic Leaded Chip Carrier.
CONNECTION DIAGRAMS
Dimensions shown in inches and (mm).
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1317 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD1317
4
REV. A
DEFINITION OF TERMS
Vos
INPUT OFFSET VOLTAGE--The voltage that
must be applied between either VINA and VINA/B or
VINB and VINA/B to obtain zero voltage between
outputs QA and
QA, or QB and QB, respectively.
dV
OS
/dT OFFSET DRIFT--The ratio of the change in input
offset voltages, over the operating temperature range,
to the change in temperature.
Ibca
INPUT BIAS CURRENT (VINA/B, ACTIVE)--
The bias current of the window comparator's com-
mon input with inputs enabled.
Ibci
INPUT BIAS CURRENT (VINA/B, INHIBIT)--
The bias current of the window comparator's com-
mon input with inputs inhibited.
Ibsa
INPUT BIAS CURRENT (VINA or VINB,
ACTIVE)--The bias current of either single input
with inputs active.
Ibsi
INPUT BIAS CURRENT (VINA or VINB,
INHIBIT)--The bias current of either single input
with inputs inhibited.
Rinc
INPUT RESISTANCE (VINA/B)--The input
resistance looking into the window comparator's
common input.
Rins
INPUT RESISTANCE (VINA or VINB)--The
input resistance looking into either single input.
C
IN
INPUT CAPACITANCE (VINA/B)--The capaci-
tance looking into the window comparator's common
input.
V
CM
INPUT COMMON-MODE VOLTAGE RANGE--
The range of voltages on the input terminals for
which the offset and propagation delay specifications
apply.
V
DIFF
INPUT DIFFERENTIAL VOLTAGE RANGE--
The maximum difference between any input terminal
voltages.
CMRR
COMMON-MODE REJECTION RATIO--The
ratio of common-mode input voltage range to the
peak-to-peak change in input offset voltage over this
range.
I
IH
LOGIC "1" INPUT CURRENT--The logic high
current flowing into (+) or out of () a logic input.
I
IL
LOGIC "0" INPUT CURRENT--The logic low
current flowing into (+) or out of () a logic input.
V
OH
LOGIC "1" OUTPUT VOLTAGE--The logic high
output voltage with a specified load.
V
OL
LOGIC "0" OUTPUT VOLTAGE--The logic low
output voltage with a specified load.
I
OH
LOGIC "1" OUTPUT CURRENT--The logic high
output source current.
I
OL
LOGIC "0" OUTPUT CURRENT--The logic low
output source current.
I+
POSITIVE SUPPLY CURRENT--The current
required from the +V
S
supply.
I
NEGATIVE SUPPLY CURRENT--The current
required from the V
S
supply.
PSRR
POWER SUPPLY REJECTION RATIO--The ratio
of power supply voltage change to the peak-to-peak
change in input offset voltage.
AD1317 SWITCHING TERMS (See Figure 3)
t
PDR
INPUT TO OUTPUT RISING EDGE DELAY--
The propagation delay measured from the time
VINA/B crosses either VINA or VINB, in a low to
high transition, to the time QA and
QA or QB and
QB cross, respectively.
t
PDF
INPUT TO OUTPUT FALLING EDGE DELAY--
The propagation delay measured from the time
VINA/B crosses either VINA or VINB, in a high to
low transition, to the time QA and
QA or QB and
QB cross, respectively.
t
S
MINIMUM LATCH SET-UP TIME--The minium
time before LE goes high with respect to
LE that an
input signal change must be present in order to be
acquired and held at the outputs.
t
H
MINIMUM LATCH HOLD TIME--The minium
time after LE goes high with respect to
LE that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
t
PW
MINIMUM LATCH ENABLE PULSE WIDTH--
The minimum time that LE must be held high with
respect to
LE in order to acquire and hold an input
change.
t
LO
LATCH ENABLE TO OUTPUT DELAY--The
time between when LE goes high with respect to
LE
that QA and
QA or QB and QB cross.
t
ID
INPUT STAGE DISABLE TIME--The time be-
tween when
IE goes high with respect to IE that the
input bias currents drop to 10% of their nominal
value.
t
IE
INPUT STAGE ENABLE TIME--The time be-
tween when IE goes high with respect to
IE that the
input bias currents rise to 90% of their nominal values.
AD1317
5
REV. A
Figure 1. Dispersion Test Input Conditions--5 V Signal
Figure 2. Dispersion Test Input Conditions--1 V Signal
Figure 3. Timing Diagram