256-Position SPI/I
2
C Selectable
Digital Potentiometer
AD5161
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
FEATURES
256-position
End-to-end resistance 5 k, 10 k, 50 k, 100 k
Compact MSOP-10 (3 mm 4.9 mm) package
Pin selectable SPI/I
2
C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/C
Low power, I
DD
= 8 A
Wide operating temperature 40C
to +125C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5161 provides a compact 3 mm 4.9 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
The wiper settings are controllable through a pin selectable SPI
or I
2
C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I
2
C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 A allows for usage in portable battery-operated
applications.
FUNCTIONAL BLOCK DIAGRAM
WIPER
REGISTER
SDI/SDA
CLK/SCL
DIS
CS/AD0
GND
SDO/NC
V
DD
A
W
B
SPI OR I
2
C
INTERFACE
Figure 1.
PIN CONFIGURATION
1
2
3
4
5
10
9
8
7
6
A
B
CS/ADO
SDO/NC
SDI/SDA
DD
AD5161
TOP VIEW
(Not to Scale)
W
V
DIS
GND
CLK/SCL
Figure 2.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use these components in an I
2
C system, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
AD5161
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Electrical Characteristics--5 k Version ...................................... 3
Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4
Timing Characteristics--5 k, 10 k, 50 k, 100 k Versions 5
Absolute Maximum Ratings
1
.......................................................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
SPI Interface .................................................................................... 12
I
2
C Interface..................................................................................... 13
Operation......................................................................................... 14
Programming the Variable Resistor ......................................... 14
Programming the Potentiometer Divider ............................... 15
Pin Selectable Digital Interface................................................. 15
Level Shifting for Bidirectional Interface ................................ 17
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range.......................................... 17
Power-Up Sequence ................................................................... 17
Layout and Power Supply Bypassing ....................................... 17
Pin Configuration and Function Descriptions........................... 18
Pin Configuration ...................................................................... 18
Pin Function Descriptions ........................................................ 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
ESD Caution................................................................................ 19
REVISION HISTORY
Revision 0: Initial Version
AD5161
Rev. 0 | Page 3 of 20
ELECTRICAL CHARACTERISTICS--5 k VERSION
(V
DD
= 5 V 10%, or 3 V 10%; V
A
= +V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.)
Table 1.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
1.5
0.1
+1.5
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
4
0.75
+4
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
30
+30
%
Resistance Temperature Coefficient
R
AB
/T V
AB
= V
DD
, Wiper = no connect
45
ppm/C
Wiper
Resistance
R
W
50
120
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential
Nonlinearity
4
DNL
1.5 0.1 +1.5 LSB
Integral
Nonlinearity
4
INL
1.5 0.6 +1.5 LSB
Voltage Divider Temperature Coefficient
V
W
/T
Code = 0x80
15
ppm/C
Full-Scale
Error
V
WFSE
Code = 0xFF
6
2.5
0
LSB
Zero-Scale
Error
V
WZSE
Code = 0x00
0
+2
+6
LSB
RESISTOR
TERMINALS
Voltage
Range
5
V
A,B,W
GND
V
DD
V
Capacitance
6
A, B
C
A,B
f = 1 MHz, measured to GND,
Code = 0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to GND,
Code = 0x80
60
pF
Shutdown Supply Current
7
I
DD_SD
V
DD
= 5.5 V
0.01
1
A
Common-Mode
Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
2.4
V
Input Logic Low
V
IL
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input
Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input
Capacitance
6
C
IL
5
pF
POWER
SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5 V
Supply
Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3
8
A
Power
Dissipation
8
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
0.2
mW
Power Supply Sensitivity
PSS
V
DD
= +5 V 10%,
Code = Midscale
0.02 0.05 %/%
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth
3dB
BW_5K R
AB
= 5 k, Code = 0x80
1.2
MHz
Total
Harmonic
Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
0.05
%
V
W
Settling Time
t
S
V
A
= 5 V, V
B
= 0 V, 1 LSB error
band
1
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 2.5 k, RS = 0
6
nV/Hz
AD5161
ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
(V
DD
= 5 V 10%, or 3 V 10%; V
A
= V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.)
Table 2.
Parameter Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
1
0.1
+1
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
2
0.25
+2
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
30
+30
%
Resistance Temperature Coefficient
R
AB
/T
V
AB
= V
DD
,
Wiper = no connect
45
ppm/C
Wiper
Resistance
R
W
V
DD
= 5 V
50
120
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential
Nonlinearity
4
DNL
1
0.1
+1
LSB
Integral
Nonlinearity
4
INL
1
0.3
+1
LSB
Voltage Divider Temperature Coefficient
V
W
/T
Code = 0x80
15
ppm/C
Full-Scale
Error
V
WFSE
Code = 0xFF
3
1
0
LSB
Zero-Scale
Error
V
WZSE
Code = 0x00
0
1
3
LSB
RESISTOR TERMINALS
Voltage
Range
5
V
A,B,W
GND
V
DD
V
Capacitance
6
A, B
C
A,B
f = 1 MHz, measured to
GND, Code = 0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to
GND, Code = 0x80
60
pF
Shutdown Supply Current
7
I
DD_SD
V
DD
= 5.5 V
0.01
1
A
Common-Mode
Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
2.4
V
Input Logic Low
V
IL
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input
Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input
Capacitance
6
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5 V
Supply
Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3
8
A
Power
Dissipation
8
P
DISS
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= 5 V
0.2
mW
Power Supply Sensitivity
PSS
V
DD
= +5 V 10%,
Code = Midscale
0.02 0.05
%/%
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth
3dB
BW
R
AB
= 10 k/50 k/100 k,
Code = 0x80
600/100/40
kHz
Total
Harmonic
Distortion
THD
W
V
A
=1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 k
0.05 %
V
W
Settling Time (10 k/50 k/100 k)
t
S
V
A
= 5 V, V
B
= 0 V,
1 LSB error band
2
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 5 k, RS = 0
9
nV/Hz
Rev. 0 | Page 4 of 20
AD5161
TIMING CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
(V
DD
= +5V 10%, or +3V 10%; V
A
= V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.)
Table 3.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS
6, 10
(Specifications Apply to All Parts)
Clock
Frequency
f
CLK
25 MHz
Input Clock Pulsewidth
t
CH
, t
CL
Clock level high or low
20
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CS Setup Time
t
CSS
15
ns
CS High Pulsewidth
t
CSW
40
ns
CLK Fall to CS Fall Hold Time
t
CSH0
0
ns
CLK Fall to CS Rise Hold Time
t
CSH1
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
I
2
C INTERFACE TIMING CHARACTERISTICS
6, 11
(Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
400
kHz
t
BUF
Bus Free Time between STOP and START
t
1
1.3
s
t
HD;STA
Hold Time (Repeated START)
t
2
After this period, the first clock pulse is
generated.
0.6
s
t
LOW
Low Period of SCL Clock
t
3
1.3
s
t
HIGH
High Period of SCL Clock
t
4
0.6
50
s
t
SU;STA
Setup Time for Repeated START Condition
t
5
0.6
s
t
HD;DAT
Data Hold Time
t
6
0.9
s
t
SU;DAT
Data Setup Time
t
7
100
ns
t
F
Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R
Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO
Setup Time for STOP Condition
t
10
0.6
s
NOTES
1
Typical specifications represent average readings at +25C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11
See timing diagrams for locations of measured values.
Rev. 0 | Page 5 of 20
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