Document Outline
- FEATURES
- APPLICATIONS
- FUNCTIONAL BLOCK DIAGRAM
- GENERAL DESCRIPTION
-
-
-
-
-
-
-
-
-
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Dual 256-Position SPI
Digital Potentiometer
AD5162
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
FEATURES
2-channel, 256-position
End-to-end resistance: 2.5 k, 10 k, 50 k, 100 k
Compact MSOP-10 (3 mm 4.9 mm) package
Fast settling time: t
S
= 5 s typical on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pin AD0
Computer software replaces C in factory programming
applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/C
Low power: I
DD
= 6 A max
Wide operating temperature: -40C to +125C
Evaluation board available
APPLICATIONS
Systems calibrations
Electronics level settings
Mechanical Trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
FUNCTIONAL BLOCK DIAGRAM
A1
A = 0
A = 1
V
DD
GND
SDI
CLK
CS
W1
WIPER
REGISTER 1
SPI INTERFACE
AD5162
04108-0-001
B1
W2
WIPER
REGISTER 2
B2
Figure 1.
GENERAL DESCRIPTION
The AD5162 provides a compact 3 mm 4.9 mm packaged
solution for dual 256-position adjustment applications. This
device performs the same electronic adjustment function as a
3-terminal mechanical potentiometer. Available in four different
end-to-end resistance values (2.5 k, 10 k, 50 k, 100 k),
this low temperature coefficient device is ideal for high accu-
racy and stability variable resistance adjustments. The wiper
settings are controllable through an SPI digital interface. The
resistance between the wiper and either endpoint of the fixed
resistor varies linearly with respect to the digital code
transferred into the RDAC
1
latch.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 6 A allows the AD5162 to be used in portable
battery-operated applications.
For applications that program the AD5162 at the factory,
Analog Devices offers device programming software running
on Windows NT/2000/XP operating systems. This software
effectively replaces any external SPI controllers, which in turn
enhances users' systems time-to-market. An AD5162 evaluation
kit and software are available. The kit includes a cable and
instruction manual.
AD5162
Rev. A | Page 2 of 20
TABLE OF CONTENTS
Electrical Characteristics--2.5 k Version ................................... 3
Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4
Timing Characteristics--All Versions ........................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Pin Configuration......................................................................... 7
Pin Function Descriptions .......................................................... 7
Typical Performance Characteristics ............................................. 8
Test Circuits..................................................................................... 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor and Voltage.................... 13
Programming the Potentiometer Divider............................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 15
Constant Bias to Retain Resistance Setting............................. 15
Evaluation Board ........................................................................ 15
SPI Interface .................................................................................... 16
SPI Compatible 3-Wire Serial Bus ........................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
11/03 Changed from REV. 0 to REV. A:
Changes to Electrical Characteristics.................................... Page 3
11/03 Revision 0: Initial Version
AD5162
Rev. A | Page 3 of 20
ELECTRICAL CHARACTERISTICS--2.5 k VERSION
Table 1. V
DD
= 5 V 10%, or 3 V 10%; V
A
= +V
DD
; V
B
= 0 V; -40C < T
A
< +125C; unless otherwise noted
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
-2
0.1
+2
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
-6
0.75
+6
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
-20
+55
%
Resistance Temperature Coefficient
(R
AB
/R
AB
)/T
V
AB
= V
DD
, wiper = no connect
35
ppm/C
R
WB
(Wiper Resistance)
R
WB
Code = 0x00, V
DD
= 5 V
160
200
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity
4
DNL
-1.5
0.1
+1.5
LSB
Integral Nonlinearity
INL
-2
0.6
+2
LSB
Voltage Divider Temperature
Coefficient
(V
W
/V
W
)/T
Code = 0x80
15
ppm/C
Full-Scale Error
V
WFSE
Code = 0xFF
-10
-2.5
0
LSB
Zero-Scale Error
V
WZSE
Code = 0x00
0
2
10
LSB
RESISTOR TERMINALS
Voltage Range
5
V
A, B, W
GND
V
DD
V
Capacitance
6
A, B
C
A, B
f = 1 MHz, measured to GND, Code =
0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to GND, Code =
0x80
60
pF
Common-Mode Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
2.4
V
Input Logic Low
V
IL
V
DD
= 5 V
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input Capacitance
6
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5
V
Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3.5
6
A
Power Dissipation
7
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
30
W
Power Supply Sensitivity
PSS
V
DD
= 5 V 10%, Code = midscale
0.02
0.08
%/%
DYNAMIC CHARACTERISTICS
8
Bandwidth -3 dB
BW_2.5 K
Code = 0x80
4.8
MHz
Total Harmonic Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
0.1
%
V
W
Settling Time
t
S
V
A
= 5 V, V
B
= 0 V, 1 LSB error band
1
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 1.25 k, R
S
= 0
3.2
nV/
Hz
See notes at end of section.
AD5162
Rev. A | Page 4 of 20
ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
Table 2. V
DD
= 5 V 10%, or 3 V 10%; V
A
= V
DD
; V
B
= 0 V; -40C < T
A
< 125C; unless otherwise noted
Parameter
Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
-1
0.1
+1
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
-2.5 0.25
+2.5
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
-20
+20
%
Resistance Temperature Coefficient
(R
AB
/R
AB
)/T
V
AB
= V
DD
, wiper = no connect
35
ppm/C
R
WB
(Wiper Resistance)
R
WB
Code = 0x00, V
DD
= 5 V
160
200
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Differential Nonlinearity
4
DNL
-1
0.1
+1
LSB
Integral Nonlinearity
4
INL
-1
0.3
+1
LSB
Voltage Divider Temperature Coefficient
(V
W
/V
W
)/T
Code = 0x80
15
ppm/C
Full-Scale Error
V
WFSE
Code = 0xFF
-2.5 -1
0
LSB
Zero-Scale Error
V
WZSE
Code = 0x00
0
1
2.5
LSB
RESISTOR TERMINALS
Voltage Range
5
V
A,B,W
GND
V
DD
V
Capacitance
6
A, B
C
A,B
f = 1 MHz, measured to GND,
Code = 0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to GND,
Code = 0x80
60
pF
Common-Mode Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
2.4
V
Input Logic Low
V
IL
V
DD
= 5 V
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input Capacitance
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5
V
Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3.5
6
A
Power Dissipation
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
30
W
Power Supply Sensitivity
PSS
V
DD
= 5 V 10%, Code =
midscale
0.02
0.08
%/%
DYNAMIC CHARACTERISTICS
Bandwidth -3 dB
BW
R
AB
= 10 k/50 k/100 k,
Code = 0x80
600/100/40
kHz
Total Harmonic Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 k
0.1
%
V
W
Settling Time (10 k/50 k/100 k)
t
S
V
A
= 5 V, V
B
= 0 V,
1 LSB error band
2
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 5 k, R
S
= 0
9
nV/
Hz
See notes at end of section.
AD5162
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS--ALL VERSIONS
Table 3. V
DD
= +5 V 10%, or +3 V 10%; V
A
= V
DD
; V
B
= 0 V; -40C < T
A
< +125C; unless otherwise noted
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS
9
(Specifications Apply to All Parts)
Clock Frequency
f
CLK
25 MHz
Input Clock Pulse Width
t
CH
, t
CL
Clock level high or low
20
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CS Setup Time
t
CSS
15
ns
CS High Pulse Width
t
CSW
40
ns
CLK Fall to CS Fall Hold Time
t
CSH0
0
ns
CLK Fall to CS Rise Hold Time
t
CSH1
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
See notes at end of section.
NOTES
1
Typical specifications represent average readings at 25C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (VW) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output DAC converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
9
See timing diagrams for locations of measured values.
AD5162
Rev. A | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4. T
A
= 25C, unless otherwise noted
Parameter
Value
V
DD
to GND
0.3 V to +7 V
V
A
, V
B
, V
W
to GND
V
DD
Terminal Current, Ax to Bx, Ax to Wx,
Bx to Wx
1
Pulsed
20 mA
Continuous
5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range
40C to +125C
Maximum Junction Temperature (T
JMAX
)
150C
Storage Temperature
65C to +150C
Lead Temperature (Soldering, 10 s)
300C
Thermal Resistance
2
JA
: MSOP-10
230C/W
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
JMAX
- T
A
)/
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5162
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
10
9
8
7
1
2
3
4
B1
A1
W2
W1
B2
CS
SDI
GND
6
5
CLK
V
DD
TOP VIEW
AD5162
04108-0-002
Figure 2.
PIN FUNCTION DESCRIPTIONS
Table 5.
Pin
No.
Mnemonic Description
1
B1
B1 Terminal.
2
A1
A1 Terminal.
3
W2
W2 Terminal.
4
GND
Digital Ground.
5
V
DD
Positive Power Supply.
6
CLK
Serial Clock Input. Positive edge
triggered.
7
SDI
Serial Data Input.
8
CS
Chip Select Input, Active Low. When CS
returns high, data is loaded into the DAC
register.
9
B2
B2 Terminal.
10
W1
W1 Terminal.
AD5162
Rev. A | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.5
1.0
0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-003
V
DD
= 5.5V
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
Figure 3. R-INL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHE
OS
TAT MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-004
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 4. R-DNL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-005
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C, +25C, +85C, +125C
V
DD
= 5.5V
T
A
= 40C, +25C, +85C, +125C
Figure 5. INL vs. Code vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-006
V
DD
= 2.7V; T
A
= 40C, +25C, +85C, +125C
R
AB
= 10k
Figure 6. DNL vs. Code vs. Temperature
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-007
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 7. INL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-008
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 8. DNL vs. Code vs. Supply Voltages
AD5162
Rev. A | Page 9 of 20
2.0
1.5
1.0
0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-009
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C, +25C, +85C, +125C
V
DD
= 5.5V
T
A
= 40C, +25C, +85C, +125C
Figure 9. R-INL vs. Code vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHE
OS
TAT MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-010
V
DD
= 2.7V, 5.5V; T
A
= 40C, +25C, +85C, +125C
R
AB
= 10k
Figure 10. R-DNL vs. Code vs. Temperature
2.0
1.5
1.0
0.5
0
0.5
FSE, FU
LL-
SC
A
L
E ER
R
O
R
(
L
SB
)
1.0
1.5
2.0
TEMPERATURE (C)
40 25 10
5
20
35
50
65
80
95
110 125
04108-0-011
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 11. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZS
E
,
ZE
RO-S
CALE
E
RROR (LS
B
)
TEMPERATURE (C)
40 25 10
5
20
35
50
65
80
95
110 125
04108-0-012
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 12. Zero-Scale Error vs. Temperature
I
DD
, S
U
P
P
L
Y
CURRE
NT (
A)
0.1
1
10
40
7
26
59
92
125
TEMPERATURE (C)
04108-0-013
V
DD
= 5V
V
DD
= 3V
Figure 13. Supply Current vs. Temperature
20
0
20
40
60
80
100
120
RHEOSTAT MODE TE
MP
CO (ppm/
C)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-014
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C TO +85C, 40C TO +125C
V
DD
= 5.5V
T
A
= 40C TO +85C, 40C TO +125C
Figure 14. Rheostat Mode Tempco R
WB
/T vs. Code
AD5162
Rev. A | Page 10 of 20
30
20
10
0
10
20
P
O
TE
NTIOME
TE
R MODE
TE
MP
CO (ppm/
C)
30
40
50
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04108-0-015
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C TO +85C, 40C TO +125C
V
DD
= 5.5V
T
A
= 40C TO +85C, 40C TO +125C
Figure 15. Potentiometer Mode Tempco V
WB
/T vs. Code
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
10k
1M
100k
10M
04108-0-016
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 16. Gain vs. Frequency vs. Code, R
AB
= 2.5 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
1k
100k
10k
1M
04108-0-017
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 17. Gain vs. Frequency vs. Code, R
AB
= 10 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
1k
100k
10k
1M
04108-0-018
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 18. Gain vs. Frequency vs. Code, R
AB
= 50 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
1k
100k
10k
1M
04108-0-019
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 19. Gain vs. Frequency vs. Code, R
AB
= 100 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
10k
1k
100k
1M
10M
04108-0-020
100k
60kHz
50k
120kHz
10k
570kHz
2.5k
2.2MHz
Figure 20. 3 dB Bandwidth @ Code = 0x80
AD5162
Rev. A | Page 11 of 20
I
DD
, S
U
P
P
L
Y
CURRE
NT (mA)
0.01
1
0.1
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
04108-0-025
T
A
= 25C
V
DD
= 2.7V
V
DD
= 5.5V
Figure 21. I
DD
vs. Input Voltage
04108-0-021
V
W
CLK
Figure 22. Digital Feedthrough
04108-0-022
V
W2
V
W1
Figure 23. Digital Crosstalk
04108-0-024
V
W2
V
W1
Figure 24. Analog Crosstalk
04108-0-026
V
W
Figure 25. Midscale Glitch, Code 0x80 to 0x7F
04108-0-023
V
W
CS
Figure 26. Large Signal Settling Time
AD5162
Rev. A | Page 12 of 20
TEST CIRCUITS
Figure 27 through Figure 32 illustrate the test circuits that
define the test conditions used in the product specification
tables.
04108-0-027
V
MS
A
W
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
04108-0-028
NO CONNECT
I
W
V
MS
A W
B
DUT
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
04108-0-029
V
MS2
V
MS1
V
W
A
W
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
V
MS2
]/I
W
Figure 29. Test Circuit for Wiper Resistance
04108-0-030
V
MS
%
DUT
( )
A
W
B
V+
V
DD
%
V
MS
V
DD
V
DD
V
A
V
MS
V+ = V
DD
10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 30. Test Circuit for Power Supply Sensitivity
(PSS, PSSR)
04108-0-031
+15V
15V
W
A
2.5V
B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 31. Test Circuit for Gain vs. Frequency
W
B
V
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04108-0-033
Figure 32. Test Circuit for Common-Mode Leakage Current
AD5162
Rev. A | Page 13 of 20
THEORY OF OPERATION
The AD5162 is a 256-position digitally controlled variable
resistor (VR) device.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 2.5 k, 10 k, 50 k, and 100 k. The nominal
resistance (R
AB
) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings.
A
W
B
A
W
B
A
W
B
04108-0-034
Figure 33. Rheostat Mode Configuration
Assuming that a 10 k part is used, the wiper's first connection
starts at the B terminal for data 0x00. Because there is a 50
wiper contact resistance, such a connection yields a minimum
of 100 (2 50 ) resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
139 (R
WB
= R
AB
/256 + 2 R
W
= 39 + 2 50 ) for data
0x01. The third connection is the next tap point, representing
178 (2 39 + 2 50 ) for data 0x02, and so on. Each LSB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 10,100 (R
AB
+ 2 R
W
).
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
04108-0-035
Figure 34. AD5162 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB
R
R
D
D
R
+
=
2
256
)
(
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the ON resistance of
the internal switch.
In summary, if R
AB
= 10 k and the A terminal is open
circuited, the following output resistance R
WB
is set for the
indicated RDAC latch codes.
Table 6. Codes and Corresponding R
WB
Resistance
D (Dec)
R
WB
()
Output State
255
9,961
Full scale (R
AB
- 1 LSB + R
W
)
128
5,060
Midscale
1
139
1 LSB
0
100
Zero scale (wiper contact resistance)
Note that, in the zero-scale condition, a finite wiper resistance
of 100 is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance R
WA
. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for R
WA
starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
AB
WA
R
R
D
D
R
+
-
=
2
256
256
)
(
(2)
For R
AB
= 10 k and the B terminal open circuited, the
following output resistance R
WA
is set for the indicated RDAC
latch codes.
Table 7. Codes and Corresponding R
WA
Resistance
D (Dec)
R
WA
()
Output State
255
139
Full scale
128
5,060
Midscale
1
9,961
1 LSB
0
10,060
Zero scale
Typical device-to-device matching is process lot dependent and
may vary by up to 30%. Because the resistance element is
processed in thin film technology, the change in R
AB
with
temperature has a very low 35 ppm/C temperature coefficient.
AD5162
Rev. A | Page 14 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04108-0-036
Figure 35. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the volt-
age applied across terminal AB divided by the 256 positions of
the potentiometer divider. The general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
-
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance, V
W
, is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/C.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures shown in Figure 36 and
Figure 37. This applies to the digital input pins SDI, CLK,
and CS.
LOGIC
340
GND
04108-0-037
Figure 36. ESD Protection of Digital Pins
A, B, W
GND
04108-0-038
Figure 37. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5162 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND are clamped by the internal forward biased
diodes (see Figure 38).
GND
A
W
B
V
DD
04108-0-039
Figure 38. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 38), it is important to
power V
DD
/GND before applying any voltage to terminals A, B,
and W; otherwise, the diode is forward biased such that V
DD
is
powered unintentionally and may affect the rest of the user's
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A
, V
B
, V
W
. The relative order
of powering V
A
, V
B
, V
W
, and the digital inputs is not important
as long as they are powered after V
DD
/GND.
AD5162
Rev. A | Page 15 of 20
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or electro-
lytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 39). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
V
DD
GND
V
DD
C3
10
F
C1
0.1
F
AD5162
+
04108-0-040
Figure 39. Power Supply Bypassing
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the addi-
tional cost for the EEMEM, the AD5162 may be considered as a
low cost alternative by maintaining a constant bias to retain the
wiper setting. The AD5162 is designed specifically with low
power in mind, which allows low power consumption even in
battery-operated systems. The graph in Figure 40 demonstrates
the power consumption from a 3.4 V 450 mAhr Li-Ion cell
phone battery, which is connected to the AD5162. The measure-
ment over time shows that the device draws approximately
1.3 A and consumes negligible power. Over a course of
30 days, the battery is depleted by less than 2%, the majority of
which is due to the intrinsic leakage current of the battery itself.
This demonstrates that constantly biasing the potentiometer is
not an impractical approach. Most portable devices do not
require the removal of batteries for the purpose of charging.
Although the resistance setting of the AD5162 is lost when the
battery needs replacement, such events occur rather infre-
quently such that this inconvenience is justified by the lower
cost and smaller size offered by the AD5162. If and when total
power is lost, the user should be provided with a means to
adjust the setting accordingly.
DAYS
BATTERY LIFE DEPLETED
0
90%
92%
94%
96%
5
10
15
98%
100%
102%
104%
106%
108%
110%
20
25
30
04108-0-041
T
A
= 25C
Figure 40. Battery Operating Life Depletion
EVALUATION BOARD
An evaluation board, along with all necessary software, is
available to program the AD5162 from any PC running
Windows 98/2000/XP. The graphical user interface, as shown in
Figure 41, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.
Figure 41. AD5162 Evaluation Board Software
The AD5162 starts at midscale upon power-up. To increment or
decrement the resistance, the user may simply move the scroll-
bars on the left. To write any specific value, the user should use
the bit pattern in the upper screen and press the Run button.
The format of writing data to the device is shown in Table 8.
AD5162
Rev. A | Page 16 of 20
SPI INTERFACE
SPI COMPATIBLE 3-WIRE SERIAL BUS
The AD5162 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 9-bit serial word must be loaded MSB
first. The format of the word is shown in Table 8.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 42).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5162 uses a
9-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Table 8. Serial Data-Word Format
B8 B7 B6 B5 B4 B3 B2 B1 B0
A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
2
8
2
7
2
0
SDI
CLK
CS
V
OUT
RDAC REGISTER LOAD
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
1
04108-0-042
Figure 42. SPI Interface Timing Diagram
(V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
t
CSHO
t
CSS
t
CL
t
CH
t
DS
t
CSW
t
S
t
CS1
t
CSH1
t
CH
CLK
CS
V
OUT
1
0
1
0
1
0
V
DD
0
1LSB
SDI
(DATA IN)
Dx
Dx
04108-0-043
Figure 43. SPI Interface Detailed Timing Diagram (V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
AD5162
Rev. A | Page 17 of 20
OUTLINE DIMENSIONS
0.23
0.08
0.80
0.60
0.40
8
0
0.15
0.00
0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10
6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 44. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model R
AB
()
Temperature
Package Description
Package Option
Branding
AD5162BRM2.5
2.5 k
40C to +125C
MSOP-10
RM-10
D0Q
AD5162BRM2.5-RL7
2.5 k
40C to +125C
MSOP-10
RM-10
D0Q
AD5162BRM10
10 k
40C to +125C
MSOP-10
RM-10
D0R
AD5162BRM10-RL7
10 k
40C to +125C
MSOP-10
RM-10
D0R
AD5162BRM50
50 k
40C to +125C
MSOP-10
RM-10
D0S
AD5162BRM50-RL7
50 k
40C to +125C
MSOP-10
RM-10
D0S
AD5162BRM100
100 k
40C to +125C
MSOP-10
RM-10
D0T
AD5162BRM100-RL7
100 k
40C to +125C
MSOP-10
RM-10
D0T
AD5162EVAL
See Note 1
Evaluation Board
1
The evaluation board is shipped with the 10 k R
AB
resistor option; however, the board is compatible with all available resistor value options.
AD5162
Rev. A | Page 18 of 20
NOTES
AD5162
Rev. A | Page 19 of 20
NOTES
AD5162
Rev. A | Page 20 of 20
NOTES
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C04108011/03(A)
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