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256-Position, Ultralow Power
1.8 V Logic-Level Digital Potentiometer
AD5165
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Ultralow standby power I
DD
= 50 nA typical
256-position
End-to-end resistance 100 k
Logic high voltage 1.8 V
Power supply 2.7 V to 5.5 V
Low temperature coefficient 35 ppm/C
Compact thin 8-lead TSOT-8 (2.9 mm 2.8 mm) package
Simple 3-wire digital interface
Wide operating temperature -40C
to +125C
Pin-to-pin compatible to AD5160 with CS inverted
APPLICATIONS
Battery-operated electronics adjustment
Remote utilities meter adjustment
Mechanical potentiometer replacement
Transducer circuit adjustment
Automotive electronics adjustment
Gain control and offset adjustment
System calibration
VCXO adjustment
GENERAL OVERVIEW
The AD5165 provides a compact 2.9 mm 2.8 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance. The AD5165's supply voltage requirement is 2.7 V
to 5.5 V, but its logic voltage requirement is 1.8 V to V
DD
. The
AD5165 consumes very low quiescent power during standby
mode and is ideal for battery-operated applications.
Wiper settings are controlled through a simple 3-wire interface.
The interface is similar to the SPI digital interface except for the
inverted chip-select function that minimizes logic power con-
sumption in the idling state. The resistance between the wiper
and either endpoint of the fixed resistor varies linearly with
respect to the digital code transferred into the wiper register.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 50 nA typical standby power allows use in battery-
operated portable or remote utility device applications.
FUNCTIONAL BLOCK DIAGRAM
WIPER
REGISTER
CS
SDI
CLK
GND
V
DD
A
W
B
04749-0-001
3-WIRE
INTERFACE
Figure 1.
PIN CONFIGURATION
A
B
CS
SDI
1
2
3
4
5
8
7
6
W
V
DD
GND
CLK
TOP VIEW
(Not to Scale)
AD5165
04749-0-002
Figure 2.
TYPICAL APPLICATION
04749-0-003
DIGITAL
CONTROL
LOGIC OR
MICRO
AD5165
5V
3.3V
CS
CLK
SDI
GND
WIDE TERMINAL
VOLTAGE RANGE:
0V < V
A
,V
B
,V
W
< 5V
V
A
V
W
V
B
V
OH
= 1.8V MIN
V
DD
Figure 3.
Note:
The terms digital potentiometer, RDAC, and VR are used interchangeably.
AD5165
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Electrical Characteristics--100 k Version .................................. 3
Absolute Maximum Ratings............................................................ 5
Pin Configuration and Functional Descriptions.......................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
3-Wire Digital Interface................................................................. 12
Theory of Operation ...................................................................... 13
Programming the Variable Resistor ......................................... 13
Programming the Potentiometer Divider ............................... 14
3-Wire Serial Bus Digital Interface .......................................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range.......................................... 14
Power-Up Sequence ................................................................... 14
Layout and Power Supply Bypassing ....................................... 15
Evaluation Board ........................................................................ 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
4/04--Revision 0: Initial Version
AD5165
Rev. 0 | Page 3 of 16
ELECTRICAL CHARACTERISTICS--100 k VERSION
V
DD
= 5 V 10%, or 3 V 10%; V
A
= V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.
Table 1.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL R
WB
, V
A
= no connect
-1
0.1
+1
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
-2
0.25
+2
LSB
Nominal Resistor Tolerance
3
R
AB
/R
AB
T
A
= 25C
-20
+20
%
Resistance Temperature Coefficient
(R
AB
/R
AB
)/Tx10
6
V
AB
= V
DD
, wiper = no connect
35
ppm/C
Wiper
Resistance
R
W
V
DD
= 2.7 V/5.5 V
85/50
150/120
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE
Resolution
N
8
Bits
Differential
Nonlinearity
4
DNL
-1
0.1
+1
LSB
Integral
Nonlinearity
4
INL
-1
0.3
+1
LSB
Voltage Divider Temperature
Coefficient
(V
W
/V
W
)/Tx10
6
Code = 0x80
15
ppm/C
Full-Scale
Error
V
WFSE
Code = 0xFF
-0.5
-0.3
0
LSB
Zero-Scale
Error
V
WZSE
Code = 0x00
0
0.1
0.5
LSB
RESISTOR TERMINALS
Voltage
Range
5
V
A,B,W
GND
V
DD
V
Capacitance
6
A, B
C
A,B
f = 1 MHz, measured to GND,
Code = 0x80
90
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to GND,
Code = 0x80
95
pF
Common-Mode
Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 2.7 V to 5.5 V
1.8
V
Input Logic Low
V
IL
V
DD
= 2.7 V to 5.5 V
0.6
V
Input
Capacitance
6
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5
V
Supply
Current
I
DD
Digital inputs = 0 V or V
DD
0.05
1 A
V
DD
= 2.7 V, digital inputs = 1.8 V
10
A
V
DD
= 5 V, digital inputs = 1.8 V
500
A
Power
Dissipation
7
P
DISS
Digital inputs = 0 V or V
DD
5.5 W
Power Supply Sensitivity
PSS
V
DD
= +5 V 10%,
Code = Midscale
0.001
0.005
%/%
DYNAMIC CHARACTERISTICS
6,
8
Bandwidth -3 dB
BW
Code = 0x80
55
kHz
Total
Harmonic
Distortion
THD
W
V
A
=1 V rms, V
B
= 0 V, f = 1 kHz,
0.05
%
V
W
Settling Time
t
S
V
A
= 5 V, V
B
= 0 V,
1 LSB error band
2
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 50 k
28
nV/Hz
1
Typical specifications represent average readings at +25C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
5
Resistor terminals A, B, and W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
8
All dynamic characteristics use V
DD
= 5 V.
AD5165
Rev. 0 | Page 4 of 16
TIMING CHARACTERISTICS--100 k VERSION
V
DD
= +5 V 10%, or +3 V 10%; V
A
= V
DD
; V
B
= 0 V; -40C < T
A
< +125C; unless otherwise noted.
Table 2.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
3-WIRE INTERFACE TIMING CHARACTERISTICS
2, ,
3 4
(specifications apply to all parts)
Clock
Frequency
f
CLK
= 1/( t
CH
+ t
CL
)
25 MHz
Input Clock Pulse Width
t
CH
, t
CL
Clock level high or low
20
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CS Setup Time
t
CSS
15
ns
CS Low Pulse Width
t
CSW
40
ns
CLK Fall to CS Rise Hold Time
t
CSH0
0
ns
CLK Fall to CS Fall Hold Time
t
CSH1
0
ns
CS Fall to Clock Rise Setup
t
CS1
10
ns
1
Typical specifications represent average readings at +25C and V
DD
= 5 V.
2
Guaranteed by design and not subject to production test.
3
All dynamic characteristics use V
DD
= 5 V.
4
See
and
for location of measured values. All input control voltages are specified with t
Figure 34
Figure 35
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
AD5165
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
T
A
= +25C, unless otherwise noted.
1, 2
Table 3.
Parameter Value
V
DD
to GND
0.3 V to +7 V
V
A
, V
B
, V
W
to GND
V
DD
Maximum Current
I
WB
, I
WA
Pulsed
I
WB
Continuous (R
WB
1
k, A open)
2
I
WA
Continuous (R
WA
1 k, B open)
2
20 mA
5 mA
5 mA
Digital Inputs and Output Voltage to GND
0 V to +7 V
Operating Temperature Range
40C to +125C
Maximum Junction Temperature (T
JMAX
) 150C
Storage Temperature
65C to +150C
Lead Temperature (Soldering, 10 30 sec)
245C
Thermal Resistance
2
JA
: TSOT-8
200C/W
1
Maximum terminal current is bounded by the maximum current handling
of the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
JMAX
- TA)/
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5165
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
A
B
CS
SDI
1
2
3
4
5
8
7
6
W
V
DD
GND
CLK
TOP VIEW
(Not to Scale)
AD5165
04749-0-002
Figure 4.
Table 4.
Pin Name Description
1
W
Wiper terminal. GND V
A
V
DD.
2 V
DD
Positive Power Supply.
3 GND Digital
Ground.
4
CLK
Serial Clock Input. Positive-edge triggered.
5
SDI
Serial Data Input (data loads MSB first).
6
CS
Chip Select Input, active high. When CS returns low, data is loaded into the wiper register.
7
B
B terminal. GND V
A
V
DD
.
8
A
A terminal. GND V
A
V
DD
.
AD5165
Rev. 0 | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE INL (LSB)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-011
5.5V
2.7V
Figure 5. R-INL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RE
HOS
T
AT MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-013
5.5V
2.7V
Figure 6. R-DNL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-006
40C
+25C
+85C
+125C
Figure 7. INL vs. Code vs. Temperature , V
DD
= 5 V
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-008
40C
+25C
+85C
+125C
Figure 8. DNL vs. Code vs. Temperature, V
DD
= 5 V
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-007
5.5V
2.7V
Figure 9. INL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-009
5.5V
2.7V
Figure 10. DNL vs. Code vs. Supply Voltages
AD5165
Rev. 0 | Page 8 of 16
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHEOSTAT MODE INL (LSB)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-010
40C
+25C
+85C
+125C
Figure 11. R-INL vs. Code vs. Temperature, V
DD
= 5 V
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHE
OS
TAT MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-012
40C
+25C
+85C
+125C
Figure 12. R-DNL vs. Code vs. Temperature, V
DD
= 5 V
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
FSE (LSB)
40
20
20
0
40
60
80
100
120
TEMPERATURE (C)
04749-0-023
FSE @ V
DD
= 5.5V
FSE @ V
DD
= 2.7V
Figure 13. Full-Scale Error vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
ZSE (
L
SB
)
40
20
20
0
40
60
80
100
120
TEMPERATURE (C)
04749-0-022
ZSE @ V
DD
= 5.5V
ZSE @ V
DD
= 2.7V
Figure 14. Zero-Scale Error vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
SU
PPLY C
U
R
R
E
N
T
(
A)
40
20
20
0
40
60
80
100
120
TEMPERATURE (C)
04749-0-020
I
DD
@ V
DD
= 5.5V
I
DD
@ V
DD
= 2.7V
Figure 15. Supply Current vs. Temperature
0.01
0.1
1
10
100
1000
10000
I
DD
(
A)
0
1
2
3
4
5
V
IH
(0) (V)
04749-0-025
V
DD
= V
A
= 5V
V
DD
= V
A
= 2.7V
Figure 16. Supply Current vs. Digital Input Voltage
AD5165
Rev. 0 | Page 9 of 16
0.01
0.1
1
10
100
1000
I
DD
(
A)
0
1
2
3
4
5
V
IH
(1MHz) (V)
04749-0-026
V
DD
= V
A
= 5V
V
DD
= V
A
= 2.7V
Figure 17. Supply Current vs. Digital Input Voltage
20
15
10
5
0
5
RHE
O
S
T
AT MODE
TE
MCO (ppm/
C)
10
15
20
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-015
Figure 18. Rheostat Mode Tempco R
WB
/T vs. Code
8
6
4
2
0
2
P
O
TE
NTIOME
TE
R MODE
TE
MP
CO (ppm/
C)
4
6
8
128
96
32
64
0
160
192
224
256
CODE (Decimal)
04749-0-014
Figure 19. Potentiometer Mode Tempco V
WB
/T vs. Code
1k
10k
100k
1M
0
6
12
18
24
30
36
42
48
54
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R)
9.052dB
START 1 000.000Hz STOP 1 000 000.000Hz
04749-0-048
Figure 20. Gain vs. Frequency vs. Code, R
AB
= 100 k
10k
10M
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
REF LEVEL
5.000dB
/DIV
0.500dB
START 1 000.000Hz STOP 1 000 000.000Hz
R = 100k
100k
54kHz
04749-0-047
Figure 21. 3 dB Bandwidth @ Code = 0x80
PSR
R
(
dB
)
0
20
40
60
80
FREQUENCY (Hz)
1k
100
10k
100k
1M
04749-0-019
CODE = 80
H
, V
A
= V
DD
, V
B
= 0V
PSRR @ V
DD
= 5V DC 10% p-p AC
PSRR @ V
DD
= 3V DC 10% p-p AC
Figure 22. PSRR vs. Frequency
AD5165
Rev. 0 | Page 10 of 16
0
100
200
300
400
500
I
DD
(
A)
600
700
800
FREQUENCY (Hz)
10k
1M
100k
10M
04749-0-018
V
DD
= 5V
CODE 55
H
CODE FF
H
Figure 23. I
DD
vs. Frequency
VW
CS
Ch 1 200mV
BW
Ch 2 5.00 V
BW
M 100ns A CH2 3.00 V
1
2
04749-0-030
Figure 24. Large Signal Settling Time, Code 0xFF0x00
VW
CLK
Ch 1 200mV
BW
Ch 2 5.00 V
BW
M 100ns A CH2 3.00 V
1
2
04749-0-030
Figure 25. Digital Feedthrough
VW
CS
Ch 1 100mV
BW
Ch 2 5.00 V
BW
M 200ns A CH1 152mV
1
2
V
A
= 5V
V
B
= 0V
04749-0-028
Figure 26. Midscale Glitch, Code 0x800x7F
AD5165
Rev. 0 | Page 11 of 16
TEST CIRCUITS
Figure 27 to Figure 33 illustrate the test circuits that define the test conditions used in the product specification tables.
V
MS
A
W
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
04749-0-031
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error
(INL, DNL)
NO CONNECT
I
W
V
MS
A W
B
DUT
04749-0-032
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V
MS2
V
MS1
V
W
A
W
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
V
MS2
]/I
W
04749-0-033
Figure 29. Test Circuit for Wiper Resistance
04749-0-034
V
MS
%
DD
%
PSS (%/%) =
V+ = V
DD
10%
PSRR (dB) = 20 LOG
MS
DD
( )
V
DD
V
A
V
MS
A
W
B
V+
V
V
V
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
+15V
15V
W
A
2.5V
B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
04749-0-035
Figure 31. Test Circuit for Gain vs. Frequency
W
B
GND TO V
DD
DUT
I
SW
CODE = 0x00
R
SW
=
0.1V
I
SW
0.1V
04749-0-036
Figure 32. Test Circuit for Incremental ON Resistance
W
B
V
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04749-0-037
Figure 33. Test Circuit for Common-Mode Leakage Current
AD5165
Rev. 0 | Page 12 of 16
3-WIRE DIGITAL INTERFACE
Note that in the AD5165 data is loaded MSB first.
Table 5. AD5165 Serial Data-Word Format
B7
B6 B5 B4 B3 B2 B1 B0
D7
D6 D5 D4 D3 D2 D1 D0
MSB
LSB
2
7
2
0
SDI
CLK
CS
VOUT
1
0
1
0
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
RDAC REGISTER LOAD
04749-0-004
Figure 34. 3-Wire Digital Interface Timing Diagram
(V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
t
CSHO
t
CSS
t
CL
t
CH
t
DS
t
CSW
t
S
t
CS1
t
CSH1
t
DH
SDI
CLK
CS
VOUT
1
0
1
0
1
0
V
DD
0
1LSB
(DATA IN)
Dx
Dx
04749-0-005
Figure 35. 3-Wire Digital Interface Detailed Timing Diagram (V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
AD5165
Rev. 0 | Page 13 of 16
THEORY OF OPERATION
The AD5165 is a 256-position digitally controlled variable
resistor (VR) device.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 100 k. The nominal resistance (R
AB
) of the VR
has 256 contact points accessed by the wiper terminal, plus the
B terminal contact. The 8-bit data in the RDAC latch is decoded
to select one of the 256 possible settings.
A
W
B
A
W
B
A
W
B
04749-0-038
Figure 36. Rheostat Mode Configuration
Assuming that a 100 k part is used, the wiper's first connec-
tion starts at the B terminal for data 0x00. Because there is a
50 wiper contact resistance, such a connection yields a mini-
mum of 100 (2 50 ) resistance between terminals W and
B. The second connection is the first tap point, which corres-
ponds to 490 (R
WB
= R
AB
/256 + 2 R
W
= 390 + 2 50 )
for data 0x01. The third connection is the next tap point,
representing 880 (2 390 + 2 50 ) for data 0x02, and
so on. Each LSB data value increase moves the wiper up the
resistor ladder until the last tap point is reached at 100,100
(R
AB
+ 2 R
W
).
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
04749-0-039
Figure 37. AD5165 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB
R
R
D
D
R
+
=
2
256
)
(
(1)
where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
R
AB
is the end-to-end resistance.
R
W
is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if R
AB
= 100 k and the A terminal is open
circuited, the following output resistance R
WB
is set for the
indicated RDAC latch codes.
Table 6. Codes and Corresponding R
WB
Resistance
D (Dec.)
R
WB
()
Output State
255
99,710
Full scale (R
AB
1 LSB + R
W
)
128 50,100
Midscale
1 490
1
LSB
0
100
Zero scale (wiper contact resistance)
Note that, in the zero-scale condition, a finite wiper resistance
of 100 is present. Care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance, R
WA
. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for R
WA
starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
AB
WA
R
R
D
D
R
+
-
=
2
256
256
)
(
(2)
For R
AB
= 100 k with the B terminal open circuited, the
following output resistance R
WA
is set for the indicated RDAC
latch codes.
Table 7. Codes and Corresponding R
WA
Resistance
D (Dec.)
R
WA
()
Output State
255 490 Full
scale
128 50,100
Midscale
1
99, 710
1 LSB
0 100,100
Zero
scale
Typical device-to-device matching is process-lot dependent
and may vary by up to 20%. Because the resistance element
is processed in thin film technology, the change in R
AB
with
temperature has a very low 35 ppm/C temperature coefficient.
AD5165
Rev. 0 | Page 14 of 16
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A to B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A to B, W to A, and W to B can be at
either polarity.
A
V
I
W
B
V
O
04749-0-040
Figure 38. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V
up to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminals A and B divided by the 256
positions of the potentiometer divider. The general equation
defining the output voltage at V
W
with respect to ground for any
valid input voltage applied to terminals A and B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
-
+
=
(3)
A more accurate calculation, which includes the effect of wiper
resistance, V
W
, is
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/C.
3-WIRE SERIAL BUS DIGITAL INTERFACE
The AD5165 contains a 3-wire digital interface (SDI, CS, and
CLK). The 8-bit serial word must be loaded MSB first. The
format of the word is shown in Table 5.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is high, the clock
loads data into the serial register on each positive clock edge,
as shown in Figure 34.
The data setup and data hold times in the specifications table
determine the valid timing requirements. The AD5165 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic low.
Extra MSB bits are ignored.
ESD PROTECTION
All digital inputs are protected with a series of input resistors
and parallel Zener ESD structures, shown in Figure 39 and
Figure 40. This applies to the digital input pins SDI, CLK,
and CS.
LOGIC
340
GND
04749-0-041
Figure 39. ESD Protection of Digital Pins
A, B, W
GND
04749-0-042
Figure 40. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5165 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer oper-
ation. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND are clamped by the internal forward-biased
diodes, as shown in Figure 41.
GND
A
W
B
V
DD
04749-0-043
Figure 41. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at terminals A, B, and W (see Figure 41), it is important to
power V
DD
/GND before applying any voltage to terminals A, B,
and W; otherwise, the diode is forward biased such that V
DD
is
powered unintentionally and may affect the rest of the user's
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A
, V
B
, and V
W
. The relative
order of powering V
A
, V
B
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/GND.
AD5165
Rev. 0 | Page 15 of 16
LAYOUT AND POWER SUPPLY BYPASSING
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disk or chip ceramic
capacitors of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 42). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
V
DD
GND
V
DD
C3
10
F
C1
0.1
F
AD5165
+
04749-0-044
Figure 42. Power Supply Bypassing
EVALUATION BOARD
An evaluation board, along with all necessary software, is
available to program the AD5165 from any PC running
Windows 98/2000/XP. The graphical user interface, as shown
in Figure 43, is straightforward and easy to use. More detailed
information is available in the user manual, which comes with
the board.
04749-0-046
Figure 43. AD5165 Evaluation Board Software
The AD5165 starts at midscale upon power-up. To increment
or decrement the resistance, the user may move the scroll bars
on the left. To write any specific value, the user should use the
bit pattern in the upper screen and click the Run button. The
format of writing data to the device is shown in Figure 32.
AD5165
Rev. 0 | Page 16 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-193BA
1
3
5
6
2
8
4
7
2.90 BSC
PIN 1
INDICATOR
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.10 MAX
0.90
0.87
0.84
SEATING
PLANE
1.00 MAX
0.20
0.08
0.60
0.45
0.30
8
4
0
2.80 BSC
Figure 44. 8-Lead Thin Small Outline Transistor Package [Thin SOT-23]
(UJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model R
AB
()
Temperature
Package Description
Package Option
Quantity on Reel
Branding
AD5165BUJZ100-R2
1
100 k
40C to +125C
Thin SOT-23
UJ-8
250
D3N
AD5165BUJZ100-R7
1
100 k
40C to +125C
Thin SOT-23
UJ-8
3,000
D3N
AD5165EVAL
Evaluation
Board
1
Z = Pb-free part.
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0474904/04(0)
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL OVERVIEW
- FUNCTIONAL BLOCK DIAGRAM
- PIN CONFIGURATION
- TYPICAL APPLICATION
-
-
-
-
-
-
-
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