AD5222 Data Sheet

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD5222

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

Increment/Decrement

Dual Digital Potentiometer

FUNCTIONAL BLOCK DIAGRAM

DECODE

UP/DOWN

COUNTER

AD5222

DECODE

UP/DOWN

COUNTER

POR

DAC

SELECT

AND

ENABLE

CLK

DACSEL

MODE

GND

FEATURES
128-Position, 2-Channel
Potentiometer Replacement
10 k

, 50 k

, 100 k , 1 M

Very Low Power: 40 A Max

2.7 V Dual Supply Operation or

2.7 V to 5.5 V Single Supply Operation

Increment/Decrement Count Control

APPLICATIONS
Stereo Channel Audio Level Control
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Line Impedance Matching

GENERAL DESCRIPTION

The AD5222 provides a dual channel, 128-position, digitally
controlled variable-resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. Choices between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.

The AD5222 contains two fixed resistors with wiper contacts that
tap the fixed resistor value at a point determined by a digitally
controlled up/down counter. The resistance between the wiper
and either end point of the fixed resistor provides a constant
resistance step size that is equal to the end-to-end resistance
divided by the number of positions (e.g., R

STEP

= 10 k

/128 =

). The variable resistor offers a true adjustable value of

resistance, between Terminal A and the wiper, or Terminal B
and the wiper. The fixed A-to-B terminal resistance of 10 k

50 k

, 100 k

, or 1 M

has a nominal temperature coefficient

of 35 ppm/

The chip select

CS, count CLK and U/D direction control inputs

set the variable resistor position. The MODE determines whether
both VRs are incremented together or independently. With
MODE at logic zero, both wipers are incremented UP or DOWN
without changing the relative settings between the wipers. Also,
the relative ratio between the wipers is preserved if either wiper
reaches the end of the resistor array. In the independent MODE
(Logic 1) only the VR determined by the DACSEL pin is changed.
DACSEL (Logic 0) changes RDAC 1. These inputs, which con-
trol the internal up/down counter, can be easily generated with

mechanical or push-button switches (or other contact closure
devices). This simple digital interface eliminates the need for
microcontrollers in front panel interface designs.

The AD5222 is available in the surface-mount (SO-14) package.
For ultracompact solutions, selected models are available in the
thin TSSOP-14 package. All parts are guaranteed to operate
over the extended industrial temperature range of 40

C to

+85

C. For 3-wire, SPI-compatible interface applications, see

the AD5203/AD5204/AD5206, AD7376, and AD8400/AD8402/
AD8403 products.

CLK

DACSEL

MODE

GND

INCREMENT

Figure 1. Typical Push-Button Control Application

REV. 0

AD5222SPECIFICATIONS

= 3 V 10% or 5 V 10%, V

= 0 V, V

= +V

, V

= 0 V, 40 C < T

< +85 C,

unless otherwise noted.)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL

R-DNL

, V

= NC

1/4 +1

LSB

Resistor Nonlinearity

R-INL

, V

= NC

0.4 +1

LSB

Nominal Resistor Tolerance

= V

, Wiper = No Connect, T

= 25

+30

Resistance Temperature Coefficient

= V

, Wiper = No Connect

ppm/

Wiper Resistance

= V

/R, V

= 3 V or 5 V

100

Nominal Resistance Match

R/R

CH 1 to 2, V

= V

, T

= 25

0.2

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Resolution

Bits

Integral Nonlinearity

INL

= 10 k

, 50 k

, or 100 k

1/4 +1

LSB

INL

= 1 M

1/2 +2

LSB

Differential Nonlinearity

DNL

1/4 +1

LSB

Voltage Divider Temperature Coefficient

Code = 40

ppm/

Full-Scale Error

WFSE

Code = 7F

0.5

LSB

Zero-Scale Error

WZSE

Code = 00

0.5

LSB

RESISTOR TERMINALS

Voltage Range

A, B, W

Capacitance

A, B

f = 1 MHz, Measured to GND, Code = 40

Capacitance

f = 1 MHz, Measured to GND, Code = 40

Common-Mode Leakage

= V

DIGITAL INPUTS AND OUTPUTS

Input Logic High

= 5 V/3 V

2.4/2.1

Input Logic Low

= 5 V/3 V

0.8/0.6 V

Input Current

= 0 V or 5 V

Input Capacitance

POWER SUPPLIES

Power Single-Supply Range

DD RANGE

= 0 V

2.7

5.5

Power Dual-Supply Range

DD/SS RANGE

2.3

2.7

Positive Supply Current

= 5 V or V

= 0 V

Negative Supply Current

= 2.5 V, V

= +2.7 V

Power Dissipation

DISS

= 5 V or V

= 0 V, V

= 5 V

150

400

Power Supply Sensitivity

PSS

0.002 0.05

%/%

DYNAMIC CHARACTERISTICS

6, 8, 9

Bandwidth 3 dB

BW_10K

= 10 k

, Code = 40

1000

kHz

BW_50K

= 50 k

, Code = 40

180

kHz

BW_100K

= 100 k

, Code = 40

kHz

BW_1M

= 500 k

, Code = 40

kHz

Total Harmonic Distortion

THD

= 1 V rms + 2 V dc, V

= 2 V dc, f = 1 kHz

0.005

Settling Time

= 10 k

1 LSB Error Band

Resistor Noise Voltage

N_WB

= 5 k

, f = 1 kHz

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts)

6, 10

Input Clock Pulsewidth

, t

Clock Level High or Low

CS to CLK Setup Time

CSS

CS Rise to CLK Hold Time

CSH

D to Clock Fall Setup Time

UDS

D to Clock Fall Hold Time

UDH

DACSEL to Clock Fall Setup Time

DSS

DACSEL to Clock Fall Hold Time

DSH

MODE to Clock Fall Setup Time

MDS

MODE to Clock Fall Hold Time

MDH

NOTES

Typicals represent average readings at 25

C, V

= 5 V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.

Wiper resistance is not measured on the R

= 1 M

models.

INL and DNL are measured at V

with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V

= V

and V

= 0 V. DNL

specification limits of

1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

DISS

is calculated from (I

). CMOS logic level inputs result in minimum power dissipation.

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

All dynamic characteristics use V

= 5 V.

See timing diagram for location of measured values. All input control voltages are specified with t

= t

= 2.5 ns (10% to 90% of +3 V) and timed from a voltage level

of 1.5 V. Switching characteristics are measured using both V

= 5 V or V

= 3 V.

Specifications subject to change without notice.

AD5222

REV. 0

ABSOLUTE MAXIMUM RATINGS

= 25

C, unless otherwise noted)

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 5 V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

, V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

, A

, B

. . . . . . . . . . . . . . . . . . .

20 mA

Digital Input Voltage to GND . . . . . . . . . . . . 0 V, V

+ 0.3 V

Operating Temperature Range . . . . . . . . . . . 40

C to +85

Maximum Junction Temperature (T

max) . . . . . . . . . . 150

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300

Package Power Dissipation . . . . . . . . . . . . . (T

max T

Thermal Resistance

SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

C/W

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

C/W

CSS

CSH

UDS

CLK

DSS

DACSEL

MDS

MODE

UDH

DSH

MDH

Figure 2. Detail Timing Diagram

Truth Table

CLK

Operation

Wiper Increment Toward Terminal A

Wiper Decrement Toward Terminal B

Wiper Position Fixed

Common Mode (MODE = 0) moves both wipers together either
UP or DOWN the resistor array without changing the relative
distance between the wipers. Also, the distance between both
wipers is preserved if either reaches the end of the array. Inde-
pendent Mode (MODE = 1) allows user to control each RDAC
individually: DACSEL = 0 sets RDAC1; DACSEL = 1: sets
RDAC2.

ORDERING GUIDE

Kilo

Package

Model

Ohms Temperature Description Option

AD5222BR10

C/+85

SO-14

R-14

AD5222BRU10

C/+85

TSSOP-14

RU-14

AD5222BR50

C/+85

SO-14

R-14

AD5222BRU50

C/+85

TSSOP-14

RU-14

AD5222BR100

100

C/+85

SO-14

R-14

AD5222BRU100 100

C/+85

TSSOP-14

RU-14

AD5222BR1M

1,000

C/+85

SO-14

R-14

AD5222BRU1M 1,000

C/+85

TSSOP-14

RU-14

The AD5222 die size is 56 mil

60 mil, 3360 sq. mil; 1.4224 mm

1.524 mm,

2.1677 sq. mm. Contains 1503 transistors. Patent Number 5495245 applies.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5222 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN FUNCTION DESCRIPTIONS

Pin Name

Description

B Terminal RDAC #1.

A Terminal RDAC #1.

Wiper RDAC #1, DACSEL = 0.

Negative Power Supply. Specified for operation
at both 0 V or 2.7 V (Sum of |V

| + |V

< 5.5 V).

Wiper RDAC #2, DACSEL = 1.

A Terminal RDAC #2.

B Terminal RDAC #2.

GND

Ground.

MODE

Common MODE = 0, Independent MODE = 1.

DACSEL DAC Select determines which wiper is incre-

mented in the Independent MODE = 1.
DACSEL = 0 sets RDAC1, DACSEL = 1 sets
RDAC2.

UP/DOWN Direction Control.

CLK

Serial Clock Input, Negative Edge Triggered.

Chip Select Input, Active Low. When

CS is

high, the UP/DOWN counter is disabled.

Positive Power Supply. Specified for operation
at both +3 V or +5 V. (Sum of |V

| + |V

< 5.5 V).

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

CLK

GND

AD5222

DACSEL

MODE

PERCENT OF NOMINAL

END-TO-END RESISTANCE % R

100

128

CODE Decimal

Figure 3. Wiper-To-End Terminal Resistance vs. Code

CURRENT mA

= 10k

= 5V

= 25 C

0.5

1.5

2.5

3.5

4.5

VOLTAGE V

Figure 4. Resistance Linearity vs. Conduction Current

180

WIPER RESISTANCE 

FREQUENCY

47 48

50 51

53 54

56 57 59

120

150

SS = 600 UNITS
V

= 2.7V

= 25 C

Figure 5. Wiper Contact Resistance

AD5222Typical Performance Characteristics

REV. 0

CODE Decimal

0.25

128

R-DNL ERROR LSB

112

0.20

0.05

0.15

0.20

0.15

0.10

= +25 C

= +85 C

= 55 C

= +15V

= 15V

= 50k

Figure 6. R-DNL Relative Resistance Step Position
Change vs. Code

CODE Decimal

1.0

128

R-INL ERROR LSB

112

0.8

0.2

0.6

0.8

0.6

0.4

= 2.7V/0V

= 25 C

50k VERSION

100k VERSION

1M VERSION

10k VERSION

Figure 7. R-INL Resistance Nonlinearity Error vs. Code

CODE Decimal

1.0

128

INL

 LSB

112

0.2

0.6

0.8

0.6

0.4

= 2.7V/0V

= 25 C

50k VERSION

100k VERSION

1M VERSION

10k VERSION

Figure 8. Potentiometer Divider INL Error vs. Code

AD5222

REV. 0

CODE Decimal

30

128

POTENTIOMETER MODE TEMPCO ppm/

112

10

20

= 2.7V/0V

= 25 C

50k VERSION

100k VERSION

1M VERSION

10k VERSION

Figure 9.

/ T Potentiometer Mode Tempco

CODE Decimal

120

80

128

RHEOSTAT MODE TEMPCO ppm/

112

100

20

40

60

50k

VERSION

10k VERSION

100k VERSION

1M VERSION

= 2.7V/0V

= 25 C

Figure 10.

/ T Rheostat Mode Tempco

FREQUENCY Hz

50

GAIN - dB 30

100

10k

100k

10

20

40

10M

CODE = 3F

= 25 C

SEE TEST CIRCUIT FIGURE 32

Figure 11. 10 k

Gain vs. Frequency vs. Code

FREQUENCY Hz

12

GAIN dB

100

10k

100k

15

18

21

= +2.7V

= 2.7V

DATA = 40

= 50mV rms

= 0V

10k 764kHz
50k 132kHz
100k 64kHz
1M 6.6kHz

OP42

50k

100k

10k

Figure 12. Gain vs. Frequency vs. R

FREQUENCY Hz

100k

THD + NOISE %

100

10k

0.001

FILTER = 22kHz
V

= 2.7V

= 1V rms

= 25 C

SEE TEST CIRCUIT FIGURE 26

SEE TEST CIRCUIT FIGURE 25

0.01

0.1

1.0

Figure 13. Total Harmonic Distortion Plus Noise vs.
Frequency

FREQUENCY Hz

NORMALIZED GAIN FLATNESS 0.1dB/DIV

100

10k

100k

SEE TEST CIRUIT 27
V

= 2.7V

= 50mV rms

= 0V

DATA = 40

OP42

10k

50k

100k

Figure 14. Normalized Gain Flatness vs. Frequency

AD5222

REV. 0

FREQUENCY Hz

1200

10M

 SUPPLY CURRENT 

1000

10k

100k

800

600

400

200

A V

= 5.5V

CODE = 15

B V

= 3.3V

CODE = 15

C V

= 5.5V

CODE = 3F

D V

= 3.3V

CODE = 3F

= 25 C

Figure 15. I

, I

Supply Current vs. Clock Frequency

COMMON MODE Volts

SWITCH RESISTANCE 

100

= 25 C

= 2.7V

= 5.5V/0V

= 2.7V/0V

Figure 16. Incremental Wiper Contact Resistance vs.
V

/ V

TEMPERATURE C

0.1

0.001

40

15

SUPPLY CURRENT mA

0.01

LOGIC = 0V OR V

= 2.7V

= 5.5V OR V

= 2.7V

Figure 17. Supply Current vs. Temperature

INPUT LOGIC VOLTAGE V

0.001

SUPPLY CURRENT mA

0.01

= 5.5V

= 2.5V

= 2.7V

0.1

Figure 18. Supply Current vs. Input Logic Voltage

20mV/DIV

CLK

2V/DIV

= 2.7V

= 0V

Figure 19. Midscale Transition 3F

to 40

20mV/DIV

= 2.7V

= 0V

CLK

2V/DIV

Figure 20. Stereo Step Transition, Mode = 0

Parametric Test CircuitsAD5222

REV. 0

V+

DUT

V+ = V

1LSB = V+/128

Figure 21. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)

NO CONNECT

DUT

Figure 22. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)

MS2

NOMINAL

DUT

MS1

= [V

MS1

 V

MS2

]/I

Figure 23. Wiper Resistance Test Circuit

PSRR (dB) = 20 LOG

(

)

PSS (%/%) = 

V+ = V

± 10%

V+

Figure 24. Power Supply Sensitivity Test Circuit (PSS,
PSRR)

OP279

+5V

OUT

DUT

5V

Figure 25. Inverting Programmable Gain Test Circuit

+5V

5V

OUT

DUT

OP279

Figure 26. Noninverting Programmable Gain Test Circuit

DUT

OP42

+15V

OUT

15V

Figure 27. Gain vs. Frequency Test Circuit

0 TO V

0.1V

CODE = 00

0.1V

DUT

Figure 28. Incremental ON Resistance Test Circuit

AD5222

REV. 0

OPERATION

The AD5222 provides a 128-position, digitally-controlled, variable
resistor (VR) device. Changing the VR settings is accomplished
by pulsing the CLK pin while

CS is active low. The U/D (UP/

DOWN) control input pin controls the direction of the increment.
When the wiper hits the end of the resistor (Terminal A or B)
additional CLK pulses no longer change the wiper setting. The
wiper position is immediately decoded by the wiper decode logic
changing the wiper resistance. Appropriate debounce circuitry is
required when push-button switches are used to control the
count sequence and direction of count. The exact timing require-
ments are shown in Figure 2. The AD5222 powers ON in a
centered wiper position, exhibiting nearly equal resistances of
R

and R

DECODE

UP/DOWN

COUNTER

AD5222

DECODE

UP/DOWN

COUNTER

POR

DAC

SELECT

AND

ENABLE

CLK

DACSEL

MODE

GND

Figure 29. Block Diagram

DIGITAL INTERFACING OPERATION

The AD5222 contains a push-button controllable interface. The
active inputs are clock (CLK),

CS and up/down (U/D). While

the MODE, and DACSEL pins control common updates or
individual updates. The negative-edge sensitive CLK input
requires clean transitions to avoid clocking multiple pulses into
the internal UP/DOWN counter register, Figure 30. Standard
logic families work well. If mechanical switches are used for
product evaluation a flip-flop or other suitable means should
debounce them. When

CS is taken active low, the clock begins

to increment or decrement the internal up/down counter, depen-
dent upon the state of the U/

D control pin. The UP/DOWN

counter value (D) starts at 40

at system power ON. Each new

CLK pulse will increment the value of the internal counter by
1 LSB until the full-scale value of 7F

is reached, as long as the

D pin is logic high. If the U/D pin is taken to logic low, the

counter will count down, stopping at code 00

(zero-scale).

Additional clock pulses on the CLK pin are ignored when the
wiper is at either the 00

position or the 7F

position. The

detailed digital logic interface circuitry is shown in Figure 30.

RDAC 1

COUNTER

RDAC 2

COUNTER

CLK

DACSEL

MODE

Figure 30. Detailed Digital Logic Interface Circuit

All digital inputs (

CS, U/D, CLK, MODE, DACSEL) are

protected with a series input resistor and parallel Zener ESD
structure shown in Figure 31. All potentiometer terminal pins
(A, B, W) are protected from ESD as shown in Figure 32.

LOGIC

Figure 31. Equivalent ESD Protection Digital Pins

A, B, W

Figure 32. Equivalent ESD Protection Analog Pins

D0
D1
D2
D3
D4
D5
D6

RDAC

UP/DOWN

CNTR

DECODE

= R

NOMINAL

/128

Figure 33. AD5222 Equivalent RDAC Circuit

AD5222

REV. 0

PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation

The nominal resistance of the RDAC between Terminals A and
B are available with values of 10 k

, 50 k

, 100 k

, and 1 M

The final three characters of the part number determine the
nominal resistance value, e.g., 10 k

= 10; 50 k

= 50; 100 k

= 100; 1 M

= 1M. The nominal resistance (R

) of the VR

has 128 contact points accessed by the wiper terminal, plus the
B terminal contact. At power ON, the resistance from the wiper
to either end Terminal A or B is approximately equal. Pulsing
the CLK pin will increase the resistance from the wiper W to
Terminal B by one unit of R

resistance, see Figure 33. The

resistance R

is determined by the number of pulses applied to

the clock pin. Each segment of the internal resistor string has a
nominal resistance value of R

= R

/128, which becomes 78

in the case of the 10 k

AD5222BR10 product. Care should be

taken to limit the current flow between W and B in the direct
contact state (R

code = 0) to a maximum value of 20 mA to

avoid degradation or possible destruction of the internal switch
contact.

Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical (see Figure 3). The resistance between the
wiper W and Terminal A also produces a digitally controlled
resistance R

. When these terminals are used the B-terminal

should be tied to the wiper.

The typical part-to-part distribution of R

is process-lot-

dependent having a

30% variation. The change in R

with

temperature has a 35 ppm/

C temperature coefficient.

The R

temperature coefficient increases as the wiper is pro-

grammed near the B-terminal due to the larger percentage
contribution of the wiper contact switch resistance, which has a
0.5%/

C temperature coefficient. Figures 9 and 10 show the

effect of the wiper contact resistance as a function of code setting.

PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation

The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A-terminal to 5 V and B-terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than 5 V. Each
LSB of voltage is equal to the voltage applied across Terminals
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to Termi-
nals AB is:

(D) = D/128

+ V

(1)

D represents the current contents of the internal up/down counter.

Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors
not the absolute value, therefore, the drift improves to 20 ppm/

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