REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5304/AD5314/AD5324*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
2.5 V to 5.5 V, 500 A, Quad Voltage Output
8-/10-/12-Bit DACs in 10-Lead microSOIC
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
V
OUT
A
BUFFER
DAC
REGISTER
STRING
DAC A
V
DD
REFIN
GND
AD5304/AD5314/AD5324
INPUT
REGISTER
V
OUT
B
BUFFER
DAC
REGISTER
INPUT
REGISTER
V
OUT
C
BUFFER
DAC
REGISTER
INPUT
REGISTER
V
OUT
D
BUFFER
DAC
REGISTER
POWER-ON
RESET
SYNC
SCLK
DIN
INTERFACE
LOGIC
POWER-DOWN
LOGIC
LDAC
STRING
DAC B
STRING
DAC C
STRING
DAC D
FEATURES
AD5304
Four Buffered 8-Bit DACs in 10-Lead microSOIC
AD5314
Four Buffered 10-Bit DACs in 10-Lead microSOIC
AD5324
Four Buffered 12-Bit DACs in 10-Lead microSOIC
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0V
REF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (
LDAC Function)
Low Power, SPITM, QSPITM, MICROWIRETM, and
DSP-Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range 40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500
A at 3 V. Their on-chip output amplifiers allow rail-to-
rail output swing to be achieved with a slew rate of 0.7 V/
s.
A 3-wire serial interface is used which operates at clock rates
up to 30 MHz and is compatible with standard SPI, QSPI,
MICROWIRE and DSP interface standards.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software
LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. The parts contain a power-down feature that
reduces the current consumption of the device to 200 nA @ 5 V
(80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1
W in power-down mode.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
2
REV. B
AD5304/AD5314/AD5324SPECIFICATIONS
(V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k
to
GND; C
L
= 200 pF to GND; All specifications T
MIN
to T
MAX
unless otherwise noted.)
B Version
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5304
Resolution
8
Bits
Relative Accuracy
0.15
1
LSB
Differential Nonlinearity
0.02
0.25
LSB
Guaranteed Monotonic by Design Over All Codes
AD5314
Resolution
10
Bits
Relative Accuracy
0.5
4
LSB
Differential Nonlinearity
0.05
0.5
LSB
Guaranteed Monotonic by Design Over All Codes
AD5324
Resolution
12
Bits
Relative Accuracy
2
16
LSB
Differential Nonlinearity
0.2
1
LSB
Guaranteed Monotonic by Design Over All Codes
Offset Error
0.4
3
% of FSR
See Figures 2 and 3
Gain Error
0.15
1
% of FSR
See Figures 2 and 3
Lower Deadband
20
60
mV
Lower Deadband Exists Only If Offset Error Is Negative
Offset Error Drift
5
12
ppm of FSR/
C
Gain Error Drift
5
5
ppm of FSR/
C
DC Power Supply Rejection Ratio
5
60
dB
V
DD
=
10%
DC Crosstalk
5
200
V
R
L
= 2 k
to GND or V
DD
DAC REFERENCE INPUTS
5
V
REF
Input Range
0.25
V
DD
V
V
REF
Input Impedance
37
45
k
Normal Operation
>10
M
Power-Down Mode
Reference Feedthrough
90
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
6
0.001
V
This is a measure of the minimum and maximum drive
Maximum Output Voltage
6
V
DD
0.001
V
capability of the output amplifier.
DC Output Impedance
0.5
Short Circuit Current
25
mA
V
DD
= 5 V
16
mA
V
DD
= 3 V
Power-Up Time
2.5
s
Coming Out of Power-Down Mode. V
DD
= 5 V
5
s
Coming Out of Power-Down Mode. V
DD
= 3 V
LOGIC INPUTS
5
Input Current
1
A
V
IL
, Input Low Voltage
0.8
V
V
DD
= 5 V
10%
0.6
V
V
DD
= 3 V
10%
0.5
V
V
DD
= 2.5 V
V
IH
, Input High Voltage
2.4
V
V
DD
= 5 V
10%
2.1
V
V
DD
= 3 V
10%
2.0
V
V
DD
= 2.5 V
Pin Capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.5
5.5
V
I
DD
(Normal Mode)
7
V
DD
= 4.5 V to 5.5 V
600
900
A
V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.5 V to 3.6 V
500
700
A
V
IH
= V
DD
and V
IL
= GND
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
0.2
1
A
V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.5 V to 3.6 V
0.08
1
A
V
IH
= V
DD
and V
IL
= GND
NOTES
1
See Terminology.
2
Temperature range: B Version: 40
C to +105C; typical at 25C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5304 (Code 8 to 248); AD5314 (Code 28 to 995); AD5324 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage,
V
REF
= V
DD
and "Offset plus Gain" Error must be positive.
7
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.
3
REV. B
AD5304/AD5314/AD5324
AC CHARACTERISTICS
1
(V
DD
= 2.5 V to 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless
otherwise noted.)
B Version
3
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
V
REF
= V
DD
= 5 V
AD5304
6
8
s
1/4 Scale to 3/4 Scale
Change
(40 Hex to C0 Hex)
AD5314
7
9
s
1/4 Scale to 3/4 Scale
Change
(100 Hex to 300 Hex)
AD5324
8
10
s
1/4 Scale to 3/4 Scale
Change
(400 Hex to C00 Hex)
Slew Rate
0.7
V/
s
Major-Code Transition Glitch Energy
12
nV-s
1 LSB Change Around Major Carry
Digital Feedthrough
1
nV-s
Digital Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
V
REF
= 2 V
0.1 V p-p
Total Harmonic Distortion
70
dB
V
REF
= 2.5 V
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology.
3
Temperature range: B Version: 40
C to +105C
; typical at 25
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Limit at T
MIN
, T
MAX
Parameter
V
DD
= 2.5 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
Unit
Conditions/Comments
t
1
40
33
ns min
SCLK Cycle Time
t
2
16
13
ns min
SCLK High Time
t
3
16
13
ns min
SCLK Low Time
t
4
0
0
ns min
SYNC to SCLK Rising Edge Setup Time
t
5
5
5
ns min
Data Setup Time
t
6
4.5
4.5
ns min
Data Hold Time
t
7
0
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t
8
80
33
ns min
Minimum
SYNC High Time
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
SCLK
SYNC
DIN
t
2
t
3
t
5
t
6
t
7
t
4
DB15
t
1
DB0
t
8
Figure 1. Serial Interface Timing Diagram
(V
DD
= 2.5 V to 5.5 V. All specifications T
MIN
to T
MAX
unless otherwise noted)
AD5304/AD5314/AD5324
4
REV. B
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . 0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . 0.3 V to V
DD
+ 0.3 V
V
OUT
AD
to GND . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40
C to +105C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . 150
C
10-Lead microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . (T
J
max T
A
)/
JA
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206
C/W
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44
C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/0
C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
10
9
8
7
6
1
2
3
4
5
V
DD
V
OUT
A
GND
DIN
SCLK
SYNC
V
OUT
D
AD5304/
AD5314/
AD5324
V
OUT
B
V
OUT
C
REFIN
PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
V
DD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND.
2
V
OUT
A
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3
V
OUT
B
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4
V
OUT
C
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
5
REFIN
Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
DD
.
6
V
OUT
D
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7
GND
Ground Reference Point for All Circuitry on the Part.
8
DIN
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input. The DIN input buffer is powered down after each write cycle.
9
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
10
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If
SYNC is
taken high before the sixteenth falling edge of SCLK, the rising edge of
SYNC acts as an interrupt and the
write sequence is ignored by the device.
ORDERING GUIDE
Temperature
Package
Package
Branding
Model
Range
Description
Option
Information
AD5304BRM
40
C to +105C
10-Lead microSOIC
RM-10
DBB
AD5314BRM
40
C to +105C
10-Lead microSOIC
RM-10
DCB
AD5324BRM
40
C to +105C
10-Lead microSOIC
RM-10
DDB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5304/AD5314/AD5324 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD5304/AD5314/AD5324
5
REV. B
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of
1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.
OFFSET ERROR
This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
OFFSET ERROR DRIFT
This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/
C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/
C.
POWER-SUPPLY REJECTION RATIO (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
OUT
to
a change in V
DD
for full-scale output of the DAC. It is measured
in dBs. V
REF
is held at 2 V and V
DD
is varied
10%.
DC CROSSTALK
This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in
V.
REFERENCE FEEDTHROUGH
This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not being
updated. It is expressed in dBs.
MAJOR-CODE TRANSITION GLITCH ENERGY
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the device
when the DAC output is not being written to (
SYNC held high). It
is specified in nV-secs and is measured with a worst-case change on
the digital input pins, e.g., from all 0s to all 1s or vice versa.
DIGITAL CROSSTALK
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.
DAC-TO-DAC CROSSTALK
This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the
LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.
MULTIPLYING BANDWIDTH
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.
TOTAL HARMONIC DISTORTION
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.
ACTUAL
IDEAL
GAIN ERROR
PLUS
OFFSET ERROR
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
ERROR
DAC CODE
AMPLIFIER
FOOTROOM
(1mV)
NEGATIVE
OFFSET
ERROR
DEADBAND CODES
Figure 2. Transfer Function with Negative Offset
OUTPUT
VOLTAGE
POSITIVE
OFFSET
DAC CODE
GAIN ERROR
PLUS
OFFSET ERROR
ACTUAL
IDEAL
Figure 3. Transfer Function with Positive Offset
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