AD5301/5311/5321 Data Sheet
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5301/AD5311/AD5321*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
+2.5 V to +5.5 V, 120 A, 2-Wire Interface,
Voltage Output 8-/10-/12-Bit DACs
FUNCTIONAL BLOCK DIAGRAM
RESISTOR
NETWORK
BUFFER
V
OUT
DAC
REGISTER
POWER-DOWN
LOGIC
AD5301/AD5311/AD5321
V
DD
SCL
A0
GND
A1*
REF
POWER-ON
RESET
PD
*
SDA
*AVAILABLE ON 8-LEAD VERSION ONLY
8-/10-/12-BIT
DAC
INTERFACE
LOGIC
FEATURES
AD5301: Buffered Voltage Output 8-Bit DAC
AD5311: Buffered Voltage Output 10-Bit DAC
AD5321: Buffered Voltage Output 12-Bit DAC
6-Lead SOT-23 and 8-Lead SOIC Packages
Micropower Operation: 120 A @ 3 V
2-Wire (I
2
C
Compatible) Serial Interface
Data Readback Capability
+2.5 V to +5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 50 nA @ 3 V
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
On-Chip Rail-to-Rail Output Buffer Amplifier
Three Power-Down Functions
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit
buffered voltage-output DACs that operate from a single +2.5 V
to +5.5 V supply consuming 120
A at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/
s. It uses a 2-wire (I
2
C compatible) serial interface that
operates at clock rates up to 400 kHz. Multiple devices can
share the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on-reset circuit, which ensures that
the DAC output powers-up to zero volts and remains there until
a valid write takes place. The parts contain a power-down feature
which reduces the current consumption of the device to 50 nA
at 3 V and provides software-selectable output loads while in
power-down mode.
The low power consumption in normal operation make these
DACs ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V
reducing to 1
W in all power-down modes.
I
2
C is a registered trademark of Philips Corporation.
*Protected by U.S. Patent No. 5684481, other patent pending.
REV. 0
2
AD5301/AD5311/AD5321SPECIFICATIONS
(V
DD
= +2.5 V to +5.5 V; R
L
= 2 k to GND;
C
L
= 200 pF to GND; All specifications T
MIN
to T
MAX
unless otherwise noted.)
B Version
2
Parameter
1
Min
Typ
Max
Units
Conditions/Comments
DC PERFORMANCE
3, 4
AD5301
Resolution
8
Bits
Relative Accuracy
0.15
1
LSB
Differential Nonlinearity
0.02
0.25
LSB
Guaranteed Monotonic by Design Over All Codes
AD5311
Resolution
10
Bits
Relative Accuracy
0.5
4
LSB
Differential Nonlinearity
0.05
0.5
LSB
Guaranteed Monotonic by Design Over All Codes
AD5321
Resolution
12
Bits
Relative Accuracy
2
16
LSB
Differential Nonlinearity
0.3
0.8
LSB
Guaranteed Monotonic by Design Over All Codes
Zero Code Error
+5
+20
mV
All Zeros Loaded to DAC, See Figure 9
Full-Scale Error
0.15
1.25
% of FSR
All Ones Loaded to DAC, See Figure 9
Gain Error
0.15
1
% of FSR
Zero Code Error Drift
5
20
V/
C
Gain Error Drift
5
5
ppm of FSR/
C
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
0.001
V min
This is a measure of the minimum and maximum drive
Maximum Output Voltage
V
DD
0.001
V max
capability of the output amplifier.
DC Output Impedance
1
Short Circuit Current
50
mA
V
DD
= +5 V
20
mA
V
DD
= +3 V
Power-Up Time
2.5
s
Coming Out of Power-Down Mode. V
DD
= +5 V
6
s
Coming Out of Power-Down Mode. V
DD
= +3 V
LOGIC INPUTS (A0, A1,
PD)
5
Input Current
1
A
V
IL
, Input Low Voltage
0.8
V
V
DD
= +5 V
10%
0.6
V
V
DD
= +3 V
10%
0.5
V
V
DD
= +2.5 V
V
IH
, Input High Voltage
2.4
V
V
DD
= +5 V
10%
2.1
V
V
DD
= +3 V
10%
2.0
V
V
DD
= +2.5 V
Pin Capacitance
3
pF
LOGIC INPUTS (SCL, SDA)
5
V
IH
, Input High Voltage
0.7 V
DD
V
DD
+ 0.3
V
V
IL
, Input Low Voltage
0.3
0.3 V
DD
V
I
IN
, Input Leakage Current
1
A
V
IN
= 0 V to V
DD
V
HYST
, Input Hysteresis
0.05 V
DD
V
C
IN
, Input Capacitance
6
pF
Glitch Rejection
6
50
ns
Pulsewidth of Spike Suppressed
LOGIC OUTPUT (SDA)
5
V
OL
, Output Low Voltage
0.4
V
I
SINK
= 3 mA
0.6
V
I
SINK
= 6 mA
Three-State Leakage Current
1
A
Three-State Output Capacitance
6
pF
POWER REQUIREMENTS
V
DD
2.5
5.5
V
I
DD
Specification Is Valid for All DAC Codes
I
DD
(Normal Mode)
DAC Active and Excluding Load Current
V
DD
= +4.5 V to +5.5 V
150
250
A
V
IH
= V
DD
and V
IL
= GND
V
DD
= +2.5 V to +3.6 V
120
220
A
V
IH
= V
DD
and V
IL
= GND
I
DD
(Power-Down Mode)
V
DD
= +4.5 V to +5.5 V
0.2
1
A
V
IH
= V
DD
and V
IL
= GND
V
DD
= +2.5 V to +3.6 V
0.05
1
A
V
IH
= V
DD
and V
IL
= GND
NOTES
1
See Terminology.
2
Temperature ranges are as follows: B Version: 40
C to +105
C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000).
5
Guaranteed by Design and Characterization, not production tested.
6
Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.
Specifications subject to change without notice .
REV. 0
AD5301/AD5311/AD5321
3
AC CHARACTERISTICS
1
B Version
3
Parameter
2
Min
Typ
Max
Units
Conditions/Comments
Output Voltage Settling Time
V
DD
= +5 V
AD5301
6
8
s
1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5311
7
9
s
1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5321
8
10
s
1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)
Slew Rate
0.7
V/
s
Major-Code Change Glitch Impulse
12
nV-s
1 LSB Change Around Major Carry
Digital Feedthrough
0.3
nV-s
NOTES
1
See Terminology
2
Guaranteed by design and characterization, not production tested.
3
Temperature ranges are as follows: B Version: 40
C to +105
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1
Limit at T
MIN
, T
MAX
Parameter
2
(B Version)
Units
Conditions/Comments
f
SCL
400
kHz max
SCL Clock Frequency
t
1
2.5
s min
SCL Cycle Time
t
2
0.6
s min
t
HIGH
, SCL High Time
t
3
1.3
s min
t
LOW
, SCL Low Time
t
4
0.6
s min
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
5
100
ns min
t
SU,DAT
, Data Setup Time
t
6
3
0.9
s max
t
HD,DAT
, Data Hold Time
0
s min
t
7
0.6
s min
t
SU,STA
, Setup Time for Repeated Start
t
8
0.6
s min
t
SU,STO
, Stop Condition Setup Time
t
9
1.3
s min
t
BUF
, Bus Free Time Between a STOP Condition and a START Condition
t
10
300
ns max
t
R
, Rise Time of Both SCL and SDA when Receiving
0
ns min
May be CMOS Driven
t
11
250
ns max
t
F
, Fall Time of SDA when Receiving
300
ns max
t
F
, Fall Time of Both SCL and SDA when Transmitting
20 + 0.1C
b
4
ns min
C
b
400
pF max
Capacitive Load for Each Bus Line
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization, not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH MIN
of the SCL signal) in order to bridge the undefined region of
SCL's falling edge.
4
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Specifications subject to change without notice.
(V
DD
= +2.5 V to +5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; All specifications T
MIN
to T
MAX
unless
otherwise noted.)
(V
DD
= +2.5 V to +5.5 V. All specifications T
MIN
to T
MAX
unless otherwise noted.)
REV. 0
AD5301/AD5311/AD5321
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5301/AD5311/AD5321 features proprietary ESD protection circuitry, perma nent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= +25
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
PD, A1, A0 to GND . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . 40
C to +105
C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . . +150
C
SOT-23 Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max T
A
)/
JA
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6
C/W
ORDERING GUIDE
Temperature
Package
Package
Branding
Model
Range
Description
Option
Information
AD5301BRT
40
C to +105
C
SOT-23
RT-6
D8B
AD5301BRM
40
C to +105
C
SOIC
RM-8
D8B
AD5311BRT
40
C to +105
C
SOT-23
RT-6
D9B
AD5311BRM
40
C to +105
C
SOIC
RM-8
D9B
AD5321BRT
40
C to +105
C
SOT-23
RT-6
DAB
AD5321BRM
40
C to +105
C
SOIC
RM-8
DAB
SOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max T
A
)/
JA
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
t
9
t
4
t
6
t
5
t
7
t
8
t
1
t
2
t
4
t
11
t
10
t
3
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 1. 2-Wire Serial Interface Timing Diagram
REV. 0
AD5301/AD5311/AD5321
5
PIN CONFIGURATIONS
6-Lead SOT-23
8-Lead SOIC
(RT-6)
(RM-8)
TOP VIEW
(Not to Scale)
6
5
4
1
2
3
GND
SDA
SCL
V
DD
A0
V
OUT
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
A0
PD
V
OUT
GND
V
DD
SCL
SDA
A1
AD5301/AD5311/AD5321
AD5301/AD5311/AD5321
PIN FUNCTION DESCRIPTION
SOIC
SOT-23
Pin No.
Pin No.
Mnemonic
Function
1
6
V
DD
Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply
should be decoupled with a 10
F in parallel with a 0.1
F capacitor to GND.
2
5
A0
Address Input. Sets the Least Significant Bit of the 7-bit slave address.
3
N/A
A1
Address Input. Sets the 2nd Least Significant Bit of the 7-bit slave address.
4
4
V
OUT
Buffered analog output voltage from the DAC. The output amplifier has rail-to-rail operation.
5
N/A
PD
Active low control input that acts as a hardware power-down option. This pin overrides any
software power-down option. The DAC output goes three-state and the current consumption
of the part drops to 50 nA @ 3 V (200 nA @ 5 V).
6
3
SCL
Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit
input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I
2
C compat-
ible interface. SCL may be CMOS/TTL driven.
7
2
SDA
Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit
input shift register during the write cycle and used to read back one or two bytes of data
(one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is
a bidirectional open-drain data line that should be pulled to the supply with an external
pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven.
8
1
GND
Ground reference point for all circuitry on the part.
REV. 0
AD5301/AD5311/AD5321
6
TERMINOLOGY
RELATIVE ACCURACY
For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL vs. Code plots can be seen in Figures 2
to 4.
DIFFERENTIAL NONLINEARITY
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of
1 LSB
maximum ensures monotonicity. These DACs are guaranteed
monotonic by design over all codes. Typical DNL vs. Code
plots can be seen in Figures 5 to 7.
ZERO CODE ERROR
Zero Code Error is a measure of the output error when zero
code (00H) is loaded to the DAC register. Ideally, the output
should be 0 V. The Zero Code Error of the AD5301/AD5311/
AD5321 is always positive because the output of the DAC can-
not go below 0 V. It is due to a combination of the offset errors
in the DAC and output amplifier. It is expressed in mV, see
Figure 9.
FULL-SCALE ERROR
Full-Scale Error is a measure of the output error when full scale
is loaded to the DAC register. Ideally, the output should be V
DD
1 LSB. Full-scale error is expressed in percent of FSR (full-
scale range). A plot can be seen in Figure 9.
GAIN ERROR
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.
ZERO CODE ERROR DRIFT
This is a measure of the change in zero code error with a
change in temperature. It is expressed in
V/
C.
GAIN ERROR DRIFT
This is a measure of the change in gain error with changes in tem-
perature. It is expressed in (ppm of full-scale range)/
C.
MAJOR CODE TRANSITION GLITCH ENERGY
Major Code Transition Glitch Energy is the energy of the im-
pulse injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).
DIGITAL FEEDTHROUGH
Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-secs and is measured with a full-scale change
on the digital input pins, i.e., from all 0s to all 1s and vice versa.
REV. 0
AD5301/AD5311/AD5321
7
Typical Performance Characteristics
CODE
INL ERROR LSBs
1.0
0.5
1.0
0
50
250
100
150
200
0
0.5
T
A
= +25 C
V
DD
= +5V
Figure 2. AD5301 Typical INL Plot
CODE
DNL ERROR LSBs
0.3
0.3
0
50
250
100
150
200
0.1
0.2
0.2
0.1
0
T
A
= +25 C
V
DD
= +5V
Figure 5. AD5301 Typical DNL Plot
TEMPERATURE C
ERROR LSBs
1.00
0.75
1.00
40
0
120
40
80
0
0.25
0.50
0.75
0.50
0.25
V
DD
= +5V
MAX INL
MAX DNL
MIN DNL
MIN INL
Figure 8. AD5301 INL Error and
DNL Error vs. Temperature
CODE
INL ERROR LSBs
3
0
200
1000
400
600
800
0
1
2
3
2
1
T
A
= +25 C
V
DD
= +5V
Figure 3. AD5311 Typical INL Plot
CODE
DNL ERROR LSBs
0.6
0.4
0
200
1000
400
600
800
0.2
0.6
0.2
0
0.4
T
A
= +25 C
V
DD
= +5V
Figure 6. AD5311 Typical DNL Plot
TEMPERATURE C
ERROR
40
0
100
40
80
10
8
6
4
2
0
2
4
6
8
10
60
20
20
ZERO SCALE
FULL SCALE
V
DD
= +5V
Figure 9. Zero-Code Error and Full-
Scale Error vs. Temperature
CODE
INL ERROR LSBs
12
0
1000
4000
2000
3000
0
4
8
12
8
4
T
A
= +25 C
V
DD
= +5V
Figure 4. AD5321 Typical INL Plot
T
A
= +25 C
V
DD
= +5V
CODE
DNL ERROR LSBs
1.0
0.5
1.0
0
1000
4000
2000
3000
0
0.5
Figure 7. AD5321 Typical DNL Plot
I
DD
A
FREQUENCY
120
200
190
V
DD
= +5V
V
DD
= +3V
180
170
160
150
140
130
110
100
90
80
Figure 10. I
DD
Histogram with V
DD
=
+3 V and V
DD
= +5 V
REV. 0
AD5301/AD5311/AD5321
8
I mA
V
OUT
V
5
0
0
3
6
3
2
1
4
15
5V SOURCE
3V SOURCE
3V SINK
5V SINK
9
12
Figure 11. Source and Sink Current
Capability
V
DD
Volts
1.0
0
2.7
3.2
5.2
3.7
4.2
4.7
0.4
0.2
0.8
0.6
I
DD
A
40 C
+25 C
+105 C
Figure 14. Power-Down Current vs.
Supply Voltage
CH1 1V, CH2 1V, TIME BASE = 20 s/DIV
CH2
CH1
V
DD
V
OUT
T
A
= +25 C
Figure 17. Power-On Reset to 0 V
I
DD
A
200
ZERO-SCALE
FULL-SCALE
180
160
140
120
100
80
60
40
20
0
CODE
V
DD
= 5V
V
DD
= 3V
T
A
= +25 C
Figure 12. Supply Current vs. Code
V Volts
300
0
0
150
100
250
200
I
DD
A
1.0
2.0
3.0
4.0
5.0
50
T
A
= +25 C
V
DD
= +5V
V
DD
= +3V
INCREASING
DECREASING
Figure 15. Supply Current vs. Logic
Input Voltage for SDA and SCL Volt-
age Increasing and Decreasing
CH1 1V, CH2 5V, TIME BASE = 1 s/DIV
CH2
CH1
V
OUT
SCL
T
A
= +25 C
V
DD
= +5V
Figure 18. Exiting Power-Down to
Midscale
V
DD
Volts
I
DD
A
200
0
2.7
3.2
3.7
4.2
100
50
4.7
5.2
150
40 C
+25 C
+105 C
Figure 13. Supply Current vs. Supply
Voltage
CH1 1V, TIME BASE = 5 s/DIV
CH1
V
OUT
V
DD
= +5V
T
A
= +25 C
LOAD = 2k AND
200pF TO GND
Figure 16. Half-Scale Settling (1/4 to
3/4 Scale Code Charge)
2.48
2.49
V
OUT
Volts
2.47
2.50
Figure 19. Major-Code Transition
REV. 0
AD5301/AD5311/AD5321
9
1ns/DIV
V Volts
2.440
2.455
2.445
2.450
Figure 20. Digital Feedthrough
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321 are single resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10 and 12
bits respectively. Data is written via a 2-wire serial interface.
They operate from single supplies of +2.5 V to +5.5 V and the
output buffer amplifiers provide rail-to-rail output swing with a
slew rate of 0.7 V/
s. The power-supply (V
DD
) acts as the refer-
ence to the DAC. The devices have three programmable power-
down modes, in which the DAC may be turned off completely
with a high-impedance output, or the output may be pulled low
by an on-chip resistor. See Power-Down section.
DIGITAL-TO-ANALOG SECTION
The architecture of the DAC channel consists of a resistor-
string DAC followed by an output buffer amplifier. The voltage
at the V
DD
pin provides the reference voltage for the DAC.
Figure 21 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
V
V
D
OUT
DD
N
=
2
where:
N = DAC resolution
D = decimal equivalent of the binary code which is loaded to the
DAC register:
0255 for AD5301 (8 Bits)
01023 for AD5311 (10 Bits)
04095 for AD5321 (12 Bits)
RESISTOR
STRING
OUTPUT BUFFER
AMPLIFIER
DAC
REGISTER
REF(+)
V
OUT
V
DD
REF()
Figure 21. DAC Channel Architecture
RESISTOR STRING
The resistor string section is shown in Figure 22. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic over all codes.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
Figure 22. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV from either rail, which gives an output
range of 0.001 V to V
DD
0.001 V. It is capable of driving a
load of 2 k
to GND and V
DD
, in parallel with 500 pF to GND.
The source and sink capabilities of the output amplifier can be
seen in Figure 11.
The slew rate is 0.7 V/
s with a half-scale settling time to
0.5 LSB (at 8 bits) of 6
s with the output unloaded.
POWER-ON RESET
The AD5301/AD5311/AD5321 are provided with a power-on
reset function, ensuring that they power up in a defined state.
The DAC register is filled with zeros and remains so until a
valid write sequence is made to the device. This is particularly
useful in applications where it is important to know the state of
the DAC output while the device is powering up.
REV. 0
AD5301/AD5311/AD5321
10
X
X
PD1
PD0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
DB0 (LSB)
DB15 (MSB)
DATA BITS
Figure 23a. AD5301 Input Shift Register Contents
X
X
PD1
PD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DB0 (LSB)
DB15 (MSB)
DATA BITS
Figure 23b. AD5311 Input Shift Register Contents
X
X
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB0 (LSB)
DB15 (MSB)
DATA BITS
Figure 23c. AD5321 Input Shift Register Contents
SERIAL INTERFACE
2-WIRE SERIAL BUS
The AD5301/AD5311/AD5321 are controlled via an I
2
C-
compatible serial bus. The DACs are connected to this bus as
slave devices (no clock is generated by the AD5301/AD5311/
AD5321 DACs).
The AD5301/AD5311/AD5321 has a 7-bit slave address. In the
case of the 6-pin device, the 6 MSBs are 000110 and the LSB is
determined by the state of the A0 pin. In the case of the 8-pin
device, the 5 MSBs are 00011 and the 2 LSBs are determined
by the state of the A0 and A1 pins. A1 and A0 allow the user to
use up to four of these DACs on one bus.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high to low transition on the SDA
line occurs while SCL is high. The following byte is the ad-
dress byte which consists of the 7-bit slave address followed
by an R/
W bit (this bit determines whether data will be read
from or written to the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/
W bit is high, the master will read
from the slave device. However, if the R/
W bit is low, the
master will write to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an Acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL.
3. When all data bits have been read or written, a STOP condi-
tion is established by the master. A STOP condition is de-
fined as a low-to-high transition on the SDA line while SCL
is high. In Write mode, the master will pull the SDA line
high during the 10th clock pulse to establish a STOP condi-
tion. In Read mode, the master will issue a No Acknowledge
for the 9th clock pulse (i.e., the SDA line remains high). The
master will then bring the SDA line low before the 10th clock
pulse and then high during the 10th clock pulse to establish a
STOP condition.
In the case of the AD5301/AD5311/AD5321, a write operation
contains two bytes whereas a read operation may contain one or
two bytes. See Figures 24 to 29 below for a graphical explana-
tion of the serial interface.
A repeated write function gives the user flexibility to update the
DAC output a number of times after addressing the part only
once. During the write cycle, each multiple of two data bytes
will update the DAC output. For example, after the DAC has
acknowledged its address byte, and receives two data bytes, the
DAC output will update after the two data bytes, if another two
data bytes are written to the DAC while it is still the addressed
slave device, these data bytes will also cause an output update.
Repeat read of the DAC is also allowed.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide. Figure 23 illustrates the
contents of the input shift register for each part. Data is loaded
into the device as a 16-bit word under the control of a serial
clock input, SCL. The timing diagram for this operation is
shown in Figure 1. The 16-bit word consists of four control bits
followed by 8, 10 or 12 bits of data, depending on the device
type. MSB (Bit 15) is loaded first. The first two bits are "don't
cares." The next two are control bits that control the mode of
operation of the device (normal mode or any one of three
power-down modes). See Power Down Modes section for a
complete description. The remaining bits are left-justified DAC
data bits, starting with the MSB and ending with the LSB.
REV. 0
AD5301/AD5311/AD5321
11
SCL
SDA
SCL
SDA
D3
D2
D1
D0
X
X
X
X
X
X
PD1
PD0
D7
D6
D5
D4
0
0
0
1
1
A1*
A0
R/
W
ACK
BY
AD5301
STOP
COND
BY
MASTER
LEAST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5301
START
COND
BY
MASTER
ADDRESS BYTE
MOST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5301
*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.
Figure 24. AD5301 Write Sequence
SCL
SDA
SCL
SDA
D5
D4
D3
D2
D1
D0
X
X
X
X
PD1
PD0
D9
D8
D7
D6
0
0
0
1
1
A1*
A0
R/
W
ACK
BY
AD5311
STOP
COND
BY
MASTER
LEAST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5311
START
COND
BY
MASTER
ADDRESS
BYTE
MOST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5311
*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.
Figure 25. AD5311 Write Sequence
SCL
SDA
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
X
X
PD1
PD0
D11
D10
D9
D8
0
0
0
1
1
A1*
A0
R/
W
ACK
BY
AD5321
STOP
COND
BY
MASTER
LEAST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5321
START
COND
BY
MASTER
ADDRESS BYTE
MOST SIGNIFICANT CONTROL BYTE
ACK
BY
AD5321
*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.
Figure 26. AD5321 Write Sequence
WRITE OPERATION
When writing to the AD5301/AD5311/AD5321 DACs, the user
must begin with an address byte, after which the DAC will
acknowledge that it is prepared to receive data by pulling SDA
low. This address byte is followed by the 16-bit word in the
form of two control bytes. The write operations for the three
DACs are shown in the figures below.
REV. 0
AD5301/AD5311/AD5321
12
READ OPERATION
When reading data back from the AD5301/AD5311/AD5321
DACs, the user must begin with an address byte after which the
DAC will acknowledge that it is prepared to transmit data by
pulling SDA low. There are two different read operations. In the
case of the AD5301, the readback is a single byte that consists
SCL
SDA
0
0
0
1
1
A1*
A0
R/
W
*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.
ACK
BY
AD5301
START
COND
BY
MASTER
ADDRESS BYTE
D7
D6
D5
D4
D3
D2
D1
D0
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
DATA BYTE
Figure 27. AD5301 Readback Sequence
SCL
SDA
SCL
SDA
D5
D4
D3
D2
D1
D0
X
X
X
X
PD1
PD0
D9
D8
D7
D6
0
0
0
1
1
A1*
A0
R/
W
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
LEAST SIGNIFICANT BYTE
ACK
BY
AD5311
START
COND
BY
MASTER
ADDRESS BYTE
MOST SIGNIFICANT BYTE
ACK
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.
Figure 28. AD5311 Readback Sequence
SCL
SDA
SCL
SDA
D7
D6
D5
D4
D3
D2
D1
D0
X
X
PD1
PD0
D11
D10
D9
D8
0
0
0
1
1
A1*
A0
R/
W
NO ACK
BY
MASTER
STOP
COND
BY
MASTER
LEAST SIGNIFICANT BYTE
ACK
BY
AD5321
START
COND
BY
MASTER
ADDRESS BYTE
MOST SIGNIFICANT BYTE
ACK
BY
MASTER
*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.
Figure 29. AD5321 Readback Sequence
of the eight data bits in the DAC register. However, in the
case of the AD5311 and AD5321, the readback consists of two
bytes that contain both the data and the power-down mode bits.
The read operations for the three DACs are shown in the figures
below.
REV. 0
AD5301/AD5311/AD5321
13
POWER-DOWN MODES
The AD5301/AD5311/AD5321 have very low power consump-
tion, dissipating typically 0.36 mW with a 3 V supply and
0.75 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into one of
three power-down modes, which are selected by Bits 13 and 12
(PD1 and PD0) of the control word. Table I shows how the state
of the bits corresponds to the mode of operation of the DAC.
Table I. PD1/PD0 Operating Modes
PD1
PD0
Operating Mode
0
0
Normal Operation
0
1
Power-Down (1 k
Load to GND)
1
0
Power-Down (100 k
Load to GND)
1
1
Power-Down (Three-State Output)
The software power-down modes programmed by PD0 and
PD1 may be overridden by the
PD pin on the 8-pin version.
Taking this pin low puts the DAC into three-state power-down
mode. If
PD is not used it should be tied high.
When both bits are set to 0, the DAC works normally with its
normal power consumption of 150
A at 5 V, while for the three
power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current drop, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode and provides a defined input
condition for whatever is connected to the output of the DAC
amplifier. There are three different options. The output is con-
nected internally to GND through a 1 k
resistor, a 100 k
resistor or it is left open-circuited (Three-State). Resistor toler-
ance =
20%. The output stage is illustrated in Figure 30.
AMPLIFIER
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
RESISTOR-
STRING DAC
V
OUT
Figure 30. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unchanged when in power-Down. The time to
exit power-down is typically 2.5
s for V
DD
= 5 V and 6
s when
V
DD
= 3 V. See Figure 18 for a plot.
APPLICATIONS
USING REF19x AS A POWER SUPPLY
Because the supply current required by the AD5301/AD5311/
AD5321 is extremely low, the user has an alternative option
to use a REF19x voltage reference (REF195 for +5 V or REF193
for +3 V) to supply the required voltage to the part, see Fig-
ure 31.
AD5301/
AD5311/
AD5321
2-WIRE
SERIAL
INTERFACE
SDA
SCL
+15V
+5V
150 A TYP
V
OUT
= 0V TO 5V
REF195
V
DD
Figure 31. REF195 as Power Supply to AD5301/AD5311/
AD5321
This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than +5 V or
+3 V (e.g., +15 V). The REF19x will output a steady supply
voltage for the AD5301/AD5311/AD5321. If the low dropout
REF195 is used, the current it needs to supply to the AD5301/
AD5311/AD5321 is 150
A. This is with no load on the output
of the DAC. When the DAC output is loaded, the REF195 also
needs to supply the current to the load.
The total current required (with a 2 k
load on the DAC
output and full scale loaded to the DAC) is:
150
A + (5 V/2 k
) = 2.65 mA
The load regulation of the REF195 is typically 2 ppm/mA which
results in an error of 5.3 ppm (26.5
V) for the 2.65 mA current
drawn from it. This corresponds to a 0.00136 LSB error.
BIPOLAR OPERATION USING THE AD5301/AD5311/
AD5321
The AD5301/AD5311/AD5321 has been designed for single-
supply operation but a bipolar output range is also possible
using the circuit in Figure 32. The circuit below will give an
output voltage range of
5 V. Rail-to-rail operation at the am-
plifier output is achievable using an AD820 or an OP295 as the
output amplifier.
+5V
5V
AD820/
OP295
2-WIRE
SERIAL
INTERFACE
+5V
AD5301/
AD5311/
AD5321
10 F
0.1 F
V
DD
V
OUT
R1 = 10k
5V
R2 = 10k
Figure 32. Bipolar Operation with the AD5301/AD5311/
AD5321
REV. 0
AD5301/AD5311/AD5321
14
AD5301
A1
A0
SDA
SCL
V
OUT
AD5301
A1
A0
SDA
SCL
V
OUT
AD5301
A1
A0
SDA
SCL
V
OUT
AD5301
A1
A0
SDA
SCL
V
OUT
SCL
SDA
+5V
V
DD
V
DD
V
DD
MASTER
R
P
R
P
Figure 33. Multiple AD5301 Devices on One Bus
The output voltage for any input code can be calculated as
follows:
V
OUT
= [(V
DD
(D/2
N
)
(R1 + R2)/R1) V
DD
(R2/R1)]
where D is the decimal equivalent of the code loaded to the
DAC.
N is the DAC resolution.
With V
DD
= 5 V, R1 = R2 = 10 k
:
V
OUT
= (10
D/2
N
) 5 V
MULTIPLE DEVICES ON ONE BUS
Figure 33 shows four AD5301 devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each DAC to be written to or
read from independently. The master device output bus line
drivers are open-drain pull downs in a fully I
2
C-compatible
interface.
CMOS DRIVEN SCL AND SDA LINES
For single or multisupply systems where the minimum SCL
swing requirements allow it, a CMOS SCL driver may be used,
the SCL pull-up resistor can be removed, making the SCL bus
line fully CMOS compatible. This will reduce power consump-
tion in both the SCL driver and receiver devices. The SDA line
remains open-drain, I
2
C-compatible.
Further changes, in the SDA line driver, may be made to make
the system more CMOS-compatible and save more power. As
the SDA line is bidirectional, it cannot be made fully CMOS-
compatible. A switched pull-up resistor can be combined with
a CMOS device with an open-circuit (three-state) input such
that the CMOS SDA driver is enabled during write cycles and
I
2
C mode is enabled during shared cycles, i.e., readback, ac-
knowledge bit cycles, start and stop conditions.
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The AD5301/AD5311/AD5321
should be decoupled to GND with a 10
F in parallel with 0.1
F
capacitor, located as close to the package as possible. The 10
F
capacitor should be the tantalum bead type, while a ceramic
0.1
F capacitor will provide sufficient low impedance path to
ground at high frequencies. The power supply lines of the
AD5301/AD5311/AD5321 should use as large a trace as pos-
sible to provide low impedance paths. A ground line routed
between the SDA and SCL lines will help reduce crosstalk
between them (not required on a multilayer board as there will
be a ground plane layer, but separating the lines will help).
REV. 0
15
6-Lead SOT-23
(RT-6)
0.122 (3.10)
0.106 (2.70)
PIN 1
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
0.075 (1.90)
BSC
0.037 (0.95) BSC
1
3
4
5
6
2
0.009 (0.23)
0.003 (0.08)
0.022 (0.55)
0.014 (0.35)
10
0
0.020 (0.50)
0.010 (0.25)
0.006 (0.15)
0.000 (0.00)
0.051 (1.30)
0.035 (0.90)
SEATING
PLANE
0.057 (1.45)
0.035 (0.90)
8-Lead SOIC
(RM-8)
0.009 (0.23)
0.005 (0.13)
0.028 (0.70)
0.016 (0.40)
6
0
0.037 (0.95)
0.030 (0.75)
8
5
4
1
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
0.193
(4.90)
BSC
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.016 (0.40)
0.010 (0.25)
0.043
(1.10)
MAX
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD5301/AD5311/AD5321
C353187/99
PRINTED IN U.S.A.
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