a
Two's Complement
Dual, 12-Bit DACs
Preliminary Technical Data
AD5329
REV PrC, 20 DEC 99
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Analog
Devices.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106 U
.
S
.
A
.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax:617/326-8703
Analog Devices, Inc., 1998
FEATURES
Monotonic DNL < 1 LSB
Improved Accuracy at Zero Scale
Fast 2
s Settling Time
Power ON Reset
3-Wire Serial Data Input
25MHz Data Load Rate
Internal Reference Voltage
+4.5V to +5.5V Single Supply Operation
APPLICATIONS
Digital Control of Gain & Offset
GENERAL DESCRIPTION
The AD5329 is a serial-input, dual 12-bit digital-to-analog converter
that accepts two's complement digital coding. An internal voltage
reference generates a stable 2V DACREF. The buffered DACREF
output generates the system bipolar ground reference at pin V
BZ
. The
bipolar DAC output swing programs over a 4V
PP
range. The device is
specified for operation from +5 volts 10%.
Data is loaded MSB first on the positive clock edge (SCLK) when the
frame synch (FSYNC) input is active low. The serial clock input word
is 16-bits with the MSB position containing an address bit. The last 12
data bits clocked into the register will be transferred to the internal
DAC register when the strobe input is returned to logic high.
The output transfer equation is:
V
OUT
= [(D-2048) / 4096 * V
DACREF
] + V
BZ
Where D is the 12-bit decimal data, and V
OUT
, V
DACREF
, V
BZ
are with
respect to ground.
The AD5329 is available in the compact 1.1mm thin
SOIC-10
package. All parts are guaranteed to operate over the industrial
temperature range of 0C to +70C.
PIN CONFIGURATION
10 GND
9 SCLK
8 FSYNC
7 NC
6 V
BZ
V
DD
1
SDA 2
NC 3
V
OUTB
4
V
OUTA
5
ORDERING GUIDE
RES
Temp
Package
Package
Model
(bits)
Range
Description Option
AD5329KRM-REEL7
12
0/+70C
SOIC-10
RM-10
FUNCTIONAL BLOCK DIAGRAM
FSYNC
V
OUTA
DAC A
REGISTER
16-Bit
SERIAL INPUT REGISTER
D11 ...............D0
Power On
Reset
SCLK
SDI
GND
12
12
EN
V
BZ
(V
REF
)
V
BZ
+ 2V
V
BZ
- 2V
DECODER SW
DRIVER A
V
DD
+
V
D A C R E F
-
DAC B
REGISTER
V
OUTB
V
BZ
+ 2V
V
BZ
- 2V
DECODER SW
DRIVER B
12
X2
X2
ADDR
DECODE
A0
AD5329
+2V
AD5329 -- SPECIFICATIONS
REV PrC 20 DEC 99
2
Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present
form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com
ELECTRICAL CHARACTERISTICS
(V
DD
= +5V10%, 0C < T
A
< +70C unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
DC CHARACTERISTICS
Resolution
N
12
Bits
Differential Nonlinearity Error
DNL
1
0.5
+1
LSB
Integral Nonlinearity Error
INL
0.05
0.02
+0.05
%FS
Integral Nonlinearity Error
INL
Within 256 codes of V
BZ
0.02
0.01
+0.02
%FS
Full-Scale Temperature Coefficient
2
V
FS
/
T
Code = 7FF
H
100
ppm/C
Positive-Full-Scale Error
V
+FSE
Code = 7FF
H
0.1
-0.05
+0.1
%FS
Bipolar-Zero-Scale Error
V
BZSE
Code = 000
H
0.1
+0.1
+0.1
V
Negative-Full-Scale Error
V
-FSE
Code = 800
H
0.1
-0.05
+0.1
%FS
ANALOG OUTPUTS
Nominal Positive Full-Scale
V
OUTA/B
Code = 7FF
H
4
Volts
Positive Full-Scale Tempco
2
TCV
OUTA/B
Code = 7FF
H
100
ppm/C
Nominal V
BZ
Output Voltage
V
BZ
2
Volts
Bipolar-Zero Output Resistance
2
R
BZ
1
Ohm
Nominal Peak-Peak Output Swing
|V
+FS
| + |V
-FS
| Code 7FF
H
to Code 800
H
4
Volts
DIGITAL INPUTS
Input Logic High
V
IH
V
DD
= +5V
2.4
V
Input Logic Low
V
IL
V
DD
= +5V
0.8
V
Input Current
I
IL
V
IN
= 0V or +5V, V
DD
= +5V
1
A
Input Capacitance
2
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD Range
4.5
5.5
V
Supply Current
I
DD
V
IH
= V
DD
or V
IL
= 0V
2.5
mA
Supply Current in Shutdown
I
DD_SHDN
V
IH
= V
DD
or V
IL
= 0V, B14=0
40
A
Power Dissipation
3
P
DISS
V
IH
= V
DD
or V
IL
= 0V, V
DD
= +5.5V
12.5
mW
Power Supply Sensitivity
PSS
V
DD
= +5V 10%
0.0002
0.01
%/%
DYNAMIC CHARACTERISTICS
2
Settling Time
t
S
For a 16 LSB step change
2
3
s
INTERFACE TIMING CHARACTERISTICS
2,4
SCLK Clock Cycle time
t
1
35
ns
Input Clock Pulse Width
t
2
, t
3
Clock level low or high
20
ns
Data Setup Time
t
4
5
ns
Data Hold Time
t
5
5
ns
FSYNC to SCLK active edge Setup Time
t
6
10
ns
SCLK to FSYNC Hold Time
t
7
0
ns
Minimum FSYNC High Time
t
8
35
ns
NOTES:
1.
Typicals represent average readings at +25C and V
DD
= +5V.
2.
Guaranteed by design and not subject to production test.
3.
PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
4.
See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are
measured using V
DD
= +5V. Input logic should have a 1V/
sec minimum slew rate.
Two's Complement, Dual 12-Bit DAC
AD5329
REV PrC 20 DEC 99
3
Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present
form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com
ABSOLUTE MAXIMUM RATINGS (T
A
= +25C, unless
otherwise noted)
V
DD
to GND ........................................................... -0.3,+6V
V
OUTA
, V
OUTB
, V
BZ
to GND....................................... 0V, V
DD
Digital Input Voltages to GND ....................... 0V, V
DD
+0.3V
Operating Temperature Range.......................... 0C to +70C
Maximum Junction Temperature (T
J MAX
)................. +150C
Storage Temperature ................................... -65C to +150C
Lead Temperature (Soldering, 10 sec) ....................... +300C
Package Power Dissipation....................... (T
JMAX
- T
A
) /
JA
Thermal Resistance
JA,
SOIC
-10 .....................................................206C/W
AD5329 Two's Complement Coding
Binary
Hexadecimal
Scale
0111 1111 1111
7 F F
+FS
0111 1111 1110
7 F F
+FS-1LSB
0000 0000 0001
0 0 1
BZS+1LSB
0000 0000 0000
0 0 0
BZS
1111 1111 1111
F F F
BZS-1LSB
1000 0000 0001
8 0 1
-FS+1LSB
1000 0000 0000
8 0 0
-FS
TABLE 2: AD5329 PIN Descriptions
Pin
Name
Description
1
V
DD
Positive power supply, specified for operation
at +5V.
2
SDA
Serial Data Input, MSB first format
3
NC
No Connect
4
V
OUTB
DAC B Voltage Output (A0 = logic "1")
5
V
OUTA
DAC A Voltage Output (A0 = logic "0")
6
V
BZ
Virtual Bipolar Zero (Active Output)
7
NC
No Connect
8
FSYNC
Frame Sync Input, Active Low. When
FSYNC
returns HIGH data in the serial input register
is transferred into the DAC register.
9
SCLK
Serial Clock Input, positive edge triggered
10
GND
Ground
TABLE 1: AD5329 Serial-Data Word Format
ADDR
DATA
B16 B15 B14 B13 B12 B11
<>
B4
B3
B2
B1
A0
X
SD
0
D11 D10
<>
D3
D2
D1
D0
MSB
LSB
SD: Shutdown is active high B14="1". Both DACs and the DACREF
becomes open circuit.
SDI
AD5329
1
0
1
SCLK
0
1
FSYNC
0
A0
X
SD
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 1A. Timing Diagram
Two's Complement, Dual 12-Bit DAC
AD5329
REV PrC 20 DEC 99
4
Information contained in this Preliminary Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present
form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 562-7254; FAX 408 562-7154; email; walt.heinzer@analog.com
FSYNC
t
3
t
2
t
4
t
5
t
7
t
6
t
8
1
SDI
0
1
SCLK
0
1
0
Dx
Dx
t
S
1LSB
ERROR
BAND
1
V
OUT
0
t
1
Dx
Dx
Figure 1B. Detail Timing Diagram
OPERATION
The AD5329 provides a 12-bit, 2's complement, dual, voltage-output
digital-to-analog converter. The first data bit of the 16-bit serial
register is decoded to determine which DAC register (DAC A:
A0= "0", DAC B: A0= "1") will be loaded with the final 12-bits of
data.
TABLE 3: Input Logic Control Truth Table
SCLK
FSYNC
Register Activity
L
H
No Shift Register Effect
P
L
Shift One bit in from the SDA pin.
L
P
Transfer SR data into DAC Register
X
L
No Operation
NOTE: P = positive edge, X = don't care, SR = Shift Register
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 12 bits of the
data word entered into the serial register are held when
FSYNC returns
high.
The internal power ON reset circuit clears the serial input registers to
all zeros, and sets the two DAC registers to V
BZ
(zero code).
All digital inputs are ESD protected with a series input resistor and
parallel Zener as shown in figure 7. Applies to digital input pins
SCLK, SDA,
FSYNC
LOGIC
1K
Figure 7. Equivalent ESD Protection Circuit
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)
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