AD5362/AD5363 8-Channel, 16/14-Bit, Serial Input, Voltage-Output DAC Preliminary data Sheet (Rev. PrC)
8-Channel, 16/14-Bit,
Serial Input, Voltage-Output DAC
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2005 Analog Devices, Inc. All rights reserved.
FEATURES
8-channel DAC in 52-LQFP and 56-LFCSP
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of -10 V to +10 V
Multiple output spans available
Temperature Monitoring Function
Channel Monitoring Multiplexer
GPIO Function
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Data error checking feature
SPI compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Instrumentation
Industrial Control System
PLC Analog I/O Cards
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Precision Medical Instruments
FUNCTIONAL BLOCK DIAGRAM
CONTROL
REGISTER
STATE
MACHINE
n
POWER-ON
RESET
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
AD5362/
AD5363
SERIAL
INTERFACE
8
BIN/2SCOMP
DAC 0
REGISTER
n
n
4
4
TO
MUX 2's
A/B SELECT
REGISTER
MUX
2
X2A REGISTER
X2B REGISTER
OFS1
REGISTER
14
14
DAC 0
OFFSET
DAC 1
BUFFER
DAC 3
REGISTER
n
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 3
GROUP 1
LDAC
DV
CC
V
DD
V
SS
AGND DNGD
DAC 0
REGISTER
n
n
4
4
TO
MUX 2's
A/B SELECT
REGISTER
MUX
2
X2A REGISTER
X2B REGISTER
OFS0
REGISTER
14
14
DAC 0
OFFSET
DAC 0
BUFFER
GROUP 0
DAC 3
REGISTER
n
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 3
BUFFER
AD5362, n = 16
AD5363, n = 14
GPIO
REGISTER
TEMP
SENSOR
TEMP_OUT
PEC
MON_IN0
MON_IN1
GPIO
MON_OUT
VOUT0 -
VOUT7
MUX
6
2
VOUT4
VOUT5
VOUT6
VOUT7
SIGGND1
VREF0
SIGGND0
VOUT0
VOUT1
VOUT2
VOUT3
VREF1
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
5362-0001B
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
Figure 1.
AD5362/AD5363--Protected by U.S. Patent No. 5,969,657; other patents pending
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 2 of 23
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 5
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Terminology .................................................................................... 11
Functional Description .................................................................. 12
DAC Architecture--General..................................................... 12
Channel Groups.......................................................................... 12
A/ B Registers And Gain/Offset Adjustment.......................... 13
Offset DACs ................................................................................ 13
Output Amplifier........................................................................ 13
Transfer Function ....................................................................... 14
Reference Selection .................................................................... 14
Calibration................................................................................... 15
Reset Function ............................................................................ 15
Clear Function ............................................................................ 15
BUSY
And
LDAC
Functions .................................................... 15
BIN
/2s Comp Pin ....................................................................... 16
Temperature Sensor ................................................................... 16
Monitor Function....................................................................... 16
GPIO Pin ..................................................................................... 16
Power-Down Mode .................................................................... 16
Temperature Monitoring........................................................... 16
Toggle Mode................................................................................ 16
Serial Interface ................................................................................ 18
SPI Write Mode .......................................................................... 18
Register Update Rates ................................................................ 18
SPI Readback Mode ................................................................... 19
Channel Addressing And Special Modes................................ 19
Special Function Mode.............................................................. 20
Power Supply Decoupling ......................................................... 21
Power Supply Sequencing ......................................................... 22
Interfacing Examples ................................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
Rev Pr B1
Added Reference Selection and Calibration Text
Rev Pr B2
Modified SPI Timing Diagrams
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 3 of 23
GENERAL DESCRIPTION
The AD5362/AD5363 contains 8, 16/14-bit DACs in a single,
56-lead, LFCSP or 52-lead LQFP package. It provides buffered
voltage outputs with a span 4 times the reference voltage. The
gain and offset of each DAC can be independently trimmed to
remove errors. For even greater flexibility, the device is divided
into two blocks of 8 DACs, and the output range of each block
can be independently adjusted by an offset DAC.
The AD5362/AD5363 offers guaranteed operation over a wide
supply range with V
SS
from -4.5 V to -16.5 V and V
DD
from
+8 V to +16.5 V. The output amplifier headroom requirement is
1.4 V operating with a load current of 1 mA.
The AD5362/AD5363 has a high-speed serial interface, which is
compatible with SPI, QSPITM, MICROWIRETM, and DSP
interface standards and can handle clock speeds of up to 50
MHz. All the outputs can be updated simultaneously by taking
the LDAC input low. Each channel has a programmable gain
and an offset adjust register.
Each DAC output is amplified and buffered on-chip with
respect to an external SIGGND input. The DAC outputs can
also be switched to SIGGND via the CLR pin
Table 1. High Channel Count Bipolar DACs
Model Resoluti
on
Nominal Output Span
Output
Channels
Linearity Error
(LSB)
Package Description
Package Option
AD5360BCPZ
16 Bits
4
V
REF
(20 V)
16
4
56-Lead LFCSP
CP-56
AD5360BSTZ
16 Bits
4
V
REF
(20 V)
16
4
52-Lead LQFP
ST-52
AD5361BCPZ
14 Bits
4
V
REF
(20 V)
16
1
56-Lead LFCSP
CP-56
AD5361BSTZ
14 Bits
4
V
REF
(20 V)
16
1
52-Lead LQFP
ST-52
AD5362BCPZ 16
Bits 4
V
REF
(20 V)
8
4
56-Lead LFCSP
CP-56
AD5362BSTZ 16
Bits 4
V
REF
(20 V)
8
4
52-Lead LQFP
ST-52
AD5363BCPZ
14 Bits
4
V
REF
(20 V)
8
1
56-Lead LFCSP
CP-56
AD5363BSTZ
14 Bits
4
V
REF
(20 V)
8
1
52-Lead LQFP
ST-52
AD5370BCPZ
16 Bits
4
V
REF
(12 V)
40
4
64-Lead LFCSP
CP-64
AD5370BSTZ
16 Bits
4
V
REF
(12 V)
40
4
64-Lead LQFP
ST-64
AD5371BCPZ
14 Bits
4
V
REF
(12 V)
40
1
100-Ball CSPBGA
BC-100-2
AD5371BSTZ
14 Bits
4
V
REF
(12 V)
40
1
80-Lead LQFP
ST-80
AD5372BCPZ
16 Bits
4
V
REF
(12 V)
32
4
56-Lead LFCSP
CP-56
AD5372BSTZ
16 Bits
4
V
REF
(12 V)
32
4
64-Lead LQFP
ST-64
AD5373BCPZ
14 Bits
4
V
REF
(12 V)
32
1
56-Lead LFCSP
CP-56
AD5373BSTZ
14 Bits
4
V
REF
(12 V)
32
1
64-Lead LQFP
ST-64
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 4 of 23
SPECIFICATIONS
DV
CC
= 2.3 V to 5.5 V; V
DD
= 8 V to 16.5 V; V
SS
= -4.5 V to -16.5 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; R
L
= Open Circuit;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. Performance Specifications
Parameter B
Version
1
Unit
Test
Conditions/Comments
2
ACCURACY
16 Bits
AD5362
Resolution
14 Bits
AD5363
Relative Accuracy
4
1
LSB max
LSB max
AD5362
AD5363
Differential Nonlinearity
1
LSB max
Guaranteed monotonic by design over temperature.
Offset Error
20
mV max
Prior to calibration
Gain Error
20
mV max
Prior to calibration
Offset Error
2
100
V max
After to calibration
Gain Error
2
100
V max
After to calibration
VOUT Temperature Coefficient
5
ppm FSR/C
typ
Includes linearity, offset, and gain drift.
DC Crosstalk
2
0.5
mV max
Typically 100 V.
REFERENCE INPUTS (VREF1, VREF2)
2
V
REF
DC Input Impedance
1
M min
Typically 100 M.
V
REF
Input Current
10
A max
Per input. Typically 30 nA.
V
REF
Range
3/5
V min/max
2% for specified operation.
SIGGND INPUT (SIGGND0 TO SIGGND4)
2
DC Input Impedance
55
k min
Typically 60 k.
Input Range
0.5
V min/max
OUTPUT CHARACTERISTICS
2
Output Voltage Range
V
SS
+ 2
V min
I
LOAD
= 1 mA.
V
DD
- 2
V max
I
LOAD
= 1 mA.
Short Circuit Current
5
mA max
Load Current
1
mA max
Capacitive Load
2200
pF max
DC Output Impedance
1
max
MONITOR PIN (MON_OUT)
Output Impedance
500
typ
Three State Leakage Current
100
nA typ
Continuous Current Limit
2
mA max
DIGITAL INPUTS
JEDEC compliant.
Input High Voltage
1.7
V min
IOV
CC
= 2.5 V to 3.6 V.
2.0
V
min
IOV
CC
= 3.6 V to 5.5 V.
Input Low Voltage
0.8
V max
IOV
CC
= 2.5 V to 5.5 V.
Input Current (with pull-up/pull-
down)
8
A max
CLR and RESET pin only.
Input Current (no pull-up/pull-down)
1
A max
All other digital input pins.
Input Capacitance
2
10
pF
max
DIGITAL OUTPUTS (SDO)
Output Low Voltage
0.5
V max
Sinking 200 A.
Output High Voltage (SDO)
DV
CC
- 0.5
V min
Sourcing 200 A.
High Impedance Leakage Current
-5
A max
SDO only.
High Impedance Output Capacitance
2
10
pF
typ
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 5 of 23
Parameter B
Version
1
Unit
Test
Conditions/Comments
2
POWER REQUIREMENTS
DV
CC
2.3/5.5
V
min/max
V
DD
8/16.5
V
min/max
V
SS
-4.5/-16.5
V
min/max
Power Supply Sensitivity
2
Full Scale/ V
DD
-75
dB
typ
Full Scale/ V
SS
-75
dB
typ
Full Scale/ V
CC
-90
dB
typ
DI
CC
2
mA
max
V
CC
= 5.5 V, V
IH
= V
CC
, V
IL
= GND.
I
DD
5
mA max
Outputs unloaded.
I
SS
5
mA max
Outputs unloaded.
Power Dissipation
Power Dissipation Unloaded (P)
350
mW
Junction Temperature
3
130
C
max
T
J
= T
A
+ P
TOTAL
J
.
1
Temperature range for B Version: -40C to +85C. Typical specifications are at 25C.
2
Guaranteed by design and characterization, not production tested.
3
Where
J
represents the package thermal impedance.
AC CHARACTERISTICS
DV
CC
= 2.5 V; V
DD
= 15 V; V
SS
= -15 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; C
L
= 200pF; R
L
= 10 k;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3. AC Characteristics
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
1
Output Voltage Settling Time
20
s typ
Full-scale change
30
s max
DAC latch contents alternately loaded with all 0s and all 1s.
Slew Rate
1
V/s typ
Digital-to-Analog Glitch Energy
20
nV-s typ
Glitch Impulse Peak Amplitude
10
mV max
Channel-to-Channel Isolation
100
dB typ
V
REF
(+) = 2 V p-p, 1 kHz.
DAC-to-DAC Crosstalk
40
nV-s typ
Between DACs in the same group.
10
nV-s typ
Between DACs from different groups.
Digital Crosstalk
0.1
nV-s typ
Digital Feedthrough
1
nV-s typ
Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 10 kHz
250
nV/(Hz)
1/2
typ
V
REF
= 0 V.
1
Guaranteed by design and characterization. Not production tested
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 6 of 23
TIMING CHARACTERISTICS
DV
CC
= 2.3 V to 5.5 V; V
DD
= 8 V to 16.5 V; V
SS
= -4.5 V to -16.5 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V;
R
L
= Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
SPI INTERFACE (Figure 4 and Figure 5)
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit
Description
t
1
20
ns min
SCLK Cycle Time.
t
2
8
ns min
SCLK High Time.
t
3
8
ns min
SCLK Low Time.
t
4
10
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time.
t
5
15
ns min
Minimum SYNC High Time.
t
6
5
ns min
24th SCLK Falling Edge to SYNC Rising Edge.
t
7
5
ns min
Data Setup Time.
t
8
4.5
ns min
Data Hold Time.
t
9
3
30
ns max
SYNC Rising Edge to BUSY Falling Edge.
t
10
480
ns max
BUSY Pulse Width Low (Single-Channel Update.) See
Table 7
t
11
480
ns max
Single-Channel Update Cycle Time
t
12
20
ns min
24th SCLK Falling Edge to LDAC Falling Edge.
t
13
20
ns min
LDAC Pulse Width Low.
t
14
150
ns typ
BUSY Rising Edge to DAC Output Response Time.
t
15
0
ns min
BUSY Rising Edge to LDAC Falling Edge.
t
16
100
ns min
LDAC Falling Edge to DAC Output Response Time.
t
17
20/30
s typ/max
DAC Output Settling Time.
t
18
350
ns max
CLR/RESET Pulse Activation Time.
t
19
10
ns
min
RESET Pulse Width Low.
t
20
120 s
max
RESET Time Indicated by BUSY
Low.
t
21
250
ns
min
Minimum SYNC High Time in Readback Mode.
t
22
5
25
ns max
SCLK Rising Edge to SDO Valid.
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
This is measured with the load circuit of Figure 2
5
This is measured with the load circuit of Figure 3.
TO
OUTPUT
PIN
V
CC
R
L
2.2k
C
L
50pF
V
OL
200A
200A
50pF
C
L
I
OL
I
OL
V
OH
(min) - V
OL
(max)
2
TO
OUTPUT
PIN
Figure 2.
Load Circuit for BUSY Timing
Figure 3. Load Circuit for SDO Timing Diagram
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 7 of 23
SCLK
SYNC
SDI
BUSY
LDAC
1
VOUT
1
LDAC
2
VOUT
2
VOUT
RESET
VOUT
CLR
1
2
t
1
t
3
t
2
24
t
5
t
4
t
6
t
7
t
8
DB23
DB0
24
t
9
t
10
t
12
t
13
t
14
t
17
t
15
t
13
t
16
t
17
t
18
t
19
t
18
t
20
1
LDAC ACTIVE DURING BUSY
2
LDAC ACTIVE AFTER BUSY
BUSY
5371-0004B
1
t
11
Figure 4.
SPI Write Timing
5371-0005C
SCLK
SYNC
SDI
SDO
24
48
DB23
DB0
DB23
DB23
DB0
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
UNDEFINED
NOP CONDITION
SELECTED REGISTER DATA
CLOCKED OUT
t
21
t
22
DB0
LSB FROM PREVIOUS READ
Figure 5.
SPI Read Timing
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 8 of 23
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4. Absolute Maximum Ratings
Parameter Rating
V
DD
to AGND
-0.3 V to +17 V
V
SS
to AGND
-17 V to +0.3 V
DV
CC
to DGND
-0.3 V to +7 V
Digital Inputs to DGND
-0.3 V to V
CC
+ 0.3 V
Digital Outputs to DGND
-0.3 V to V
CC
+ 0.3 V
V
REF
0, V
REF1
to AGND
-0.3 V to +5.5 V
VOUT0VOUT7 to AGND
V
SS
- 0.3 V to V
DD
+ 0.3 V
SIGGND to AGND
1 V
AGND to DGND
-0.3 V to +0.3 V
Operating Temperature Range (T
A
)
Industrial (B Version)
-40C to +85C
Storage Temperature Range
-65C to +150C
Junction Temperature (T
J
max)
150C
Reflow Soldering
Peak Temperature
230C
Time at Peak Temperature
10 s to 40 s
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 9 of 23
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
NC
NC
NC
NC
VDD
VSS
VREF0
NC = NO CONNECT
PIN 1
INDICATOR
AD5362/
AD5363
TOP VIEW
(Not to scale)
N
C
N
C
V
O
U
T
4
V
O
U
T
5
V
O
U
T
6
V
O
U
T
7
S
I
G
G
N
D
1
N
C
N
C
N
C
N
C
N
C
N
C
N
C
NC
NC
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF1
NC
NC
VSS
VDD
C
L
R
L
D
A
C
A
G
N
D
D
G
N
D
D
V
C
C
S
D
O
P
E
C
S
D
I
S
C
L
K
S
Y
N
C
D
V
C
C
D
G
N
D
N
C
N
C
5362LFCSP
39
38
37
36
35
34
33
32
31
30
29
28
27
NC = NO CONNECT
PIN 1
INDICATOR
AD5362/
AD5363
TOP VIEW
(Not to scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
52 51 50 49 48 47 46 45
43 42 41 40
44
LDAC
CLR
RESET
BIN/2SCOMP
BUSY
GPIO
MON_OUT
MON_IN0
NC
NC
VDD
VSS
VREF0
N
C
V
O
U
T
4
V
O
U
T
5
V
O
U
T
6
V
O
U
T
7
S
I
G
G
N
D
1
N
C
N
C
N
C
N
C
N
C
N
C
N
C
NC
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
TEMP_OUT
MON_IN1
VREF1
NC
VSS
VDD
NC
A
G
N
D
D
G
N
D
D
V
C
C
S
D
O
P
E
C
S
D
I
S
C
L
K
S
Y
N
C
D
V
C
C
D
G
N
D
N
C
N
C
N
C
Figure 6
. 56 Lead LFCSP Pin Configuration
Figure 7
. 52 Lead LQFP Pin Configuration
Table 5. Pin Function Descriptions
Pin Name
Function
DV
CC
Logic Power Supply; 2.3 V to 5.5 V. These pins should be decoupled with 0.1 F ceramic capacitors and 10 F capacitors.
V
SS
Negative Analog Power Supply; -11.4 V to -16.5 V for specified performance. These pins should be decoupled with 0.1 F
ceramic capacitors and 10 F capacitors.
V
DD
Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with 0.1 F
ceramic capacitors and 10 F capacitors.
AGND
Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
DGND
Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
SIGGND0
Reference Ground for DACs 0 to 3. VOUT0 to VOUT3 are referenced to this voltage.
SIGGND1
Reference Ground for DACs 4 to 7. VOUT4 to VOUT7 are referenced to this voltage.
V
REF
0
Reference Input for DACs 0 to 3. This voltage is referred to AGND.
V
REF
1
Reference Input for DACs 4 to 7. This voltage is referred to AGND.
VOUT0 to
VOUT15
DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each analog output is capable of driving an output
load of 10 k to ground. Typical output impedance of these amplifiers is 0.5 .
SYNC
Active Low or SYNC Input for SPI Interface. This is the frame synchronization signal for the SPI serial interface. See SPI
timing diagrams and descriptions for more details.
SCLK
Serial Clock Input for SPI Interface. See SPI timing diagrams and descriptions for more details.
SDI
Serial Data Input for SPI Interface. See SPI timing diagrams and descriptions for more details.
SDO
Serial Data Output for SPI Interface. See SPI timing diagrams and descriptions for more details.
LDAC
Load DAC Logic Input (Active Low). See the BUSY and LDAC FUNCTIONS section for more information.
BUSY
Digital Input/Open-Drain Output. See the BUSY and LDAC FUNCTIONS section for more information
RESET
Asynchronous Digital Reset Input
CLR
Asynchronous clear input (level sensitive, active low). See the Clear Function section for more information
PEC
Packet Error Check output. This is an open-drain output with a 50 k
pullup, that goes low if the packet error check fails.
TEMP_OUT
Provides an output voltage proportional to chip temperature. This is typically 1.5 V at 25 C with an output variation of 5
mV/C.
MON_OUT
Analog multiplexer output. Any DAC output or the MON_IN0 or the MON_IN1 input can be switched to this output.
MON_IN0,
MON_IN1
Analog multiplexer inputs, which can be switched to MON_OUT.
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 10 of 23
Pin Name
Function
GPIO
Digital I/O pin. This pin can be configured as an input or output that can be read or programmed high or low via the serial
interface. When configured as an input it has a weak pulldown.
BIN/2SCOMP
Digital input, sets the DAC coding. 0 = offset binary, 1 = 2's complement. This input has a weak pulldown.
EXPOSED
PADDLE
The Lead Free Chip Scale Package (LFCSP) has an exposed paddle on the underside. This should be connected to V
SS
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 11 of 23
TERMINOLOGY
Relative Accuracy
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. Zero-scale error is
mainly due to offsets in the output amplifier.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It does not include
zero-scale error.
Gain Error
Gain error is the difference between full-scale error
and zero-scale error. It is expressed in mV.
Gain Error = Full-Scale Error - Zero-Scale Error
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
V
DD
and V
SS
Vpower supplies. If the dc load current changes in
one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple V
DD
and V
SS
terminals are
provided to minimize dc crosstalk.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC's reference input that appears at the
output of another DAC operating from another reference. It is
expressed in dB and measured at midscale.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device's digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is
measured in nV/(Hz)
1/2
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 12 of 23
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE--GENERAL
The AD5362/AD5363 contains 8 DAC channels and 8 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit resistor-string DAC in the case of
the AD5362 and a 14-bit DAC in the case of the AD5363,
followed by an output buffer amplifier. The resistor-string
section is simply a string of resistors, each of value R, from V
REF
to AGND. This type of architecture guarantees DAC
monotonicity. The 16(14)-bit binary digital code loaded to the
DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies
the DAC out voltage by 4. The output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.
CHANNEL GROUPS
The 16 DAC channels of the AD5362/AD5363 are arranged into
two groups of 8 channels. The eight DACs of Group 0 derive
their reference voltage from VREF0, and those of Group 1 from
VREF1
Table 6. AD5362(AD5363) Registers
Register Name
Word Length (Bits)
Description
X1A (group)(channel)
16(14)
Input data register A, one for each DAC channel.
X1B (group) (channel)
16(14)
Input data register B, one for each DAC channel.
M (group) (channel)
16(14)
Gain trim registers, one for each DAC channel.
C (group) (channel)
16(14)
Offset trim registers, one for each DAC channel.
X2A (group)(channel)
16(14)
Output data register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
X2B (group) (channel)
16(14)
Output data register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
DAC (group) (channel)
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable, nor directly writable.
OFS0
14
Offset DAC 0 data register, sets offset for Group 0.
OFS1
14
Offset DAC 1 data register, sets offset for Group 1.
Control
8
Bit 4 = Overtemperature indicator. 1 = chip temperature > 130 C.
Bit 3 = PEC error flag. 1 = PEC error. Cleared on reading control register.
Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = X1B registers.
Bit 1 = Soft Power Down. 0 = soft power up. 1 = soft power down
Bit 0 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.
Monitor
6
Bit 5 = Monitor enable. 0 = off. 1 = on.
Bit 4 = 0, DAC selected by bits 3 to 0.
Bits 3 0 = DAC channel 0000 = 0 to 1111 = 15.
Bit 4 = 1, MON_IN pin selected by bit 0.
Bit 0 = MON_IN select. 0 = MON_IN0. 1 = MON_IN1.
GPIO
2
Bit 1 = GPIO configuration. 0 = input. 1 = output.
Bit 0 = GPIO data. Stores state of GPIO pin when input. Drives GPIO pin when output.
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 13 of 23
A/ B REGISTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data word can be written to either the X1A or X1B input
register, depending on the setting of the A/B bit in the Control
Register. If the A/B bit is 0, data will be written to the X1A
register. If the A/B bit is 1, data will be written to the X1B
register. Note that this single bit is a global control and affects
every DAC channel in the device. It is not possible to set up the
device on a per-channel basis so that some writes are to X1A
registers and some writes are to X1B registers.
DAC
DAC
REGISTER
MUX
X2B
REGISTER
X2A
REGISTER
MUX
M
REGISTER
C
REGISTER
X1B
REGISTER
X1A
REGISTER
Figure 8. Data Registers Associated With Each DAC Channel
Each DAC channel also has a gain (M) and offset (C) register,
which allow trimming out of the gain and offset errors of the
entire signal chain. Data from the X1A register is operated on
by a digital multiplier and adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is
operated on by the multiplier and adder and stored in the X2B
register.
Although a multiplier and adder symbol are shown for each
channel, there is only one multiplier and one adder in the
device, which are shared between all channels. This has
implications for the update speed when several channels are
updated at once, as described later.
Each time data is written to the X1A register, or to the M or C
register with the A/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B, or to
M or C with A/B set to 1. The X2A and X2B registers are not
readable, nor directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B Select Register associated with each group of 8
DACs. If a bit in this register is 0, the DAC takes its data from
the X2A register; if 1 the DAC takes its data from the X2B
register (bit 0 controls DAC 0 through bit 7 controls DAC 7).
Note that, since there are 8 bits in 2 registers, it is possible to set
up, on a per-channel basis, whether each DAC takes its data
from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B Select Registers to 0 or to 1.
All DACs in the AD5362/AD5363 can be updated
simultaneously by taking LDAC low, when each DAC register
will be updated from either its X2A or X2B register, depending
on the setting of the A/B select registers. The DAC register is
not readable, nor directly writable by the user.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are
two 14-bit Offset DACs, one for Group 0, and one for Group 1.
These allow the output range of all DACs connected to them to
be offset. Thus, subject to the limitations of headroom, it is
possible to set the output range of Group 0, and/or Group 1 to
be unipolar positive, unipolar negative, or bipolar, either
symmetrical or asymmetrical about zero volts.
OUTPUT AMPLIFIER
As the output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, this limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of
20V, since the maximum supply voltage is 16.5 V.
DAC
CHANNEL
OFFSET
DAC
CLR
CLR
CLR
SIGGND
SIGGND
OUTPUT
S1
S2
S3
R4
R1
R3
R5
R6
R2
CHECK VALUE OF R1 &R5
R1,R2,R3 = 20k
R4,R5 = 60k
R6 = 10k
2049-0008
10k
Figure 9. Output Amplifier and Offset DAC
Figure 9 shows details of a DAC output amplifier and its
connections to the Offset DAC. On power up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so the
output is pulled to SIGGND. S2 is also closed to prevent the
output amplifier being open-loop. If CLR is low at power-up,
the output will remain in this condition until CLR is taken high.
The DAC registers can be programmed, and the outputs will
assume the programmed values when CLR is taken high. Even
if CLR is high at power-up, the output will remain in the above
condition until V
DD
> 6 V and V
SS
< -4 V and the initialization
sequence has finished. The outputs will then go to their power-
on default value.
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 14 of 23
TRANSFER FUNCTION
From the foregoing, it can be seen that the output voltage of a
DAC in the AD5362/AD5363 depends on the value in the input
register, the value of the M and C registers, and the offset from
the Offset DAC. The transfer function is given by:
AD5362
Code applied to DAC from X1A or X1B register:-
DAC_CODE = INPUT_CODE
(m+1)/2
16
+ c - 2
15
DAC output voltage:-
V
OUT
= 4
V
REF
(DAC_CODE OFFSET_CODE
4 )/2
16
+V
SIGGND
Notes
Gain = 4.
For 12 V span V
REF
= 3.0 V.
For 20 V span V
REF
= 5.0 V.
X1A, X1B default code = 32768
m = code in gain register; default m code = 2
16
1.
c = code in offset register; default c code = 2
15
.
OFFSET_CODE is the 14-bit code written to the offset DAC
register. As this DAC is a 14 bit device, the code must by
multiplied by 4 or left-shift twice to make the transfer function
correct, since the X, M and C registers are 16-bit. The default
value for the Offset DAC is 8192 (0x2000)
AD5363
Code applied to DAC from X1A or X1B register:-
DAC_CODE = INPUT_CODE
(m+1)/2
14
+ c - 2
13
DAC output voltage:-
V
OUT
= 4
V
REF
(DAC_CODE OFFSET_CODE )/2
14
+V
SIGGND
Notes
Gain = 4.
For 12 V span V
REF
= 3.0 V.
For 20 V span V
REF
= 5.0 V.
X1A, X1B default code = 8192
m = code in gain register; default m code = 2
14
1.
c = code in offset register; default c code = 2
13
.
OFFSET_CODE is the code loaded to the offset DAC. The
default value for the Offset DAC is 8192 (0x2000)
REFERENCE SELECTION
The AD5362/AD5363 has two reference input pins. The voltage
applied to the reference pins determines the output voltage span
on VOUT0 to VOUT7. VREF0 determines the voltage span for
VOUT0 to VOUT3 and VREF1 determines the voltage span for
VOUT4to VOUT7. The reference voltage applied to each VREF
pin can be different, if required, allowing each group of 4
channels to have a different voltage span. The output voltage
range can be adjusted further by programming the offset and
gain registers for each channel as well as programming the
offset DAC. If the offset and gain features are not used (i.e. the
m and c registers are left at their default values) the required
reference levels can be calculated as follows:
VREF = (VOUT
max
VOUT
min
)/4
If the offset and gain features of the AD5362AD5363are used,
then the required output range is slightly different. The chosen
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the chosen
output range should be larger than the actual, required range.
The required reference levels can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum
gain required on the full output signal range.
3.
Calculate the new maximum output range on VOUT
including the expected maximum offset and gain
errors.
4.
Choose the new required VOUT
max
and VOUT
min
,
keeping the VOUT limits centered on the nominal
values. Note that V
DD
and V
SS
must provide sufficient
headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX VOUTMIN)/4
Reference Selection Example
Nominal Output Range = 20V (-10V to +10V)
Offset Error = 100mV
Gain Error = 3%
SIGGND = AGND = 0V
1)
Gain Error = 3%
=> Maximum Positive Gain Error = +3%
=> Output Range incl. Gain Error = 20 + 0.03(20)=20.6V
2)
Offset Error = 100mV
=> Maximum Offset Error Span = 2(100mV)=0.2V
=> Output Range including Gain Error and Offset Error =
20.6V + 0.2V = 20.8V
3)
VREF Calculation
Actual Output Range = 20.6V, that is -10.3V to +10.3V
(centered);
VREF = (10.3V + 10.3V)/4 = 5.15V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
1.
Use a resistor divider to divide down a convenient,
higher reference level to the required level.
2.
Select a convenient reference level above VREF and
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 15 of 23
modify the Gain and Offset registers to digitally
downsize the reference. In this way the user can use
almost any convenient reference level but may reduce
the performance by overcompaction of the transfer
function.
3.
Use a combination of these two approaches
CALIBRATION
The user can perform a system calibration by overwriting the
default values in the m and c registers for any individual DAC
channels as follows:
Calculate the nominal offset and gain coefficients for the
new output range (see previous example)
Calculate the new m and c values for each channel based on
the specified offset and gain errors
Calibration Example
Nominal Offset Coefficient = 8192
Nominal Gain Coefficient = 20/20.6 16383 = 15906
Example 1: Gain Error = 3%, Offset Error = 100mV
1) Gain Error (3%) Calibration: 15906 1.03 = 16383
=> Load Code "0b0011 1111 1111 1111" to m register
2) Offset Error (100mV) Calibration:
LSB Size = 20.6/16384 = 1.257 mV;
Offset Coefficient for100mV Offset = 100/1.257 = 80 LSBs
=> Load Code "0b1000 0000 0101 0000" to c register
For the AD5362 the 16-bit nominal gain and offset values
should be used.
RESET FUNCTION
When the RESET pin is taken low, the DAC buffers are
disconnected and the DAC outputs VOUT0 to VOUT7 are tied
to their associated SIGGND signals via a 10 k resistor. On the
rising edge of RESET the AD5362/AD5363 state machine
initiates a reset sequence to reset the X, M and C registers to
their default values. This sequence typically takes 300s and the
user should not write to the part during this time. When the
reset sequence is complete, and provided that CLR is high, the
DAC output will be at a potential specified by the default
register settings which will be equivalent to SIGGGND. The
DAC outputs will remain at SIGGND until the X, M or C
registers are updated and LDAC is taken low.
CLEAR FUNCTION
CLR is an active low input which should be high for normal
operation. The CLR pin has in internal 500k pull-down
resistor. When CLR is low, the input to each of the DAC output
buffer stages, VOUT0 to VOUT7, is switched to the externally
set potential on the relevant SIGGND pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the
DAC outputs remain cleared until LDAC is taken low. The
contents of input registers and DAC registers 0 to 7 are not
affected by taking CLR low. To prevent glitches appearing on
the outputs CLR should be brought low whenever the output
span is adjusted by writing to the offset DAC.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M registers.
During the calculation of X2, the BUSY output goes low. While
BUSY is low, the user can new data to the X1, M, or C registers,
provided the first stage of the calculation is complete (see the
Register Update Rates section for more details).
The BUSY pin is bidirectional and has a 50 k internal pullup
resistor. Where multiple AD5362 or AD5363 devices may be
used in one system the BUSY pins can be tied together. This is
useful where it is required that no DAC in any device is updated
until all other DACs are ready. When each device has finished
updating the X2 (A or B) registers it will release the BUSY pin.
If another device hasn't finished updating its X2 registers it will
hold BUSY low, thus delaying the effect of LDAC going low.
The DAC outputs are updated by taking the LDAC input low. If
LDAC goes low while BUSY is active, the LDAC event is stored
and the DAC outputs update immediately after BUSY goes
high. A user can also hold the LDAC input permanently low. In
this case, the DAC outputs update immediately after BUSY
goes high.
As described later, the AD5362/AD5363 has flexible addressing
that allows writing of data to a single channel, all channels in a
group, or all channels in the device. This means that several
register values may need to be calculated and updated. As there
is only one multiplier shared between 8 channels, this task must
be done sequentially, so the length of the BUSY pulse will vary
according to the number of channels being updated.
Table 7. BUSY Pulse Widths
Action
BUSY Pulse Width
(s max)
Loading X1A, X1B, C, or M to 1 channel
1.25
Loading X1A, X1B, C, or M to 2 channels
1.75
Loading X1A, X1B, C, or M to 8 channels
4.75
BUSY Pulse Width = ((Number of Channels +1) 500ns) +250ns
The AD5362/AD5363 contains an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
written to since the last time LDAC was brought low. Normally,
when LDAC is brought low, the DAC registers are filled with
the contents of the X2A or X2B registers, depending on the
setting of the A/B Select Registers. However the
AD5362/AD5363 updates the DAC register only if the X2 data
has changed, thereby removing unnecessary digital crosstalk.
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 16 of 23
BIN/2S COMP PIN
The BIN/2SCOMP pin determines if the input data is
interpreted as offset binary or 2's complement. If this pin is low,
then the data is binary. If it is 1, the data is interpreted as 2's
complement. This affects only the X, C, and Offset DAC
registers. The M register data and all control and command
data is interpreted as straight binary.
TEMPERATURE SENSOR
The on-chip temperature sensor provides a voltage output at
the TEMP_OUT pin that is linearly proportional to the
Centigrade temperature scale. The typical accuracy of the
temperature sensor is 1C at +25C and 5C over the -40C
to +85C range. Its nominal output voltage is 1.5V at +25C,
varying at 5 mV/C, giving a typical output range of 1.175V to
1.9 V over the full temperature range. Its low output
impedance, low self heating, and linear output simplify
interfacing to temperature control circuitry and A/D
converters.
MONITOR FUNCTION
The AD5362/AD5363 contains a channel monitor function that
consists of an analog multiplexer addressed via the serial
interface, allowing any channel output to be routed to this pin
for monitoring using an external ADC. In addition, two
monitor inputs, MON_IN0 and MON_IN1 are provided,
which can also be routed to MON_OUT. The monitor function
is controlled by the Monitor Register, which allows the monitor
output to be enabled or disabled, and selection of a DAC
channel or one of the monitor pins. When disabled, the
monitor output is high impedance, so several monitor outputs
may be connected in parallel and only one enabled at a time.
Table 8 shows the control register settings relevant to the
monitor function.
Table 8. Control Register Monitor Functions
F5 F4 F3 F2
F1
F0
0 X X X
X
X MON_OUT
Disabled
1 X X X
X
X MON_OUT
Enabled
1 0 0 0
0
X MON_OUT
=
VOUT0
1 0 0 0
0
1 MON_OUT
=
VOUT1
1 0 0 1
1
1 MON_OUT
=
VOUT7
1 1 0 0
0
0 MON_OUT
=
MON_IN0
1 1 0 0
0
1 MON_OUT
=
MON_IN1
The multiplexer is implemented as a series of analog switches.
Since this could conceivably cause a large amount of current to
flow from the input of the multiplexer, i.e. VOUTx or
MON_INx to the output of the multiplexer, MON_OUT, care
should taken to ensure that whatever is connected to the
MON_OUT pin is of high enough impedance to prevent the
Continuous Current Limit specification from being exceeded.
GPIO PIN
The AD5362/AD5363 has a general-purpose I/O pin, GPIO.
This can be configured as an input or an output and read back
or programmed (when configured as an output) via the serial
interface. Typical applications for this pin include monitoring
the status of a logic signal, limit switch, or controlling an
external multiplexer. The GPIO pin is configured by writing to
the GPIO register, which has the special function code of
0b001101 (see Table 11 and Table 13 ). When Bit F1 is set the
GPIO pin will be an output and F0 will determine whether the
pin is high or low. The GPIO pin can be set as an input by
writing 0 to both F1 and F0. The status of the GPIO pin can be
determined by initiating a read operation using the appropriate
bits in Table 14. The status of the pin will be indicated by the
LSB of the register read.
POWER-DOWN MODE
The AD5362/AD5363 can be powered down by setting Bit 0 in
the control register. This will turn off the DACs thus reducing
the current consumption. The DAC outputs will be connected
to their respective SIGGND potentials. The power-down mode
doesn't change the contents of the registers and the DACs will
return to their previous voltage when the power-down bit is
cleared.
TEMPERATURE MONITORING
The AD5362/AD5363 can be programmed to power down the
DACs if the temperature on the die exceeds 130C. Setting Bit 1
in the control register (see Table 13) will enable this function. If
the die temperature exceeds 130C the AD5362/AD5363 will
enter a temperature power-down mode, which is equivalent to
setting the power-down bit in the control register. To indicate
that the AD5362/AD5363 has entered temperature shutdown
mode Bit 4 of the control register is set. The AD5362/AD5363
will remain in temperature shutdown mode, even if the die
temperature falls, until Bit 1 in the control register is cleared.
TOGGLE MODE
The AD5362/AD5363 has two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a micro-processor which would otherwise have to
write to each channel individually. When the user writes to
either the X1A ,X2A, M or C registers the calculation engine
will take a certain amount of time to calculate the appropriate
X2A or X2B values. If the application only requires that the
DAC output switch between two levels, such as a data generator,
any method which reduces the amount of calculation time
encountered is advantageous. For the data generator example
the user need only set the high and low levels for each channel
once, by writing to the X1A and X1B registers. The values of
X2A and X2B will be calculated and stored in their respective
registers. The calculation delay therefore only happens during
the setup phase, i.e. when programming the initial values. To
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 17 of 23
toggle a DAC output between the two levels it is only required
to write to the relevant A/B Select Register to set the MUX2
register bit. Furthermore, since there are 4 MUX2 control bits
per register it is possible to update four channels with a single
write. Table 12 shows the bits that correspond to each DAC
output.
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 18 of 23
SERIAL INTERFACE
The AD5362/AD5363 contains an SPI-compatible interface
operating at clock frequencies up to 50MHz. To minimize both
the power consumption of the device and on-chip digital noise,
the interface powers up fully only when the device is being
written to, that is, on the falling edge of SYNC. The serial
interface is 2.5 V LVTTL compatible when operating from a
2.3 V to 3.6 V DV
CC
supply. It is controlled by four pins, as
follows.
SYNC
Frame synchronization input.
SDI
Serial data input pin.
SCLK
Clocks data in and out of the device.
SPI WRITE MODE
The AD5362/AD5363 allows writing of data via the serial
interface to every register directly accessible to the serial
interface, which is all registers except the X2A and X2B
registers and the DAC registers. The X2A and X2B registers are
update when writing to the X1A, X1B, M and C registers, and
the DAC registers are updated by LDAC.
The serial word (see Tables 7 and 8) is 24 bits long. 16(14) of
these bits are data bits, five bits are address bits, and two bits are
mode bits that determine what is done with the data.
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5362/AD5363 by clock pulses applied to SCLK. The first
falling edge of SYNC starts the write cycle. At least 24 falling
clock edges must be applied to SCLK to clock in 24 bits of data,
before SYNC is taken high again. If SYNC is taken high before
the 24th falling clock edge, the write operation will be aborted.
If a continuous clock is used, and PEC mode isn't used, SYNC
must be taken high before the 25th falling clock edge. This
inhibits the clock within the AD5362/AD5363. If more than 24
falling clock edges are applied before SYNC is taken high again,
the input data will be corrupted. If an externally gated clock of
exactly 24 pulses is used, SYNC may be taken high any time
after the 24th falling clock edge.
The input register addressed is updated on the rising edge of
SYNC. In order for another serial transfer to take place, SYNC
must be taken low again.
REGISTER UPDATE RATES
As mentioned previously the value of the X2 (A or B) register is
calculated each time the user writes new data to the
corresponding X1, C or M registers. The calculation is
performed by a three stage process. The first two stages take
500ns each and the third stage takes 250ns. When the writes to
one of the X1, C or M registers is complete the calculation
process begins. If the write operation involves the update of a
single DAC channel the user is free to write to another register
provided that the write operation doesn't finish until the first
stage calculation is complete, i.e. 500ns after the completion of
the first write operation. If a group of channels is being updated
by a single write operation the first stage calculation will be
repeated for each channel, taking 500ns per channel. In this
case the user should not complete the next write operation until
this time has elapsed.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5362/AD5363 offers the option of error
checking based on an 8-bit (CRC-8) cyclic redundancy check.
The device controlling the AD5362/AD5363 should generate an
8-bit frame check sequence using the polynomial C(x) = x
8
+ x
2
+ x
1
+1. This is added to the end of the data word, and 32 data
bits are sent to the AD5362/AD5363 before taking SYNC high.
If the AD5362/AD5363 sees a 32-bit data frame, it will perform
the error check when SYNC goes high. If the check is valid,
then the data will be written to the selected register. If the error
check fails, the Packet Error Check output (PEC) will go low
and bit 3 of the Control Register is set. After reading this
register, this error flag is cleared automatically and PEC goes
high again.
SYNC
SCLK
DIN
24-BIT DATA TRANSFER - NO ERROR CHECKING
SYNC
SCLK
DIN
MSB
D23
LSB
D0
MSB
D31
LSB
D8
D7
D0
UPDATE ON SYNC HIGH
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
24-BIT DATA
24 BIT DATA
24-BIT DATA TRANSFER WITH ERROR CHECKING
8-BIT FCS
PEC
PEC GOES LOW IF
ERROR CHECK FAILS
5360-0010
Figure 10. SPI Write With and Without Error Checking
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 19 of 23
Table 7. AD5362 Serial Word Bit Assignation
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 8. AD5363 Serial Word Bit Assignation
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1* I0*
M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
M1 and M0 are mode bits.
A5 is an unused address bit and must always be written as 0.
A4 to A0 are address bits.
D15 to D0 are data bits.
*In the AD5363, bits I1 and I0 only used in Special Function Mode
SPI READBACK MODE
The AD5362/AD5363 allows data readback via the serial
interface from every register directly accessible to the serial
interface, which is all registers except the X2A, X2B and DAC
registers. In order to read back a register, it is first necessary to
tell the AD5362/AD5363 which register is to be read. This is
achieved by writing to the device a word whose first two bits are
the special function code 00. The remaining bits then
determine if the operation is a readback, and the register which
is to be read back, or if it is a write to of the special function
registers such as the control register.
After the special function write has been performed, if it is a
readback command then data from the selected register will be
clocked out of the SDO pin during the next SPI operation. The
SDO pin is normally three-state but becomes driven as soon as
a read command has been issued. The pin will remain driven
until the registers data has been clocked out. See Figure 5 for
the read timing diagram.
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, then the data word D15 to D0 is
written to the device. Address bits A4 to A0 determine which
channel or channels is/are written to, while the mode bits
determine to which register (X1A, X1B, C or M) the data is
written, as shown in Table 7. If data is to be written to the X1A
or X1B register, the setting of the A/B bit in the Control
Register determines which (0 X1A, 1 X1B).
Table 9. Mode Bits
M1 M0 Action
1 1 Write DAC input data (X1A or X1B) register,
depending on Control Register A/B bit.
1
0
Write DAC offset (C) register
0
1
Write DAC gain (M) register
0 0 Special function, used in combination with other
bits of word
The AD5362/AD5363 has very flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in groups 0 and 1, or all channels in the device.
Table 11 shows all these address modes.
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 20 of 23
Table 10.Group and Channel Addressing
This table shows which groups(s) and which channel(s) is/are addressed for every combination of address bits A4 to A0.
ADDRESS BITS A4 TO A3
00 01 10 11
000
All groups, all channels
Group 0, channel 0
Group 1, channel 0
Unused
001
Group 0, all channels
Group 0, channel 1
Group 1, channel 1
Unused
010
Group 1, all channels
Group 0, channel 2
Group 1, channel 2
Unused
011
Unused
Group 0, channel 3
Group 1, channel 3
Unused
100
Unused
Unused
Unused
Unused
101
Unused
Unused
Unused
Unused
110
Unused
Unused
Unused
Unused
ADDRESS
BITS A2 TO
A0
111
Unused
Unused
Unused
Unused
SPECIAL FUNCTION MODE
If the mode bits are 00, then the special function mode is
selected, as shown in Table 12. Bits I21 to I16 of the serial data
word select the special function, while the remaining bits are
data required for execution of the special function, for example
the channel address for data readback.
The codes for the special functions are shown in Table 13. Table
14 shows the addresses for data readback.
Table 11. Special Function Mode
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
Table 12. DACs Select by A/B Select Registers
Bits
A/B Select
Register
F7 F6 F5 F4 F3 F2 F1 F0
0
Not Used
Not Used
Not Used
Not Used
VOUT3
VOUT2
VOUT1
VOUT0
1
Not Used
Not Used
Not Used
Not Used
VOUT7
VOUT6
VOUT5
VOUT4
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 21 of 23
Table 13. Special Function Codes
SPECIAL FUNCTION CODE
DATA
S5 S4 S3 S2 S1 S0 F15-F0
ACTION
0 0 0 0 0 0 0000
0000
0000
0000
NOP
0
0
0
0
0
1
XXXX XXXX XXX[F4:F0]
Write control register
F4 = 1
Over-temperature; F4 = 0
Temp OK
F3 = 1
PEC error; F3 = 0
PEC OK
F2 = 1
Select B Register for input;
F2 = 0
Select A Register for input
F1 = 1
Enable temperature shutdown;
F1 = 0
Disable temperature shutdown
F0 = 1
Soft power down; F0 = 0
Soft power up
0
0
0
0
1
0
[F13:F0]
Write data in F13:F0 to OFS0 register
0
0
0
0
1
1
[F13:F0]
Write data in F13:F0 to OFS1 register
0 0 0 1 0 1 See
Table 14
Select register for readback
0
0
0
1
1
0
XXXX XXXX XXXX [F3:F0]
Write data in F3:F0 to A/B Select Register 0 (Group 0)
0
0
0
1
1
1
XXXX XXXX XXXX [F3:F0]
Write data in F3:F0 to A/B Select Register 1 (Group 1)
0
0
1
1
0
0
XXXX XXXX XX[F5:F0]
F5 = 1
Monitor enable; F5 = 0
Monitor disable
F4 = 1
Monitor input pin selected by F0
(0 = MON_IN0, 1 = MON_IN1)
F4 = 0
Monitor DAC channel selected by F3:F0
(0000 = channel 0
0111 = channel 7)
0
0
1
1
0
1
XXXX XXXX XXXX XX[F1:F0]
GPIO configure and write
F1 = 1
GPIO is output. Data to output is written to F0
F1 = 0
GPIO is input. Data can be read from F0 on readback
Note. When writing to the offset registers, the 14-bit data is right justified (bits F15 and F14 are don't care). When writing to the X, M or C registers of the AD5363, the
14-bit data is left-justified (bits 1 and 0 of the data word are don't care).
Table 14. Address Codes for Data Readback
F15 F14 F13 F12 F11 F10 F9 F8 F7 REGISTER
READ
1
0 0 0
X1A
Register
0 0 1
X2B
Register
0 1 0
C
Register
0 1 1
Bits F12 to F7 select channel to be read
back, from Channel 0 = 000000 to
Channel 7 = 000111
M Register
1 0 0 0 0 0 0 0 1 Control
Register
1 0 0 0 0 0 0 1 0 OFS0
Data
Register
1 0 0 0 0 0 0 1 1 OFS1
Data
Register
1 0 0 0 0 0 1 1 0 A/B
Select
Register
0
1 0 0 0 0 0 1 1 1 A/B
Select
Register
1
1 0 0 0 0 1 0 1 1 GPIO
read
(data
in
F0)
2
1
F6 to F0 are don't care for data readback functions except for GPIO read.
2
F6 to F0 should be 0 for GPIO read
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5362/AD5363 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5362/AD5363 is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (V
SS
, V
DD
, V
CC
), it
AD5362/AD5363
Preliminary Technical Data
Rev. Pr C | Page 22 of 23
is recommended to tie these pins together and to decouple each
supply once.
The AD5362/AD5363 should have ample supply decoupling of
10 F in parallel with 0.1 F on each supply located as close to
the package as possible, ideally right up against the device. The
10 F capacitors are the tantalum bead type. The 0.1 F capaci-
tor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5362/AD5363 to
avoid noise coupling. The power supply lines of the
AD5362/AD5363 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching digital signals should
be shielded with digital ground to avoid radiating noise to other
parts of the board, and should never be run near the reference
inputs. It is essential to minimize noise on all V
REF
lines.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5362/AD5363 it is
important that the AGND and DGND pins are connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications this is not an issue as the
ground pins for the power supplies will be connected to the
ground pins of the AD5362/AD5363 via ground planes. Where
the AD5362/AD5363 is to be used in a hot-swap card care
should be taken to ensure that the ground pins are connected to
the supply grounds before the positive or negative supplies are
connected. This is required to prevent currents flowing in
directions other than towards an analog or digital ground.
INTERFACING EXAMPLES
The SPI interface of the AD5362 and AD5363 are designed to
allow the parts to be easily connected to industry standard DSPs
and micro-controllers. Figure 10 shows how the
AD5362/AD5363 could be connected to the Analog Devices
BlackfinTM DSP. The Blackfin has an integrated SPI port which
can be connected directly to the SPI pins of the AD5362 or
AD5363 and programmable I/O pins which can be used to set
or read the state of the digital input or output pins associated
with the interface.
SYNC
SCLK
SDI
SDO
CLR
LDAC
RESET
BUSY
SPISELx
SCK
MOSI
MISO
PF8
PF9
PF10
PF7
AD536x
ADSP-BF531
536x-0101
Figure 10. Interfacing to a Blackfin DSP
The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTS). Figure 11 shows how one SPORT
can be used to control the AD5362 or AD5363. In this example
the Transmit Frame Synchronization (TFS) pin is connected to
the Receive Frame Synchronization (RFS) pin. Similarly the
transmit and receive clocks (TCLK and RCLK) are also
connected together. The user can write to the AD5362 or
AD5363 by writing to the transmit register. A read operation
can be accomplished by first writing to the AD5362/AD5363 to
tell the part that a read operation is required. A second write
operation with a NOP instruction will cause the data to be read
from the AD5362/AD5363. The DSPs receive interrupt can be
used to indicate when the read operation is complete.
SYNC
SCLK
SDI
SDO
CLR
LDAC
RESET
BUSY
TFSx
RFSx
TCLKx
RCLKx
DTxA
DRxA
FLAG2
FLAG1
FLAG0
FLAG3
AD536x
536x-0101
ADSP-21065L
Figure 11. Interfacing to a ADSP-21065L DSP
Preliminary Technical Data
AD5362/AD5363
Rev. Pr C | Page 23 of 23
OUTLINE DIMENSIONS
PIN 1
INDICATOR
TOP
VIEW
7.75
BSC SQ
8.00
BSC SQ
1
56
14
15
43
42
28
29
6.25
6.10 SQ
5.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
0.20 REF
12 MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
6.50
REF
SEATING
PLANE
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
0.05 MAX
0.02 NOM
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 11. 56 Lead LFCSP Package
Dimensions shown in millimeters
TOP VIEW
(PINS DOWN)
40
52
1
14
13
26
27
39
0.65
BSC
12.00 BSC
SQ
10.00
BSC SQ
0.38
0.32
0.22
1.60
MAX
SEATING
PLANE
0.75
0.60
0.45
VIEW A
0.20
0.09
1.45
1.40
1.35
0.10 MAX
COPLANARITY
VIEW A
ROTATED 90 CCW
SEATING
PLANE
10
6
2
7
3.5
0
0.15
0.05
PIN 1
COMPLIANT TO JEDEC STANDARDS MS-026BCC
Figure 12. 52 Lead LQFP Package
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD5362BCPZ
-40C to +85C
56-Lead LFCSP
CP-56
AD5362BSTZ
-40C to +85C
52-Lead LQFP
ST-52
AD5363BCPZ
-40C to +85C
56-Lead LFCSP
CP-56
AD5363BSTZ
-40C to +85C
52-Lead LQFP
ST-52
PR05762-0-9/05(PrC)
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