32-Channel, 3 V/5 V, Single-Supply,

14-Bit, Voltage Output DAC

AD5382

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: 40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm Ч 14 mm)
User Interfaces:

Parallel
Serial (SPI®/QSPITM/MICROWIRETM/DSP compatible,

featuring data readback)

C® compatible

INTEGRATED FUNCTIONS

Channel monitor
Simultaneous output update via LDAC

Clear function to user programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor

APPLICATIONS

Variable optical attenuators (VOA)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation

FUNCTIONAL BLOCK DIAGRAM

VOUT0

DAC 0

DAC

REG 0

INPUT
REG 0

m REG 0

c REG 0

1.25V/2.5V

REFERENCE

POWER-ON

RESET

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

DAC 1

DAC

REG 1

INPUT
REG 1

m REG 1

c REG 1

VOUT6

DAC 6

DAC

REG 6

INPUT
REG 6

m REG 6

c REG 6

VOUT7

VOUT8

DAC 7

DAC

REG 7

INPUT
REG 7

m REG 7

c REG 7

Ч4

03733-0-001

FIFO

STATE

MACHINE

CONTROL

LOGIC

INTERFACE

CONTROL

LOGIC

DB13/(DIN/SDA)

DB12/(SCLK/SCL)

DB11/(SPI/I2C)

DB10

A4
A0

REG 0

REG 1

RESET

BUSY

CLR

MON_IN1
MON_IN2
MON_IN3
MON_IN4

SER/PAR

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO

36-TO-1

MUX

OUT

0.........V

OUT

MON_OUT

LDAC

VOUT31

DVDD (Ч3)

DGND (Ч3)

AVDD (Ч4)

AGND (Ч4)

DAC GND (Ч4)

REFGND

REFOUT/REFIN

SIGNAL GND (Ч4)

AD5382

DB0

Figure 1.

AD5382

Rev. 0 | Page 2 of 40

TABLE OF CONTENTS

General Description ......................................................................... 3

Specifications..................................................................................... 4

AD5382-5 Specifications ............................................................. 4

AD5382-3 Specifications ............................................................. 6

AC Characteristics........................................................................ 7

Timing Characteristics..................................................................... 8

SPI, QSPI, MICROWIRE, or DSP Compatible Serial
Interface .................................................................................... 8

C Serial Interface...................................................................... 10

Parallel Interface ......................................................................... 11

Absolute Maximum Ratings.......................................................... 13

Pin Configuration and Function Descriptions........................... 14

Terminology .................................................................................... 17

Typical Performance Characteristics ........................................... 18

Functional Description .................................................................. 21

DAC Architecture--General..................................................... 21

Data Decoding ............................................................................ 21

On-Chip Special Function Registers (SFR) ............................ 22

SFR Commands .......................................................................... 22

Hardware Functions....................................................................... 25

Reset Function ............................................................................ 25

Asynchronous Clear Function.................................................. 25

BUSY and LDAC Functions...................................................... 25

FIFO Operation in Parallel Mode ............................................ 25

Power-On Reset.......................................................................... 25

Power-Down ............................................................................... 25

AD5382 Interfaces.......................................................................... 26

DSP, SPI, Microwire Compatible Serial Interfaces................. 26

C Serial Interface ..................................................................... 28

Parallel Interface......................................................................... 30

Microprocessor Interfacing....................................................... 31

Application Information................................................................ 33

Power Supply Decoupling ......................................................... 33

Typical Configuration Circuit .................................................. 33

AD5382 Monitor Function ....................................................... 34

Toggle Mode Function............................................................... 34

Thermal Monitor Function....................................................... 35

AD5382 in a MEMS Based Optical Switch............................. 35

Optical Attenuators .................................................................... 36

Outline Dimensions ....................................................................... 37

Ordering Guide .......................................................................... 37

REVISION HISTORY

5/04--Revision 0: Initial Version

AD5382

Rev. 0 | Page 3 of 40

GENERAL DESCRIPTION

The AD5382 is a complete, single-supply, 32-channel, 14-bit
DAC available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5382 includes an internal software-selectable 1.25 V/
2.5 V, 10 ppm/°C reference, an on-chip channel monitor
function that multiplexes the analog outputs to a common
MON_OUT pin for external monitoring, and an output
amplifier boost mode that allows optimization of the amplifier
slew rate. The AD5382 contains a double-buffered parallel
interface that features a 20 ns WR pulse width, an SPI/QSPI/
MICROWIRE/DSP compatible serial interface with interface

speeds in excess of 30 MHz and an I2C compatible interface
that supports a 400 kHz data transfer rate.

An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated indepen-
dently or simultaneously using the LDAC input.

Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC channel.
Power consumption is typically 0.25 mA/channel when
operating with boost mode disabled.

Table 1. Other High Channel Count, Low Voltage, Single Supply DACs in Product Portfolio

Model Resolution

Range

Output Channels

Linearity Error (LSB) Package

Description Package

Option

AD5380BST-5

14 Bits

4.5 V to 5.5 V

±4

100-Lead LQFP

ST-100

AD5380BST-3

14 Bits

2.7 V to 3.6 V

±4

100-Lead LQFP

ST-100

AD5384BBC-5

14 Bits

4.5 V to 5.5 V

±4

100-Lead CSPBGA

BC-100

AD5384BBC-3

14 Bits

2.7 V to 3.6 V

±4

100-Lead CSPBGA

BC-100

AD5381BST-5

12 Bits

4.5 V to 5.5 V

±1

100-Lead LQFP

ST-100

AD5381BST-3

12 Bits

2.7 V to 3.6 V

±1

100-Lead LQFP

ST-100

AD5383BST-5

12 Bits

4.5 V to 5.5 V

±1

100-Lead LQFP

ST-100

AD5383BST-3

12 Bits

2.7 V to 3.6 V

±1

100-Lead LQFP

ST-100

AD5390BST-5

14 Bits

4.5 V to 5.5 V

±3

52-Lead LQFP

ST-52

AD5390BCP-5

14 Bits

4.5 V to 5.5 V

±3

64-Lead LFCSP

CP-64

AD5390BST-3

14 Bits

2.7 V to 3.6 V

±3

52-Lead LQFP

ST-52

AD5390BCP-3

14 Bits

2.7 V to 3.6 V

±3

64-Lead LFCSP

CP-64

AD5391BST-5

12 Bits

4.5 V to 5.5 V

±1

52-Lead LQFP

ST-52

AD5391BCP-5

12 Bits

4.5 V to 5.5 V

±1

64-Lead LFCSP

CP-64

AD5391BST-3

12 Bits

2.7 V to 3.6 V

±1

52-Lead LQFP

ST-52

AD5391BCP-3

12 Bits

2.7 V to 3.6 V

±1

64-Lead LFCSP

CP-64

AD5392BST-5

14 Bits

4.5 V to 5.5 V

±3

52-Lead LQFP

ST-52

AD5392BCP-5

14 Bits

4.5 V to 5.5 V

±3

64-Lead LFCSP

CP-64

AD5392BST-3

14 Bits

2.7 V to 3.6 V

±3

52-Lead LQFP

ST-52

AD5392BCP-3

14 Bits

2.7 V to 3.6 V

±3

64-Lead LFCSP

CP-64

Table 2. 40-Channel Bipolar Voltage Output DAC

Model

Resolution

Analog Supplies

Output Channels

Linearity Error (LSB)

Package

Package Option

AD5379ABC

14 Bits

±11.4 V to ±16.5 V

±3

108-Lead CSPBGA

BC-108

AD5382

Rev. 0 | Page 4 of 40

SPECIFICATIONS

AD5382-5 SPECIFICATIONS

Table 3. AV

= 4.5 V to 5.5 V; DV

= 2.7 V to 5.5 V, AGND = DGND = 0 V;

External REFIN = 2.5 V; all specifications T

MIN

to T

MAX

, unless otherwise noted

Parameter

AD5382-5

Unit

Test Conditions/Comments

ACCURACY

Resolution 14

Bits

Relative Accuracy

(INL)

±4

LSB max

Differential Nonlinearity (DNL)

1/+2

LSB max

Guaranteed monotonic over temperature

Zero-Scale Error

mV max

Offset Error

±4

mV max

Measured at Code 32 in the linear region

Offset Error TC

±5

µV/°C typ

Gain Error

±0.024

% FSR max

At 25°C

±0.06

% FSR max

MIN

to T

MAX

Gain Temperature Coefficient

ppm FSR/°C typ

DC Crosstalk

0.5

LSB max

REFERENCE INPUT/OUTPUT

Reference Input

Reference Input Voltage

2.5

±1% for specified performance, AVdd=2xREFIN+50mV

DC Input Impedance

M min

Typically 100 M

Input Current

±1

µA max

Typically ±30 nA

Reference Range

1 to V

V min/max

Reference Output

Enabled via CR10 in the AD5382 control register.
CR12 selects the reference voltage.

Output Voltage

2.495/2.505

V min/max

At ambient. CR12 = 1. Optimized for 2.5 V operation.

1.22/1.28

V min/max

1.25 V reference selected. CR12 = 0

Reference TC

±10

ppm/°C max

Temperature Range : +25°C to +85°C

±15

ppm/°C max

Temperature Range : 40°C to +85°C

OUTPUT CHARACTERISTICS

Output Voltage Range

0/AV

V min/max

Short-Circuit Current

mA max

Load Current

±1

mA max

Capacitive Load Stability

200

pF max

= 5 k

1000

pF max

DC Output Impedance

0.5

max

MONITOR PIN

Output Impedance

500

typ

Three-State Leakage Current

100

nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)

= 2.7 V to 5.5 V

, Input High Voltage

V min

, Input Low Voltage

0.8

V max

Input Current

±10

µA max

Total for all pins. T

= T

MIN

to T

MAX

Pin Capacitance

pF max

LOGIC INPUTS (SDA, SCL ONLY)

, Input High Voltage

0.7 DV

V min

SMBus compatible at DV

< 3.6 V

, Input Low Voltage

0.3 DV

V max

SMBus compatible at DV

< 3.6 V

, Input Leakage Current

±1

µA max

HYST

, Input Hysteresis

0.05 DV

V min

, Input Capacitance

pF typ

Glitch Rejection

ns max

Input filtering suppresses noise spikes of less than 50 ns

AD5382

Rev. 0 | Page 5 of 40

Parameter

AD5382-5

Unit

Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)

, Output Low Voltage

0.4

V max

= 5 V ± 10%, sinking 200 µA

, Output High Voltage

V min

= 5 V ± 10%, sourcing 200 µA

, Output Low Voltage

0.4

V max

= 2.7 V to 3.6 V, sinking 200 µA

, Output High Voltage

0.5

V min

= 2.7 V to 3.6 V, sourcing 200 µA

High Impedance Leakage Current

±1

µA max

SDO only

High Impedance Output Capacitance

pF typ

SDO only

LOGIC OUTPUT (SDA)

, Output Low Voltage

0.4

V max

SINK

= 3 mA

0.6

V max

SINK

= 6 mA

Three-State Leakage Current

±1

µA max

Three-State Output Capacitance

pF typ

POWER REQUIREMENTS

4.5/5.5

V min/max

2.7/5.5

V min/max

Power Supply Sensitivity

Mid Scale/V

dB typ

0.375

mA/channel max

Outputs unloaded, Boost off. 0.25 mA/channel typ

0.475

mA/channel max

Outputs unloaded, Boost on. 0.325 mA/channel typ

mA max

= DV

, V

= DGND.

(Power-Down)

µA max

Typically 200 nA

(Power-Down)

µA max

Typically 3 µA

Power Dissipation

mW max

Outputs unloaded, Boost off, AV

= DV

= 5 V

AD5382-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: 40°C to +85°C.

Accuracy guaranteed from V

OUT

= 10 mV to AV

50 mV.

Guaranteed by characterization, not production tested.

Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded

accuracy specifications.

AD5382

Rev. 0 | Page 6 of 40

AD5382-3 SPECIFICATIONS

Table 4. AV

= 2.7 V to 3.6 V; DV

= 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V;

all specifications T

MIN

to T

MAX

, unless otherwise noted

Parameter

AD5382-3

Unit

Test Conditions/Comments

ACCURACY

Resolution

Bits

Relative Accuracy

(INL)

±4

LSB max

Differential Nonlinearity (DNL)

1/+2

LSB max

Guaranteed monotonic over temperature

Zero-Scale Error

mV max

Offset Error

±4

mV max

Measured at Code 64 in the linear region

Offset Error TC

±5

µV/°C typ

Gain Error

±0.024

% FSR max

At 25 °C

±0.06

% FSR max

MIN

to T

MAX

Gain Temperature Coefficient

ppm FSR/°C typ

DC Crosstalk

0.5

LSB max

REFERENCE INPUT/OUTPUT

Reference Input

Reference Input Voltage

1.25

±1% for specified performance

DC Input Impedance

M min

Typically 100 M

Input Current

±10

µA max

Typically ±30 nA

Reference Range

1 to AV

V min/max

Reference Output

Enabled via CR10 in the AD5382 control register.
CR12 selects the reference voltage.

Output Voltage

1.247/1.253

V min/max

At ambient. CR12 = 0. Optimized for 1.25 V operation

2.43/2.57

V min/max

2.5 V reference selected, CR12 = 1

Reference TC

±10

ppm/°C max

Temperature Range : +25°C to +85°C

±15

ppm/°C max

Temperature Range :40°C to +85°C

OUTPUT CHARACTERISTICS

Output Voltage Range

0/AV

V min/max

Short-Circuit Current

mA max

Load Current

±1

mA max

Capacitive Load Stability

200

pF max

= 5 k

1000

pF max

DC Output Impedance

0.5

max

MONITOR PIN (MON OUT)

Output Impedance

500

typ

Three-State Leakage Current

100

nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)

= 2.7 V to 3.6 V

, Input High Voltage

V min

IL,

Input Low Voltage

0.8

V max

Input Current

±10

µA max

Total for all pins. T

= T

MIN

to T

MAX

Pin Capacitance

pF max

LOGIC INPUTS (SDA, SCL ONLY)

, Input High Voltage

0.7 DV

V min

SMBus compatible at DV

< 3.6 V

, Input Low Voltage

0.3 DV

V max

SMBus compatible at DV

< 3.6 V

, Input Leakage Current

±1

µAmax

HYST

, Input Hysteresis

0.05 DV

min

, Input Capacitance

pF typ

Glitch Rejection

ns max

Input filtering suppresses noise spikes of less than 50 ns

AD5382

Rev. 0 | Page 7 of 40

Parameter

AD5382-3

Unit

Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)

, Output Low Voltage

0.4

V max

Sinking 200 µA

, Output High Voltage

0.5

V min

Sourcing 200 µA

High Impedance Leakage Current

±1

µA max

SDO only

High Impedance Output Capacitance

pF typ

SDO only

LOGIC OUTPUT (SDA)

, Output Low Voltage

0.4

V max

SINK

= 3 mA

0.6

V max

SINK

= 6 mA

Three-State Leakage Current

±1

µA max

Three-State Output Capacitance

pF typ

POWER REQUIREMENTS

2.7/3.6

V min/max

2.7/5.5

V min/max

Power Supply Sensitivity

Midscale/V

dB typ

0.375

mA/channel max

Outputs unloaded, Boost off. 0.25 mA/channel typ

0.475

mA/channel max

Outputs unloaded, Boost on. 0.325 mA/channel typ

mA max

= DV

, V

= DGND.

(Power-Down)

µA max

(Power-Down)

µA max

Power Dissipation

mW max

Outputs unloaded, Boost off, AV

= DV

= 3 V

AD5382-3 is calibrated using an external 1.25 V reference. Temperature range is 40°C to +85°C.

Accuracy guaranteed from V

OUT

= 10 mV to AV

50 mV.

Guaranteed by characterization, not production tested.

Default on the AD5382-5 is 2.5 V. Programmable to 1.25 V via CR12 in the AD5382 control register; operating the AD5382-5 with a 1.25 V reference leads to degraded

accuracy specifications.

AC CHARACTERISTICS

Table 5. AV

= 4.5 V to 5.5 V; DV

= 2.7 V to 5.5 V; AGND = DGND= 0 V

Parameter

All

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time

1/4 scale to 3/4 scale change settling to ±1 LSB.

µs

typ

µs

max

Slew Rate

V/µs typ

Boost mode off, CR11 = 0

V/µs typ

Boost mode on, CR11 = 1

Digital-to-Analog Glitch Energy

nV-s typ

Glitch Impulse Peak Amplitude

mV typ

Channel-to-Channel Isolation

100

dB typ

See Terminology section

DAC-to-DAC Crosstalk

nV-s typ

See Terminology section

Digital Crosstalk

0.8

nV-s typ

Digital Feedthrough

0.1

nV-s typ

Effect of input bus activity on DAC output under test

Output Noise 0.1 Hz to 10 Hz

µV p-p typ

External reference, midscale loaded to DAC

µV p-p typ

Internal reference, midscale loaded to DAC

Output Noise Spectral Density

@ 1 kHz

150

nV/Hz typ

@ 10 kHz

100

nV/Hz typ

Guaranteed by design and characterization, not production tested.

The slew rate can be programmed via the current boost control bit (CR11 ) in the AD5382 control register.

AD5382

Rev. 0 | Page 8 of 40

TIMING CHARACTERISTICS

SPI, QSPI, MICROWIRE, OR DSP COMPATIBLE SERIAL INTERFACE

Table 6. DV

= 2.7 V to 5.5 V ; AV

= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications

MIN

to T

MAX

, unless otherwise noted

Parameter

1, 2, 3

Limit at T

MIN

, T

MAX

Unit

Description

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK falling edge setup time

ns min

24th SCLK falling edge to SYNC falling edge

min

Minimum SYNC low time

ns min

Minimum SYNC high time

ns min

Minimum SYNC high time in Readback mode

ns min

Data setup time

4.5

ns min

Data hold time

ns max

24th SCLK falling edge to BUSY falling edge

670

ns max

BUSY pulse width low (single channel update)

min

24th SCLK falling edge to LDAC falling edge

ns min

LDAC pulse width low

100

ns max

BUSY rising edge to DAC output response time

ns min

BUSY rising edge to LDAC falling edge

100

ns min

LDAC falling edge to DAC output response time

µs typ

DAC output settling time

ns min

CLR pulse width low

µs

max

CLR pulse activation time

ns max

SCLK rising edge to SDO valid

min

SCLK falling edge to SYNC rising edge

ns min

SYNC rising edge to SCLK rising edge

min

SYNC rising edge to LDAC falling edge

Guaranteed by design and characterization, not production tested.

All input signals are specified with t

= t

= 5 ns (10% to 90% of V

) and are timed from a voltage level of 1.2 V.

See Figure 2, Figure 3, Figure 4, and Figure 5.

Standalone mode only.

Daisy-chain mode only.

50pF

TO OUTPUT PIN

(MIN) OR

(MAX)

200

03731-0-003

Figure 2. Load Circuit for SDO Timing Diagram

(Serial Interface, Daisy-Chain Mode)

AD5382

Rev. 0 | Page 9 of 40

LDAC ACTIVE DURING BUSY

LDAC ACTIVE AFTER BUSY

BUSY

SYNC

LDAC

CLR

OUT

DIN

SCLK

03731-0-004

DB0

DB23

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

SCLK

SYNC

DIN

SDO

DB23

DB0

DB23

DB0

DB23

DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

UNDEFINED

NOP CONDITION

SELECTED REGISTER

DATA CLOCKED OUT

03731-0-005

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

SCLK

SYNC

SDO

DIN

LDAC

DB23

DB0

DB23

DB0

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N+1

UNDEFINED

INPUT WORD FOR DAC N

03731-0-006

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

AD5382

Rev. 0 | Page 10 of 40

C SERIAL INTERFACE

Table 7. DV

= 2.7 V to 5.5 V; AV

= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications

MIN

to T

MAX

, unless otherwise noted

Parameter

1, 2

Limit at T

MIN

, T

MAX

Unit

Description

SCL

400

kHz max

SCL clock frequency

2.5

µs min

SCL cycle time

0.6

µs min

HIGH

, SCL high time

1.3

µs min

LOW

, SCL low time

0.6

µs min

HD,STA

, start/repeated start condition hold time

100

ns min

SU,DAT

, data setup time

0.9

µs

max

HD,DAT

, data hold time

µs

min

HD,DAT

, data hold time

0.6

µs min

SU,STA

, setup time for repeated start

0.6

µs min

SU,STO

, stop condition setup time

1.3

µs min

BUF

, bus free time between a STOP and a START condition

300

ns max

, rise time of SCL and SDA when receiving

ns min

, rise time of SCL and SDA when receiving (CMOS compatible)

300

ns max

, fall time of SDA when transmitting

ns min

, fall time of SDA when receiving (CMOS compatible)

300

ns max

, fall time of SCL and SDA when receiving

20 + 0.1C

min

, fall time of SCL and SDA when transmitting

400

pF max

Capacitive load for each bus line

Guaranteed by design and characterization, not production tested.

See Figure 6.

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

min of the SCL signal) in order to bridge the undefined region of

SCL's falling edge.

is the total capacitance, in pF, of one bus line. t

and t

are measured between 0.3 DV

and 0.7 DV

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

SDA

SCL

03731-0-007

Figure 6. I2C Compatible Serial Interface Timing Diagram

AD5382

Rev. 0 | Page 11 of 40

PARALLEL INTERFACE

Table 8. DV

= 2.7 V to 5.5 V; AV

= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications

MIN

to T

MAX

, unless otherwise noted

Parameter

1,2,3

Limit at T

MIN

, T

MAX

Unit

Description

4.5

ns min

REG0, REG1, address to WR rising edge setup time

4.5

ns min

REG0, REG1, address to WR rising edge hold time

ns min

CS pulse width low

ns min

WR pulse width low

ns min

CS to WR falling edge setup time

ns min

WR to CS rising edge hold time

4.5

ns min

Data to WR rising edge setup time

4.5

ns min

Data to WR rising edge hold time

ns min

WR pulse width high

700

ns min

Minimum WR cycle time (single-channel write)

ns max

WR rising edge to BUSY falling edge

4, 5

670

ns max

BUSY pulse width low (single-channel update)

ns min

WR rising edge to LDAC falling edge

ns min

LDAC pulse width low

100

ns max

BUSY rising edge to DAC output response time

ns min

LDAC rising edge to WR rising edge

ns min

BUSY rising edge to LDAC falling edge

100

ns min

LDAC falling edge to DAC output response time

µs typ

DAC output settling time

ns min

CLR pulse width low

µsmax

CLR pulse activation time

Guaranteed by design and characterization, not production tested.

All input signals are specified with t

= t

= 5 ns (10% to 90% of DV

) and timed from a voltage level of 1.2 V.

See Figure 7.

See Figure 29.

Measured with the load circuit of Figure 2.

AD5382

Rev. 0 | Page 13 of 40

ABSOLUTE MAXIMUM RATINGS

Table 9. T

= 25°C, unless otherwise noted

Parameter Rating

to AGND

0.3 V to +7 V

to DGND

0.3 V to +7 V

Digital Inputs to DGND

0.3 V to DV

+ 0.3 V

SDA/SCL to DGND

0.3 V to + 7 V

Digital Outputs to DGND

0.3 V to DV

+ 0.3 V

REFIN/REFOUT to AGND

0.3 V to AV

+ 0.3 V

AGND to DGND

0.3 V to +0.3 V

VOUTx to AGND

0.3 V to AV

+ 0.3 V

Analog Inputs to AGND

0.3 V to AV

+ 0.3 V

MON_IN Inputs to AGND

0.3 V to AV

+ 0.3 V

MON_OUT to AGND

0.3 V to AV

+ 0.3 V

Operating Temperature Range

Commercial (B Version)

40°C to +85°C

Storage Temperature Range

65°C to +150°C

JunctionTemperature (T

Max)

150°C

100-lead LQFP Package

Thermal Impedance

44°C/W

Reflow Soldering

Peak Temperature

230°C

Transient currents of up to 100 mA will not cause SCR latch-up

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

AD5382

Rev. 0 | Page 14 of 40

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESET
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
REG0
REG1
VOUT23
VOUT22
VOUT21
VOUT20
AVDD3
AGND3
DAC_GND3
SIGNAL_GND3
VOUT19
VOUT18
VOUT17
VOUT16
AVDD2
AGND2

VOU

I
N

VOU

DAC_

GND2

I
GNAL_

ND2

VOU

/(S

NC/AD0

)

DB13/(

IN/SDA)

DB1

/
(S

CLK/S

DB11/(

SPI/I2C)

DB1

DB9

DB8

O(A/B)

DGND

SER

/PA

WR (DCE

N/AD1

)

LDAC

BUS

100

24
25

FIFO EN

CLR

VOUT24
VOUT25
VOUT26

VOUT27

SIGNAL_GND4

DAC_GND4

AGND4

AVDD4

VOUT28
VOUT29
VOUT30
VOUT31

REF GND

REFOUT/REFIN

SIGNAL_GND1

DAC_GND1

AVDD1

VOUT0
VOUT1
VOUT2
VOUT3
VOUT4

AGND1

PIN 1

IDENTIFIER

AD5382

TOP VIEW

(Not to Scale)

03733-0-002

Figure 8. 100-Lead LQFP Pin Configuration

Table 10. Pin Function Descriptions

Mnemonic

Function

VOUTx

Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. Each output is capable of driving an output load of 5 k to ground. Typical output impedance is 0.5 .

SIGNAL_GND(14)

Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together
internally and should be connected to the AGND plane as close as possible to the AD5382.

DAC_GND(14)

Each group of eight channels contains a DAC_GND pin. This is the ground reference point for the internal 14-bit
DAC. These pins shound be connected to the AGND plane.

AGND(14)

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be
connected externally to the AGND plane.

AVDD(14)

Analog Supply Pins. Each group of eight channels has a separate AVDD pin. These pins are internally shorted and
should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating range for the
AD5382-5 is 4.5 V to 5.5 V; operating range for the AD5382-3 is 2.7 V to 3.6 V.

DGND

Ground for All Digital Circuitry.

DVDD

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled
with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND.

REFGND

Ground Reference Point for the Internal Reference.

REFOUT/REFIN

The AD5382 contains a common REFOUT/REFIN pin. When the internal reference is selected, this pin is the reference
output. If the application requires an external reference, it can be applied to this pin and the internal reference can
be disabled via the control register. The default for this pin is a reference input.

MON_OUT

When the monitor function is enabled, this pin acts as the output of a 36-to-1 channel multiplexer that can be
programmed to multiplex one of channels 0 to 31 or any of the monitor input pins (MON_IN1 to MON_IN4) to the
MON_OUT pin. The MON_OUT pin's output impedance is typically 500 and is intended to drive a high input
impedance like that exhibited by SAR ADC inputs.

AD5382

Rev. 0 | Page 15 of 40

Mnemonic

Function

MON_INx

Monitor Input Pins. The AD5382 contains four monitor input pins that allow the user to connect input signals, within
the maximum ratings of the device, to these pins for monitoring purposes. Any of the signals applied to the MON_IN
pins along with the 32 output channels can be switched to the MON_OUT pin via software. For example, an external
ADC can be used to monitor these signals.

SER/PAR

Interface Select Input. This pin allows the user to select whether the serial or parallel interface will be used. If it is tied
high, the serial interface mode is selected and Pin 97 (SPI/I2C) is used to determine if the interface mode is SPI or I

Parallel interface mode is selected when SER/PAR is low.

CS/(SYNC/AD0)

In parallel interface mode, this pin acts as the chip select input (level sensitive, active low). When low, the AD5382 is
selected.

In serial interface mode, this is the frame synchronization input signal for the serial clocks before the addressed
register is updated.

In I

C mode, this pin acts as a hardware address pin used in conjunction with AD1 to determine the software address

for the device on the I

C bus.

WR/(DCEN/ AD1)

Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a
daisy-chain enable in SPI mode and as a hardware address pin in I

C mode.

Parallel Interface Write Input (edge sensitive). The rising edge of WR is used in conjunction with CS low and the
address bus inputs to write to the selected device registers.

Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction
with SER/PAR high to enable the SPI serial interface Daisy-Chain mode.

C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address

for this device on the I

C bus.

DB13DB0

Parallel Data Bus. DB13 is the MSB and DB0 is the LSB of the input data-word on the AD5382.

A4A0

Parallel Address Inputs. A4 to A0 are decoded to address one of the AD5382's 40 input channels. Used in conjunction
with the REG1 and REG0 pins to determine the destination register for the input data.

REG1, REG0

In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1
and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and
are also used to decide the special function registers.

SDO/(A/B)

Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a
number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge
of SCLK.

In parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5382's data
registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC is used to
switch the output between the data contained in the A and B data registers. All DAC channels contain two data
registers. In normal mode, Data Register A is the default for data transfers.

BUSY

Digital CMOS Output. BUSY goes low during internal calculations of the data (x2) loaded to the DAC data register.
During this time, the user can continue writing new data to the x1, c, and m registers, but no further updates to the
DAC registers and DAC outputs can take place. If LDAC is taken low while BUSY is low, this event is stored. BUSY also
goes low during power-on reset, and when the RESET pin is low. During this time, the interface is disabled and any
events on LDAC are ignored. A CLR operation also brings BUSY low.

LDAC

Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input
registers are transferred to the DAC registers and the DAC outputs are updated. If LDAC is taken low while BUSY is
active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when
BUSY goes inactive. However any events on LDAC during power-on reset or on RESET are ignored.

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated
with the data contained in the CLR code register. BUSY is low for a duration of 35 µs while all channels are being
updated with the CLR code.

RESET

Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-
on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1,
m, c, and x2 registers to their default power-on values. This sequence takes 270 µs. The falling edge of RESET initiates
the RESET process and BUSY goes low for the duration, returning high when RESET is complete. While BUSY is low,
all interfaces are disabled and all LDAC pulses are ignored. When BUSY returns high, the part resumes normal
operation and the status of the RESET pin is ignored until the next falling edge is detected.

Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode where the device
consumes 2 µA AIDD and 20 µA DIDD. In power-down mode, all internal analog circuitry is placed in low power
mode, and the analog output will be configured as a high impedance output or will provide a 100 k load to
ground, depending on how the power-down mode is configured. The serial interface remains active during power-
down.

AD5382

Rev. 0 | Page 16 of 40

Mnemonic

Function

FIFOEN

FIFO Enable (Level Sensitive, Active High). When connected to DVDD, the internal FIFO is enabled, allowing the user
to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO_EN pin is
sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I

interface modes, the FIFO_EN pin should be tied low.

DB11 (SPI/I2C)

Multifunction Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word. In serial
interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/PAR = 1) and
this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB13 is the serial data
(DIN) input.

When serial interface mode is selected (SER/PAR = 1) and this input is high I

C Mode is selected. In this mode, DB12 is

the serial clock (SCL) input and DB13 is the serial data (SDA) input.

DB12 (SCLK/SCL)

Multifunction Input Pin. In parallel interface mode, this pin acts as DB12 of the parallel input data-word. In serial
interface mode, this pin acts as a serial clock input.

Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This
operates at clock speeds up to 50 MHz.

C Mode. In I

C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I

mode is compatible with both 100 kHz and 400 kHz operating modes.

DB13/(DIN/SDA)

Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB13 of the parallel input data-word.

Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling
edge of SCLK.

C Mode. In I

C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.

No Connect. The user is advised not to connect any signals to these pins.

AD5382

Rev. 0 | Page 17 of 40

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error, and is
expressed in LSB.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register. Ideally, with all 0s loaded to
the DAC and m = all 1s, c = 2

n 1

VOUT

(Zero-Scale)

= 0 V

Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in mV. It is mainly due to
offsets in the output amplifier.

Offset Error

Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) in the linear region of the transfer
function, expressed in mV. Offset error is measured on the
AD5382-5 with Code 32 loaded into the DAC register, and on
the AD5382-3 with Code 64.

Gain Error

Gain Error is specified in the linear region of the output range
between V

OUT

= 10 mV and V

OUT

= AV

50 mV. It is the

deviation in slope of the DAC transfer characteristic from the
ideal and is expressed in %FSR with the DAC output unloaded.

DC Crosstalk

This is the dc change in the output level of one DAC at midscale
in response to a full-scale code (all 0s to all 1s, and vice versa)
and output change of all other DACs. It is expressed in LSB.

DC Output Impedance

This is the effective output source resistance. It is dominated by
package lead resistance.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ј to ѕ full-scale input change,
and is measured from the BUSY rising edge.

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data
between 0x1FFF and 0x2000.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one DAC due to both the digital change and to the
subsequent analog output change at another DAC. The victim
channel is loaded with midscale. DAC-to-DAC crosstalk is
specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter
is defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device's digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.

Output Noise Spectral Density

This is a measure of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
Hertz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/Hz in a
1 Hz bandwidth at 10 kHz.

AD5382

Rev. 0 | Page 18 of 40

TYPICAL PERFORMANCE CHARACTERISTICS

03731-0-033

INPUT CODE

16384

4096

8192

12288

INL E

RROR (LS

)

2.0

1.5

1.0

0.5

1.0

1.5

= DV

= 5.5V

REF

= 2.5V

= 25°C

Figure 9. Typical AD5382-5 INL Plot

03731-0-034

SAMPLE NUMBER

550

100 150 200 250 300

350 400

500

450

AMP

ITUDE

)

2.523

2.539
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524

= DV

= 5V

REF

= 2.5V

= 25°C

14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 10nV-s

Figure 10. AD5382-5 Glitch Impulse

03732-0-003

= DV

= 5V

REF

= 2.5V

= 25°C

OUT

Figure 11. Slew Rate with Boost Off

03731-0-035

INPUT CODE

16384

4096

8192

12288

INL E

RROR (LS

)

2.0

1.5

1.0

0.5

1.0

1.5

= DV

= 3V

REF

= 1.25V

= 25°C

Figure 12. Typical AD5382-3 INL Plot

03731-0-036

SAMPLE NUMBER

550

100 150 200 250 300

350 400

500

450

AMP

ITUDE

)

1.245

1.254

1.253

1.252

1.251

1.250

1.249

1.248

1.247

1.246

= DV

= 3V

REF

= 1.25V

= 25°C

14ns/SAMPLE NUMBER
1 LSB CHANGE AROUND MIDSCALE
GLITCH IMPULSE = 5nV-s

Figure 13. AD5382-3 Glitch Impulse

03732-0-004

= DV

= 5V

REF

= 2.5V

= 25°C

OUT

Figure 14. Slew Rate with Boost On

AD5382

Rev. 0 | Page 19 of 40

04598-0-049

(mA)

RCE

NTAGE

OF UNITS

(%)

= 5.5V

REF

= 2.5V

= 25°C

Figure 15. AI

Histogram

04598-0-050

(mA)

0.8

0.9

0.4

0.5

0.6

0.7

NUMBE

R OF UNITS

= 5.5V

= DV

= DGND

= 25°C

Figure 16. DI

Histogram

03731-0-045

= DV

= 5V

REF

= 2.5V

= 25°C

EXITS SOFT PD
TO MIDSCALE

OUT

BUSY

Figure 17. Exiting Soft Power Down

03731-0-011

= DV

= 5V

REF

= 2.5V

= 25°C

POWER SUPPLY RAMP RATE = 10ms

OUT

Figure 18. AD5382 Power-Up Transient

04598-0-051

INL ERROR DISTRIBUTION (LSB)

NUMBE

R OF UNITS

= 5.5V

REFIN = 2.5V
T

= 25°C

Figure 19. INL Error Distribution

03731-0-038

= DV

= 5V

REF

= 2.5V

= 25°C

EXITS HARDWARE PD

TO MIDSCALE

OUT

Figure 20. Exiting Hardware Power Down

AD5382

Rev. 0 | Page 20 of 40

03731-0-039

CURRENT (mA)

40

20

10

OUT

)

ZEROSCALE

1/4 SCALE

MIDSCALE

3/4 SCALE

FULLSCALE

= DV

= 5V

REF

= 2.5V

= 25°C

Figure 21. AD5382-5 Output Amplifier Source and Sink Capability

03731-0-047

SOURCE

SINK

(mA)

2.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

RROR V

LTAGE

)

0.20

0.10

0.05

0.15

0.05

0.10

0.15

= 5V

REF

= 2.5V

= 25°C

ERROR AT ZERO SINKING CURRENT

OUT

) AT FULL-SCALE SOURCING CURRENT

Figure 22. Headroom at Rails vs. Source/Sink Current

03731-0-047

FREQUENCY (Hz)

100k

100

10k

OUTP

UT NOIS

(nV

/
Hz)

600

500

400

300

200

100

= 5V

= 25°C

REFOUT DECOUPLED
WITH 100nF CAPACITOR

REFOUT = 2.5V

REFOUT = 1.25V

Figure 23 REFOUT Noise Spectral Density

03731-0-040

CURRENT (mA)

40

20

10

40

OUT

)

ZERO-SCALE

1/4 SCALE

MIDSCALE

3/4 SCALE

FULL-SCALE

= DV

= 3V

REF

= 1.25V

= 25°C

Figure 24. AD5382-3 Output Amplifier Source and Sink Capability

03731-0-041

SAMPLE NUMBER

550

100 150 200 250 300

350 400

500

450

AMP

ITUDE

)

2.449

2.456

2.455

2.454

2.453

2.452

2.451

2.450

= DV

= 5V

REF

= 2.5V

= 25°C

14ns/SAMPLE NUMBER

Figure 25. Adjacent Channel DAC-to-DAC Crosstalk

= DV

= 5V

REF

= 2.5V

= 25°C

EXITS SOFT PD

TO MIDSCALE

03731-0-046

= DV

= 5V

= 25°C

DAC LOADED WITH MIDSCALE
EXTERNAL REFERENCE
Y AXIS = 5

V/DIV

X AXIS = 100ms/DIV

Figure 26. 0.1 Hz to 10 Hz Noise Plot

AD5382

Rev. 0 | Page 21 of 40

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE--GENERAL

The AD5382 is a complete, single-supply, 32-channel voltage
output DAC that offers 14-bit resolution. The part is available in
a 100-lead LQFP package and features both a parallel and a
serial interface. This product includes an internal, software
selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to
drive the buffered reference inputs; alternatively, an external
reference can be used to drive these inputs. Internal/external
reference selection is via the CR10 bit in the control register;
CR12 selects the reference magnitude if the internal reference is
selected. All channels have an on-chip output amplifier with
rail-to-rail output capable of driving 5 k in parallel with a
200 pF load.

03731-0-016

OUT

14-BIT

DAC

DAC
REG

m REG

c REG

Ч1 INPUT

REG

Ч2

INPUT DATA

REF

AVDD

Figure 27. Single-Channel Architecture

The architecture of a single DAC channel consists of a 14-bit
resistor-string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 14-bit binary digital code
loaded to the DAC register determines at what node on the
string the voltage is tapped off before being fed to the output
amplifier. Each channel on these devices contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. These registers give the user the ability to
calibrate out errors in the complete signal chain, including the
DAC, using the internal m and c registers, which hold the
correction factors. All channels are double buffered, allowing
synchronous updating of all channels using the LDAC pin.
Figure 27 shows a block diagram of a single channel on the
AD5382. The digital input transfer function for each DAC can
be represented as

x2 = [(m + 2)/ 2

Ч x1] + (c 2

n 1

)

where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 14-bit data-word written to the DAC input register.
m is the gain coefficient (default is 0x3FFE on the AD5382).
The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and LSB (DB0) is a zero.
n = DAC resolution (n = 14 for AD5382).
c is the14-bit offset coefficient (default is 0x2000).

The complete transfer function for these devices can be
represented as

OUT

= 2 Ч V

REF

Ч x2/2

x2 is the data-word loaded to the resistor string DAC. V

REF

is the

internal reference voltage or the reference voltage externally
applied to the DAC REFOUT/REFIN pin. For specified
performance, an external reference voltage of 2.5 V is
recommended for the AD5380-5, and 1.25 V for the AD5380-3.

DATA DECODING

The AD5382 contains a 14-bit data bus, DB13DB0. Depending
on the value of REG1 and REG0 (see Table 11), this data is
loaded into the addressed DAC input registers, offset (c)
registers, or gain (m) registers. The format data, offset (c), and
gain (m) register contents are shown in Table 12 to Table 14.

Table 11. Register Selection

REG1

REG0

Register Selected

Input Data Register (x1)

Offset Register (c)

Gain Register (m)

Special Function Registers (SFRs)

Table 12. DAC Data Format (REG1 = 1, REG0 = 1)

DB13 to DB0

DAC Output (V)

11 1111 1111 1111 2

REF

Ч (16383/16384)

11 1111 1111 1110 2

REF

Ч (16382/16384)

10 0000 0000 0001 2

REF

Ч (8193/16384)

10 0000 0000 0000 2

REF

Ч (8192/16384)

01 1111 1111 1111 2

REF

Ч (8191/16384)

00 0000 0000 0001 2

REF

Ч (1/16384)

00 0000 0000 0000 0

Table 13. Offset Data Format (REG1 = 1, REG0 = 0)

DB13 to DB0

Offset (LSB)

11 1111 1111 1111

+8191

11 1111 1111 1110

+8190

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

00 0000 0000 0001

8191

00 0000 0000 0000

8192

Table 14. Gain Data Format (REG1 = 0, REG0 = 1)

DB13 to DB0

Gain Factor

1111 1111 1110 1

1111 1111 1110 0.75

1111 1111 1110 0.5

0111 1111 1110 0.25

0000 0000 0000 0

AD5382

Rev. 0 | Page 22 of 40

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

The AD5382 contains a number of special function registers
(SFRs), as outlined in Table 15. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using address bits A4 to A0.

Table 15. SFR Register Functions (REG1 = 0, REG0 = 0)

R/W A4 A3 A2 A1 A0 Function

NOP (No Operation)

Write CLR Code

Soft CLR

Soft Power-Down

Soft Power-Up

Control Register Write

Control Register Read

Monitor Channel

Soft Reset

SFR COMMANDS

NOP (No Operation)

REG1 = REG0 = 0, A4A0 = 00000

Performs no operation but is useful in serial readback mode to
clock out data on D

OUT

for diagnostic purposes. BUSY pulses

low during a NOP operation.

Write CLR Code

REG1 = REG0 = 0, A4A0 = 00001
DB13DB0 = Contain the CLR data

Bringing the CLR line low or exercising the soft clear function
will load the contents of the DAC registers with the data con-
tained in the user configurable CLR register, and will set
VOUT0 to VOUT31 accordingly. This can be very useful for
setting up a specific output voltage in a clear condition. It is also
beneficial for calibration purposes; the user can load full scale
or zero scale to the clear code register and then issue a hard-
ware or software clear to load this code to all DACs, removing
the need for individual writes to each DAC. Default on power-
up is all zeros.

Soft CLR

REG1 = REG0 = 0, A4A0 = 00010
DB13DB0 = Don't Care.

Executing this instruction performs the CLR, which is function-
ally the same as that provided by the external CLR pin. The
DAC outputs are loaded with the data in the CLR code register.
It takes 35 µs to fully execute the SOFT CLR and is indicated by
the BUSY low time.

Soft Power-Down

REG1 = REG0 = 0, A4A0 = 01000
DB13DB0 = Don't Care

Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 µA max and the digital
current to 20 µA max. In power-down mode, the output
amplifier can be configured as a high impedance output or
provide a 100 k load to ground. The contents of all internal
registers are retained in power-down mode. No register can be
written to while in power-down.

Soft Power-Up

REG1 = REG0 = 0, A4A0 = 01001
DB13DB0 = Don't Care

This instruction is used to power up the output amplifiers and
the internal reference. The time to exit powerdown is 8 µs. The
hardware power-down and software function are internally
combined in a digital OR function.

Soft RESET

REG1 = REG0 = 0, A4A0 = 01111
DB13DB0 = Don't Care

This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of the
DAC registers are cleared, setting all analog outputs to 0 V. The
soft reset activation time is 135 µs max.

AD5382

Rev. 0 | Page 23 of 40

Table 16. Control Register Contents

MSB

LSB

CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

Control Register Write/Read

REG1 = REG0 = 0, A4A0 = 01100, R/W status determines if
the operation is a write (R/W = 0) or a read (R/W = 1). DB13 to
DB0 contains the control register data.

Control Register Contents

CR13:

Power-Down Status. This bit is used to configure the

output amplifier state in power down.

CR13 = 1. Amplifier output is high impedance (default on
power-up).

CR13 = 0. Amplifier output is 100 k to ground.

CR12:

REF Select. This bit selects the operating internal

reference for the AD5382. CR12 is programmed as follows:

CR12 = 1: Internal reference is 2.5 V (AD5382-5 default), the
recommended operating reference for AD5382-5.

CR12 = 0: Internal reference is 1.25 V (AD5382-3 default),
the recommended operating reference for AD5382-3.

CR11:

Current Boost Control. This bit is used to boost the

current in the output amplifier, thereby altering its slew rate.
This bit is configured as follows:

CR11 = 1: Boost Mode On. This maximizes the bias current
in the output amplifier, optimizing its slew rate but increasing
the power dissipation.

CR11 = 0: Boost Mode Off (default on power-up). This
reduces the bias current in the output amplifier and reduces
the overall power consumption.

CR10:

Internal/External Reference. This bit determines if the

DAC uses its internal reference or an externally applied
reference.

CR10 = 1: Internal Reference Enabled. The reference output
depends on data loaded to CR12.

CR10 = 0: External Reference Selected (default on power up).

CR9:

Channel Monitor Enable (see Channel Monitor Function)

CR9 = 1: Monitor Enabled. This enables the channel monitor
function. After a write to the monitor channel in the SFR
register, the selected channel output is routed to the
MON_OUT pin.

CR9 = 0: Monitor Disabled (default on power-up). When the
monitor is disabled, MON_OUT is three-stated.

CR8:

Thermal Monitor Function. This function is used to

monitor the AD5382's internal die temperature when enabled.
The thermal monitor powers down the output amplifiers when
the temperature exceeds 130°C. This function can be used to
protect the device in cases where power dissipation may be
exceeded if a number of output channels are simultaneously
short-circuited. A soft power-up will re-enable the output
amplifiers if the die temperature has dropped below 130°C.

CR8 = 1: Thermal Monitor Enabled.

CR8 = 0: Thermal Monitor Disabled (default on power- up).

CR7 and CR6:

Don't Care.

CR5 to CR2:

Toggle Function Enable. This function allows the

user to toggle the output between two codes loaded to the A and
B register for each DAC. Control register bits CR5 to CR2 are
used to enable individual groups of eight channels for opera-
tion in toggle mode. A Logic 1 written to any bit enables a group
of channels; a Logic 0 disables a group. LDAC is used to toggle
between the two registers. Table 17 shows the decoding for
toggle mode operation. For example, CR5 controls group 3,
which contains channels 24 to 31, CR5 = 1 enables these
channels .

CR1 and CR0:

Don't Care.

Table 17.

CR Bit

Group

Channels

CR5 3

2431

CR4 2

1623

CR3 1

815

CR2 0

Channel Monitor Function

REG1 = REG0 = 0, A4A0 = 01010

DB13DB8 = Contain data to address the monitored channel.

A channel monitor function is provided on the AD5382. This
feature, which consists of a multiplexer addressed via the
interface, allows any channel output or the signals connected to
the MON_IN inputs to be routed to the MON_OUT pin for
monitoring using an external ADC. The channel monitor
function must be enabled in the control register before any
channels are routed to MON_OUT. On the AD5382, DB13 to
DB8 contain the channel address for the monitored channel.
Selecting channel address 63 three-states MON_OUT.

AD5382

Rev. 0 | Page 24 of 40

Table 18. AD5382 Channel Monitor Decoding

REG1 REG0 A4 A3 A2 A1 A0 DB13 DB12 DB11 DB10 DB9 DB8 DB7DB0 MON_OUT

0 1 0 1 0 0

0 0 X

VOUT0

0 1 0 1 0 0

0 1 X

VOUT1

0 1 0 1 0 0

1 0 X

VOUT2

0 1 0 1 0 0

1 1 X

VOUT3

0 1 0 1 0 0

0 0 X

VOUT4

0 1 0 1 0 0

0 1 X

VOUT5

0 1 0 1 0 0

1 0 X

VOUT6

0 1 0 1 0 0

1 1 X

VOUT7

0 1 0 1 0 0

0 0 X

VOUT8

0 1 0 1 0 0

0 1 X

VOUT9

0 1 0 1 0 0

1 0 X

VOUT10

0 1 0 1 0 0

1 1 X

VOUT11

0 1 0 1 0 0

0 0 X

VOUT12

0 1 0 1 0 0

0 1 X

VOUT13

0 1 0 1 0 0

1 0 X

VOUT14

0 1 0 1 0 0

1 1 X

VOUT15

0 1 0 1 0 0

0 0 X

VOUT16

0 1 0 1 0 0

0 1 X

VOUT17

0 1 0 1 0 0

1 0 X

VOUT18

0 1 0 1 0 0

1 1 X

VOUT19

0 1 0 1 0 0

0 0 X

VOUT20

0 1 0 1 0 0

0 1 X

VOUT21

0 1 0 1 0 0

1 0 X

VOUT22

0 1 0 1 0 0

1 1 X

VOUT23

0 1 0 1 0 0

0 0 X

VOUT24

0 1 0 1 0 0

0 1 X

VOUT25

0 1 0 1 0 0

1 0 X

VOUT26

0 1 0 1 0 0

1 1 X

VOUT27

0 1 0 1 0 0

0 0 X

VOUT28

0 1 0 1 0 0

0 1 X

VOUT29

0 1 0 1 0 0

1 0 X

VOUT30

0 1 0 1 0 0

1 1 X

VOUT31

0 1 0 1 0 1

0 0 X

MON_IN1

0 1 0 1 0 1

0 1 X

MON_IN2

0 1 0 1 0 1

1 0 X

MON_IN3

0 1 0 0 1

1 1 X

MON_IN4

0 1 0 1 0 1

0 0 X

Undefined

0 1 0 1 0 1

0 1 X

Undefined

· ·

0 1 0 1 0 1

1 0 X

Undefined

0 1 0 1 0 1

1 1 X

Three-State

03733-0-003

DB13DB8

CHANNEL ADDRESS

AD5382

CHANNEL

MONITOR

DECODING

0 0 0 1 0 1 0

VOUT0
VOUT1

VOUT31

VOUT30

MON_OUT

REG1 REG0 A4 A3 A2 A1 A0

MON_IN1
MON_IN2
MON_IN3
MON_IN4

Figure 28. Channel Monitor Decoding

AD5382

Rev. 0 | Page 25 of 40

HARDWARE FUNCTIONS

RESET FUNCTION

Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. Reset is a negative edge-
sensitive input. The default corresponds to m at full scale and to
c at zero. The contents of the DAC registers are cleared, setting
VOUT 0 to VOUT 31 to 0 V. This sequence takes 270 µs max.
The falling edge of RESET initiates the reset process; BUSY goes
low for the duration, returning high when RESET is complete.
While BUSY is low, all interfaces are disabled and all LDAC
pulses are ignored. When BUSY returns high, the part resumes
normal operation and the status of the RESET pin is ignored
until the next falling edge is detected.

ASYNCHRONOUS CLEAR FUNCTION

Bringing the CLR line low clears the contents of the DAC
registers to the data contained in the user configurable CLR
register and sets VOUT 0 to VOUT 31 accordingly. This func-
tion can be used in system calibration to load zero scale and full
scale to all channels. The execution time for a CLR is 35 µs.

BUSY AND LDAC FUNCTIONS

BUSY is a digital CMOS output that indicates the status of the
AD5382. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m registers. During the calculation
of x2, the BUSY output goes low. While BUSY is low, the user
can continue writing new data to the x1, m, or c registers, but no
DAC output updates can take place. The DAC outputs are
updated by taking the LDAC input low. If LDAC goes low while
BUSY is active, the LDAC event is stored and the DAC outputs
update immediately after BUSY goes high. The user may hold
the LDAC input permanently low, in which case the DAC
outputs update immediately after BUSY goes high. BUSY also
goes low during power-on reset and when a falling edge is
detected on the RESET pin. During this time, all interfaces are
disabled and any events on LDAC are ignored. The AD5382
contains an extra feature whereby a DAC register is not updated
unless its x2 register has been written to since the last time
LDAC was brought low. Normally, when LDAC is brought low,
the DAC registers are filled with the contents of the x2 registers.
However, the AD5382 will only update the DAC register if the
x2 data has changed, thereby removing unnecessary digital
crosstalk.

FIFO OPERATION IN PARALLEL MODE

The AD5382 contains a FIFO to optimize operation when
operating in parallel interface mode. The FIFO Enable (level
sensitive, active high) is used to enable the internal FIFO. When
connected to DVDD, the internal FIFO is enabled, allowing the
user to write to the device at full speed. FIFO is only available in
parallel interface mode. The status of the FIFO_EN pin is
sampled on power-up, and after a CLEAR or RESET, to
determine if the FIFO is enabled. In either serial or I

C interface

modes, FIFO_EN should be tied low. Up to 128 successive
instructions can be written to the FIFO at maximum speed in
parallel mode. When the FIFO is full, any further writes to the
device are ignored. Figure 29 shows a comparison between
FIFO mode and non-FIFO mode in terms of channel update
time. Figure 29 also outlines digital loading time.

NUMBER OF WRITES

TIME (

WITHOUT FIFO

(CHANNEL UPDATE TIME)

WITH FIFO

(CHANNEL UPDATE TIME)

WITH FIFO

(DIGITAL LOADING TIME)

03731-0-018

Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)

POWER-ON RESET

The AD5382 contains a power-on reset generator and state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance. The
BUSY pin goes low during the power-on reset sequencing,
preventing data writes to the device.

POWER-DOWN

The AD5382 contains a global power-down feature that puts all
channels into a low power mode and reduces the analog power
consumption to 2 µA max and digital power consumption to
20 µA max. In power-down mode, the output amplifier can be
configured as a high impedance output or provide a 100 k
load to ground. The contents of all internal registers are
retained in power-down mode. When exiting power-down, the
settling time of the amplifier will elapse before the outputs settle
to their correct values.

AD5382

Rev. 0 | Page 26 of 40

AD5382 INTERFACES

The AD5382 contains both parallel and serial interfaces.
Furthermore, the serial interface can be programmed to be
either SPI, DSP, MICROWIRE, or I

C compatible. The SER/PAR

pin selects parallel and serial interface modes. In serial mode,
the SPI/I2C pin is used to select DSP, SPI, MICROWIRE, or I

interface mode.

The devices use an internal FIFO memory to allow high speed
successive writes in parallel interface mode. The user can con-
tinue writing new data to the device while write instructions are
being executed. The BUSY signal indicates the current status of
the device, going low while instructions in the FIFO are being
executed. In parallel mode, up to 128 successive instructions can
be written to the FIFO at maximum speed. When the FIFO is
full, any further writes to the device are ignored.

To minimize both the power consumption of the device and the
on-chip digital noise, the active interface only powers up fully
when the device is being written to, i.e., on the falling edge of
WR or the falling edge of SYNC.

DSP, SPI, MICROWIRE COMPATIBLE SERIAL
INTERFACES

The serial interface can be operated with a minimum of three
wires in standalone mode or four wires in daisy-chain mode.
Daisy chaining allows many devices to be cascaded together to
increase system channel count. The SER/PAR pin must be tied
high and the SPI/I2C pin (Pin 97) should be tied low to enable
the DSP/SPI/MICROWIRE compatible serial interface. In serial
interface mode, the user does not need to drive the parallel
input data pins. The serial interface's control pins are

SYNC, DIN, SCLK--Standard 3-Wire Interface Pins.
DCEN

--Selects Standalone Mode or Daisy-Chain Mode.

SDO

--Data Out Pin for Daisy-Chain Mode.

Figure 3 and Figure 5 show timing diagrams for a serial write to
the AD5382 in standalone and daisy-chain modes. The 24-bit
data-word format for the serial interface is shown in Table 19

A/B. When toggle mode is enabled, this pin selects whether the
data write is to the A or B register. With toggle disabled, this bit
should be set to zero to select the A data register.

R/W is the read or write control bit.

A4A0

are used to address the input channels.

REG1 and REG0

select the register to which data is written, as

shown in Table 11.

DB13DB0

contain the input data-word.

is a don't care condition.

Standalone Mode

By connecting the DCEN (Daisy-Chain Enable) pin low, stand-
alone mode is enabled. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC starts the write cycle and resets a counter that
counts the number of serial clocks to ensure that the correct
number of bits are shifted into the serial shift register. Any
further edges on SYNC except for a falling edge are ignored
until 24 bits are clocked in. Once 24 bits have been shifted in,
the SCLK is ignored. In order for another serial transfer to take
place, the counter must be reset by the falling edge of SYNC.

Table 19. 32-Channel, 14-Bit DAC Serial Input Register Configuration

MSB

LSB

A/B R/W

0 A4 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

AD5382

Rev. 0 | Page 27 of 40

Daisy-Chain Mode

For systems that contain several devices, the SDO pin may be
used to daisy-chain several devices together. This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface lines.

By connecting the DCEN (Daisy-Chain Enable) pin high, daisy-
chain mode is enabled. The first falling edge of SYNC starts the
write cycle. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 24 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting the SDO of
the first device to the DIN input on the next device in the chain,
a multidevice interface is constructed. Twenty-four clock pulses
are required for each device in the system. Therefore, the total
number of clock cycles must equal 24N, where N is the total
number of AD538x devices in the chain.

When the serial transfer to all devices is complete, SYNC is
taken high. This latches the input data in each device in the
daisy-chain and prevents any further data from being clocked
into the input shift register.

If the SYNC is taken high before 24 clocks are clocked into the
part, this is considered a bad frame and the data is discarded.

The serial clock may be either a continuous or a gated clock. A
continuous SCLK source can only be used if it can be arranged
that SYNC is held low for the correct number of clock cycles. In
gated clock mode, a burst clock containing the exact number of
clock cycles must be used and SYNC must be taken high after
the final clock to latch the data.

Readback Mode

Readback mode is invoked by setting the R/W bit = 1 in the
serial input register write. With R/W = 1, Bits A4 to A0, in
association with Bits REG1 and REG0, select the register to be
read. The remaining data bits in the write sequence are don't
cares. During the next SPI write, the data appearing on the SDO
output will contain the data from the previously addressed
register. For a read of a single register, the NOP command can
be used in clocking out the data from the selected register on
SDO. Figure 30 shows the readback sequence. For example, to
read back the M register of channel 0 on the AD5382, the
following sequence should be implemented. First, write
0x404XXX to the AD5382 input register. This configures the
AD5382 for read mode with the m register of Channel 0
selected. Note that data bits DB13 to DB0 are don't cares. Follow
this with a second write, a NOP condition, 0x000000. During
this write, the data from the m register is clocked out on the
DOUT line, i.e., data clocked out will contain the data from the
m register in Bits DB13 to DB0, and the top 10 bits contain the
address information as previously written. In readback mode,
the SYNC signal must frame the data. Data is clocked out on the
rising edge of SCLK and is valid on the falling edge of the SCLK
signal. If the SCLK idles high between the write and read
operations of a readback operation, the first bit of data is
clocked out on the falling edge of SYNC.

03731-0-019

SCLK

SYNC

DIN

SDO

UNDEFINED

SELECTED REGISTER DATA CLOCKED OUT

NOP CONDITION

INPUT WORD SPECIFIES REGISTER TO BE READ

DB23

DB0

DB23

DB0

DB23

Figure 30. Serial Readback Operation

AD5382

Rev. 0 | Page 28 of 40

C SERIAL INTERFACE

The AD5382 features an I

C compatible 2-wire interface

consisting of a serial data line (SDA) and a serial clock line
(SCL). SDA and SCL facilitate communication between the
AD5382 and the master at rates up to 400 kHz. Figure 6 shows
the 2-wire interface timing diagrams that incorporate three
different modes of operation. In selecting the I

C operating

mode, first configure serial operating mode (SER/PAR = 1) and
then select I

C mode by configuring the SPI/I2C pin to a

Logic 1. The device is connected to the I

C bus as a slave device

(i.e., no clock is generated by the AD5382). The AD5382 has a
7-bit slave address 1010 1AD1AD0. The 5 MSB are hard-coded
and the 2 LSB are determined by the state of the AD1 and AD0
pins. The facility to hardware configure AD1 and AD0 allows
four of these devices to be configured on the bus.

C Data Transfer

One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals that configure START and STOP conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I

C bus is not busy.

START and STOP Conditions

A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high. A START condition from
the master signals the beginning of a transmission to the
AD5382. The STOP condition frees the bus. If a repeated
START condition (Sr) is generated instead of a STOP condition,
the bus remains active.

Repeated START Conditions

A repeated START (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I

C devices and wants to maintain control of

the bus.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. ACK is always generated by the receiving
device. The AD5382 devices generate an ACK when receiving
an address or data by pulling SDA low during the ninth clock
period. Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs if a
receiving device is busy or if a system fault has occurred. In the
event of an unsuccessful data transfer, the bus master should
reattempt communication.

AD5382 Slave Addresses

A bus master initiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD5382 waits for a START condition followed
by its slave address. The LSB of the address word is the Read/
Write (R/W) bit. The AD5382 is a receive only device; when
communicating with the AD5382, R/W = 0. After receiving the
proper address 1010 1AD1AD0 , the AD5382 issues an ACK by
pulling SDA low for one clock cycle.

The AD5382 has four different user programmable addresses
determined by the AD1 and AD0 bits.

Write Operation

There are three specific modes in which data can be written to
the AD5382 DAC.

4-Byte Mode

When writing to the AD5382 DACs, the user must begin with
an address byte (R/W = 0) after which the DAC will acknowl-
edge that it is prepared to receive data by pulling SDA low. The
address byte is followed by the pointer byte; this addresses the
specific channel in the DAC to be addressed and is also
acknowledged by the DAC. Two bytes of data are then written
to the DAC, as shown in Figure 31. A STOP condition follows.
This allows the user to update a single channel within the
AD5382 at any time and requires four bytes of data to be
transferred from the master.

3-Byte Mode

In 3-byte mode, the user can update more than one channel in a
write sequence without having to write the device address byte
each time. The device address byte is only required once; sub-
sequent channel updates require the pointer byte and the data
bytes. In 3-byte mode, the user begins with an address byte
(R/W = 0), after which the DAC will acknowledge that it is
prepared to receive data by pulling SDA low. The address byte is
followed by the pointer byte. This addresses the specific channel
in the DAC to be addressed and is also acknowledged by the
DAC. This is then followed by the two data bytes. REG1 and
REG0 determine the register to be updated.

If a STOP condition does not follow the data bytes, another
channel can be updated by sending a new pointer byte followed
by the data bytes. This mode only requires three bytes to be sent
to update any channel once the device has been initially
addressed, and reduces the software overhead in updating the
AD5382 channels. A STOP condition at any time exits this
mode. Figure 32 shows a typical configuration.

AD5382

Rev. 0 | Page 29 of 40

AD1

AD0

R/W

SCL

SDA

SCL

SDA

START COND

BY MASTER

ACK BY

AD538x

ACK BY

AD538x

ADDRESS BYTE

MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

POINTER BYTE

MSB

ACK BY

AD538x

ACK BY

AD538x

STOP
COND

MASTER

REG1

REG0

MSB

LSB

MSB

LSB

03731-0-020

Figure 31. 4-Byte AD5382, I

C Write Operation

03731-0-021

SCL

SDA

SCL

SDA

SCL

SDA

SCL

START COND

BY MASTER

ACK BY

AD538x

MSB

ADDRESS BYTE

POINTER BYTE FOR CHANNEL "N"

MOST SIGNIFICANT DATA BYTE

POINTER BYTE FOR CHANNEL "NEXT CHANNEL"

LEAST SIGNIFICANT DATA BYTE

MOST SIGNIFICANT DATA BYTE

LEAST SIGNIFICANT DATA BYTE

ACK BY

AD538x

ACK BY

AD538x

DATA FOR CHANNEL "N"

DATA FOR CHANNEL "NEXT CHANNEL"

ACK BY

AD538x

AD1

AD0

R/W

REG1

REG0

MSB

LSB

MSB

LSB

MSB

ACK BY

AD538x

ACK BY

AD538x

ACK BY

AD538x

STOP COND
BY MASTER

REG1

REG0

MSB

LSB

MSB

LSB

Figure 32. 3-Byte AD5382, I

C Write Operation

AD5382

Rev. 0 | Page 30 of 40

2-Byte Mode

Following initialization of 2-byte mode, the user can update
channels sequentially. The device address byte is only required
once and the pointer address pointer is configured for auto-
increment or burst mode.

The user must begin with an address byte (R/W = 0), after
which the DAC will acknowledge that it is prepared to receive
data by pulling SDA low. The address byte is followed by a
specific pointer byte (0xFF) that initiates the burst mode of
operation. The address pointer initializes to channel zero, the
data following the pointer is loaded to Channel 0, and the
address pointer automatically increments to the next address.

The REG0 and REG1 bits in the data byte determine which
register will be updated. In this mode, following the initializa-
tion, only the two data bytes are required to update a channel.
The channel address automatically increments from Address 0
to Channel 31 and then returns to the normal 3-byte mode of
operation. This mode allows transmission of data to all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode is not supported in 2-byte mode.
Figure 33 shows a typical configuration.

PARALLEL INTERFACE

The SER/PAR pin must be tied low to enable the parallel
interface and disable the serial interfaces. Figure 7 shows the
timing diagram for a parallel write. The parallel interface is
controlled by the following pins:

CS Pin

Active Low Device Select Pin.

WR Pin

On the rising edge of WR, with CS low, the addresses on Pins
A4 to A0 are latched; data present on the data bus is loaded into
the selected input registers.

REG0, REG1 Pins

The REG0 and REG1 pins determine the destination register of
the data being written to the AD5382. See Table 11.

Pins A4 to A0

Each of the 40 DAC channels can be addressed individually.

Pins DB13 to DB0

The AD5382 accepts a straight 14-bit parallel word on DB13 to
DB0, where DB13 is the MSB and DB0 is the LSB.

AD1

AD0

R/W

A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1

START COND

BY MASTER

ADDRESS BYTE

POINTER BYTE

MOST SIGNIFICANT DATA BYTE

CHANNEL 0 DATA

LEAST SIGNIFICANT DATA BYTE

ACK BY

CONVERTER

MSB

ACK BY

CONVERTER

ACK BY

AD538x

ACK BY

AD538x

MOST SIGNIFICANT DATA BYTE

CHANNEL 1 DATA

LEAST SIGNIFICANT DATA BYTE

ACK BY

CONVERTER

ACK BY

CONVERTER

MOST SIGNIFICANT DATA BYTE

CHANNEL N DATA FOLLOWED BY STOP

LEAST SIGNIFICANT DATA BYTE

ACK BY

CONVERTER

ACK BY

CONVERTER

STOP

COND

MASTER

REG1

REG0

MSB

LSB

MSB

LSB

REG1

REG0

MSB

LSB

MSB

LSB

REG1

REG0

MSB

LSB

MSB

LSB

SCL

SDA

SCL

SDA

SCL

SDA

SCL

SDA

03731-0-022

Figure 33. 2-Byte, I

C Write Operation

AD5382

Rev. 0 | Page 31 of 40

MICROPROCESSOR INTERFACING

Parallel Interface

The AD5382 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure 35 shows the AD5382 family
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to
A0A4 on the AD5382. The upper address lines are decoded to
provide a CS, LDAC signal for the AD5382. The fast interface
timing of the AD5382 allows direct interface to a wide variety of
microcontrollers and DSPs, as shown in Figure 35.

AD5382 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity bit
(CPOL) = 0, and the Clock Phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)--see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5382, the MOSI output drives the serial data line (D

)

of the AD5382, and the MISO input is driven from D

OUT

. The

SYNC signal is derived from a port line (PC7). When data is

being transmitted to the AD5382, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle.

03733-0-004

MC68HC11

AD5382

MISO
MOSI

SCK

PC7

SDO

RESET

SER/PAR

DIN
SCLK
SYNC
SPI/I2C

Figure 34. AD5382-to-MC68HC11 Interface

03733-0-005

CONTROLLER/

DSP PROCESSOR*

AD5382

ADDRESS

DECODE

UPPER BITS OF

ADDRESS BUS

DATA

BUS

D15

A4
A3
A2
A1
A0

R/W

A4
A3
A2
A1
A0
WR

REG1
REG0
D13

D0
CS
LDAC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 35. AD5382-to-Parallel Interface

AD5382

Rev. 0 | Page 32 of 40

AD5382 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity bit = 0. This is done by
writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example I/O, port RA1 is being used to pulse SYNC and
enable the serial port of the AD5382. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive read/write operations
may be needed depending on the mode. Figure 36 shows the
connection diagram.

03733-0-006

PIC16C6X/7X

AD5382

SDI/RC4

SDO/RC5

SCK/RC3

RA1

SDO

RESET

SER/PAR

DIN
SCLK
SYNC
SPI/I2C

Figure 36. AD5382-to-PIC16C6x/7x Interface

AD5382 to 8051

The AD5382 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 37 shows how the 8051 is
connected to the AD5382. Because the AD5382 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5382
requires its data to be MSB first. Since the 8051 outputs the LSB
first, the transmit routine must take this into account.

03733-0-007

8XC51

AD5382

RxD

TxD

P1.1

SDO

RESET

SER/PAR

DIN
SCLK
SYNC
SPI/I2C

Figure 37. AD5382-to-8051 Interface

AD5382 to ADSP-2101/ADSP-2103

Figure 38 shows a serial interface between the AD5382 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT has been enabled.

03733-0-008

ADSP-2101/

ADSP-2103

AD5382

SCK

TFS

RFS

SDO

RESET

SER/PAR

DIN
SCLK

SPI/I2C

SYNC

Figure 38. AD5382-to-ADSP-2101/ADSP-2103 Interface

AD5382

Rev. 0 | Page 33 of 40

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5382 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5382 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only, a star ground
point established as close to the device as possible.

For supplies with multiple pins (AV

, DV

), these pins should

be tied together. The AD5382 should have ample supply bypass-
ing of 10 µF in parallel with 0.1 µF on each supply, located as
close to the package as possible and ideally right up against the
device. The 10 µF capacitors are the tantalum bead type. The
0.1 µF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.

The power supply lines of the AD5382 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the D

and SCLK lines will help reduce crosstalk

between them (this is not required on a multilayer board
because there will be a separate ground plane, but separating the
lines will help). It is essential to minimize noise on the V

and

REFIN lines.

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best, but is not always possible with
a double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the solder side.

TYPICAL CONFIGURATION CIRCUIT

Figure 39 shows a typical configuration for the AD5382-5 when
configured for use with an external reference. In the circuit
shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied
together to a common AGND. AGND and DGND are
connected together at the AD5382 device. On power-up, the
AD5382 defaults to external reference operation. All AV

lines

are connected together and driven from the same 5 V source. It
is recommended to decouple close to the device with a 0.1 µF
ceramic and a 10 µF tantalum capacitor. In this application, the
reference for the AD5382-5 is provided externally from either

an ADR421 or ADR431 2.5 V reference. Suitable external
references for the AD5382-3 include the ADR280 1.2 V
reference. The reference should be decoupled at the
REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

03733-0-009

ADR431/

ADR421

AD5382-5

AVDD

DVDD

SIGNAL

GND

DAC
GND

DGND

VOUT31

VOUT0

AGND

REFOUT/REFIN

REFGND

0.1

AVDD

DVDD

Figure 39. Typical Configuration with External Reference

Figure 40 shows a typical configuration when using the internal
reference. On power-up, the AD5382 defaults to an external
reference; therefore, the internal reference needs to be
configured and turned on via a write to the AD5382 control
register. Control Register Bit CR12 allows the user choose the
reference value; Bit CR 10 is used to select the internal
reference. It is recommended to use the 2.5 V reference when
AV

= 5 V, and the 1.25 V reference when AV

= 3 V.

03733-0-010

AD5382

AVDD

DVDD

SIGNAL

GND

DAC
GND

DGND

VOUT31

VOUT0

AGND

REFOUT/REFIN

REFGND

0.1

AVDD

DVDD

Figure 40. Typical Configuration with Internal Reference

Digital connections have been omitted for clarity. The AD5382
contains an internal power- on reset circuit with a 10 ms
brownout time. If the power supply ramp rate exceeds 10 ms,
the user should reset the AD5382 as part of the initialization
process to ensure the calibration data gets loaded correctly into
the device.

AD5382

Rev. 0 | Page 34 of 40

AD5382 MONITOR FUNCTION

The AD5382 contains a channel monitor function that consists
of a multiplexer addressed via the interface, allowing any chan-
nel output to be routed to this pin for monitoring using an
external ADC. The channel monitor function must be enabled
in the control register before any channels are routed to
MON_OUT. Table 18 contains the decoding information
required to route any channel to MON_OUT. External signals
within the AD5382's absolute max input range can be connected
to the MON_IN pins and monitored at MON_OUT. Selecting
Channel Address 63 three-states MON_OUT. Figure 41 shows a
typical monitoring circuit implemented using a 12-bit SAR
ADC in a 6-lead SOT-23 package. The controller output port
selects the channel to be monitored, and the input port reads
the converted data from the ADC.

TOGGLE MODE FUNCTION

The toggle mode function allows an output signal to be gener-
ated using the LDAC control signal that switches between two
DAC data registers. This function is configured using the SFR
control register as follows. A write with REG1 = REG0 = 0 and
A4A0 = 01100 specifies a control register write. The toggle
mode function is enabled in groups of eight channels using bits
CR5 to CR2 in the control register. See the AD5382 control
register description. Figure 42 shows a block diagram of toggle
mode implementation. Each of the 32 DAC channels on the
AD5382 contain an A and B data register. Note that the B
registers can only be loaded when toggle mode is enabled. The

sequence of events when configuring the AD5382 for toggle
mode is

Enable toggle mode for the required channels via the
control register.

Load data to A registers.

Load data to B registers.

Apply LDAC.

The LDAC is used to switch between the A and B registers in
determining the analog output. The first LDAC configures the
output to reflect the data in the A registers. This mode offers
significant advantages if the user wants to generate a square
wave at the output of all 32 channels, as might be required to
drive a liquid crystal based variable optical attenuator. In this
case, the user writes to the control register and enables the
toggle function by setting CR5 to CR2 = 1, thus enabling the
four groups of eight for toggle mode operation. The user must
then load data to all 32 A and B registers. Toggling LDAC will
set the output values to reflect the data in the A and B registers.
The frequency of the LDAC determines the frequency of the
square wave output.

Toggle mode is disabled via the control register. The first LDAC
following the disabling of the toggle mode will update the
outputs with the data contained in the A registers.

AD7476

GND

SDATA

SCLK

AVCC

MON_OUT

AGND

DIN

SYNC

SCLK

DAC_GND SIGNAL_GND

VOUT0

VOUT31

AVCC

AD5382

OUTPUT PORT

INPUT PORT

CONTROLLER

03733-0-011

AD780/

ADR431

REFOUT/REFIN

MON_IN1

MON_IN2

AVCC

Figure 41. Typical Channel Monitoring Circuit

AD5382

Rev. 0 | Page 35 of 40

14-BIT DAC

DAC

REGISTER

INPUT

DATA

INPUT

REGISTER

DATA

REGISTER

DATA

REGISTER

A/B

OUT

LDAC
CONTROL INPUT

03731-0-029

Figure 42. Toggle Mode Function

ACTUATORS

FOR MEMS

MIRROR

ARRAY

SENSOR

AND

MULTIPLEXER

8-CHANNEL ADC

(AD7856)

SINGLE CHANNEL

ADC (AD7671)

AD5382

14-BIT DAC

REF

OUT

REF

AVDD

VO1

VO31

G = 50

OUTPUT RANGE

0200V

ADSP-21065L

0.01

03733-0-012

+5V

Figure 43. AD5382 in a MEMS Based Optical Switch

THERMAL MONITOR FUNCTION

The AD5382 contains a temperature shutdown function to
protect the chip in case multiple outputs are shorted. The short
circuit current of each output amplifier is typically 40 mA.
Operating the AD5382 at 5 V leads to a power dissipation of
200 mW per shorted amplifier. With five channels shorted, this
leads to an extra watt of power dissipation. For the 100-lead
LQFP, the

is typically 44°C/W.

The thermal monitor is enabled by the user via CR8 in the
control register. The output amplifiers on the AD5382 are
automatically powered down if the die temperature exceeds
approximately 130°C. After a thermal shutdown has occurred,
the user can re-enable the part by executing a soft power-up if
the temperature has dropped below 130°C or by turning off the
thermal monitor function via the control register.

AD5382 IN A MEMS BASED OPTICAL SWITCH

In their feed-forward control paths, MEMS based optical
switches require high resolution DACs that offer high channel
density with 14-bit monotonic behavior. The 32-channel, 14-bit
AD5382 DAC satisfies these requirements. In the circuit in
Figure 43, the 0 V to 5 V outputs of the AD5382 are amplified to
achieve an output range of 0 V to 200 V, which is used to control
actuators that determine the position of MEMS mirrors in an
optical switch. The exact position of each mirror is measured
using sensors. The sensor outputs are multiplexed into a high
resolution ADC in determining the mirror position. The control
loop is closed and driven by an ADSP-21065L, a 32-bit SHARC®
DSP with an SPI compatible SPORT interface. The ADSP-
21065L writes data to the DAC, controls the multiplexer, and
reads data from the ADC via the serial interface.

AD5382

Rev. 0 | Page 36 of 40

OPTICAL ATTENUATORS

Based on its high channel count, high resolution, monotonic
behavior, and high level of integration, the AD5382 is ideally
targeted at optical attenuation applications used in dynamic
gain equalizers, variable optical attenuators (VOA), and optical
add-drop multiplexers (OADM). In these applications, each
wavelength is individually extracted using an arrayed wave

guide; its power is monitored using a photodiode, transimped-
ance amplifier and ADC in a closed-loop control system. The
AD5382 controls the optical attenuator for each wavelength,
ensuring that the power is equalized in all wavelengths before
being multiplexed onto the fiber. This prevents information loss
and saturation from occurring at amplification stages further
along the fiber.

ATTENUATOR

AWG

FIBRE

DWDM

OUT

OPTICAL

SWITCH

1n1

DWDM

AD5382,

32-CHANNEL,

14-BIT DAC

N:1 MULTIPLEXER

16-BIT ADC

CONTROLLER

TIA/LOG AMP
(AD8304/AD8305)

ADG731
(32:1 MUX)

AD7671
(0-5V, 1MSPS)

PHOTODIODES

ADD

PORTS

DROP

PORTS

03733-0-013

Figure 44. OADM Using the AD5382 as Part of an Optical Attenuator

AD5382

Rev. 0 | Page 37 of 40

OUTLINE DIMENSIONS

TOP VIEW

(PINS DOWN)

100

14.00 BSC SQ

0.50 BSC

0.27
0.22
0.17

1.60 MAX

SEATING

PLANE

12°

TYP

0.75
0.60
0.45

VIEW A

16.00 BSC SQ

12.00

REF

0.20
0.09

1.45
1.40
1.35

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING

PLANE

10°

6°
2°

7°

3.5°

0°

0.15
0.05

PIN 1

COMPLIANT TO JEDEC STANDARDS MS-026BED

Figure 45. 100-Lead Leaded Quad Flatpack [LQFP]

(ST-100)

Dimensions shown in millimeters

ORDERING GUIDE

Model Resolution

Temperature

Range

Output
Channels

Linearity
Error

Package
Description

Package
Option

AD5382BST-3

14 Bits

40°C to +85°C

2.7 V to 3.6 V

±4 LSB

100-Lead LQFP

ST-100

AD5382BST-3-REEL

14 Bits

40°C to +85°C

2.7 V to 3.6 V

±4 LSB

100-Lead LQFP

ST-100

AD5382BST-5

14 Bits

40°C to +85°C

4.5 V to 5.5 V

±4 LSB

100-Lead LQFP

ST-100

AD5382BST-5-REEL

14 Bits

40°C to +85°C

4.5 V to 5.5 V

±4 LSB

100-Lead LQFP

ST-100

EVAL-AD5382EB

Evaluation

Kit

РР»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: AD5392BST-3

Document Outline

Р­Р»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: AD5392BST-3

Document Outline

РР»РµРєС‚СЂРѕРЅРЅС‹Р№ РєРѕРјРїРѕРЅРµРЅС‚: AD5392BST-3