AD5541/AD5542 Data Sheet
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5541/AD5542
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
5 V, Serial-Input
Voltage-Output, 16-Bit DACs
FUNCTIONAL BLOCK DIAGRAMS
SERIAL
INPUT
REGISTER
REF
CS
DIN
SCLK
AGND
V
OUT
V
DD
DGND
AD5541
16-BIT
DAC
16-BIT
DATA
LATCH
CONTROL
LOGIC
SERIAL
INPUT
REGISTER
REFF
CS
DIN
SCLK
AGNDF
V
OUT
V
DD
DGND
AD5542
16-BIT
DAC
16-BIT
DATA
LATCH
CONTROL
LOGIC
REFS
LDAC
AGNDS
RFB
INV
R
FB
R
INV
FEATURES
Full 16-Bit Performance
5 V Single Supply Operation
Low Power
Short Settling Time
Unbuffered Voltage Output Capable of Driving 60 k
Loads Directly
SPITM/QSPITM/MICROWIRETM-Compatible Interface
Standards
Power-On Reset Clears DAC Output to 0 V (Unipolar
Mode)
Schmitt Trigger Inputs for Direct Optocoupler Interface
APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control
GENERAL DESCRIPTION
The AD5541 and AD5542 are single, 16-bit, serial input,
voltage output DACs that operate from a single 5 V
10%
supply.
The AD5541 and AD5542 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards.
These DACs provide 16-bit performance without any adjust-
ments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed to by an output buffer.
The AD5542 can be operated in bipolar mode generating a
V
REF
output swing. The AD5542 also includes Kelvin sense
connections for the reference and analog ground pins to reduce
layout sensitivity.
The AD5541 and AD5542 are available in an SO package.
PRODUCT HIGHLIGHTS
1. Single Supply Operation.
The AD5541 and AD5542 are fully specified and guaranteed
for a single 5 V
10% supply.
2. Low Power Consumption.
These parts consume typically 1.5 mW with a 5 V supply.
3. 3-Wire Serial Interface.
4. Unbuffered output capable of driving 60 k
loads.
This reduces power consumption as there is no internal buffer
to drive.
5. Power-On Reset circuitry.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
2
REV. A
AD5541/AD5542SPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Condition
STATIC PERFORMANCE
Resolution
16
Bits
Relative Accuracy, INL
0.5
1.0
LSB
L, C Grades
0.5
2.0
LSB
B, J Grades
0.5
4.0
LSB
A Grade
Differential Nonlinearity
0.5
1.0
LSB
Guaranteed Monotonic
1.5
LSB
J Grade
Gain Error
1.5
5
LSB
T
A
= 25
C
7
LSB
Gain Error Temperature Coefficient
0.1
ppm/
C
Zero Code Error
0.3
1
LSB
T
A
= 25
C
2
LSB
Zero Code Temperature Coefficient
0.05
ppm/
C
AD5542
Bipolar Resistor Matching
1.000
/
R
FB
/R
INV
, Typically R
FB
= R
INV
= 28 k
0.0015
0.0076
%
Ratio Error
Bipolar Zero Offset Error
1
5
LSB
T
A
= 25
C
7
LSB
Bipolar Zero Temperature Coefficient
0.2
ppm/
C
OUTPUT CHARACTERISTICS
Output Voltage Range
0
V
REF
1 LSB
V
Unipolar Operation
V
REF
V
REF
1 LSB
V
AD5542 Bipolar Operation
Output Voltage Settling Time
1
s
to 1/2 LSB of FS, C
L
= 10 pF
Slew Rate
25
V/
s
C
L
= 10 pF, Measured from 0% to 63%
Digital-to-Analog Glitch Impulse
10
nV-s
1 LSB Change Around the Major Carry
Digital Feedthrough
10
nV-s
All 1s Loaded to DAC, V
REF
= 2.5 V
DAC Output Impedance
6.25
k
Tolerance Typically 20%
Power Supply Rejection Ratio
1.0
LSB
V
DD
10%
DAC REFERENCE INPUT
Reference Input Range
2.0
V
DD
V
Reference Input Resistance
2
9
k
Unipolar Operation
7.5
k
AD5542, Bipolar Operation
LOGIC INPUTS
Input Current
1
A
V
INL
, Input Low Voltage
0.8
V
V
INH
, Input High Voltage
2.4
V
Input Capacitance
3
10
pF
Hysteresis Voltage
3
0.4
V
REFERENCE
Reference 3 dB Bandwidth
1.3
MHz
All 1s Loaded
Reference Feedthrough
1
mV p-p
All 0s Loaded, V
REF
= 1 V p-p at 100 kHz
Signal-to-Noise Ratio
92
dB
Reference Input Capacitance
75
pF
Code 0000 Hex
120
pF
Code FFFF Hex
POWER REQUIREMENTS
V
DD
4.50
5.50
V
I
DD
0.3
1.1
mA
Power Dissipation
1.5
6.05
mW
NOTES
1
Temperature ranges are as follows: A, B, C Versions: 40
C to +85
C. J, L Versions: 0
C to 70
C.
2
Reference input resistance is code-dependent, minimum at 8555 hex.
3
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
(V
DD
= 5 V 10%, V
REF
= 2.5 V, AGND = DGND = 0 V. All specifications
T
A
= T
MIN
to T
MAX,
unless otherwise noted.)
AD5541/AD5542
3
REV. A
SCLK
CS
DIN
DB15
LDAC
*
DB0
t
1
*AD5542
ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t
2
t
3
t
5
t
6
t
7
t
8
t
9
t
11
t
4
t
10
t
12
Figure 1. Timing Diagram
TIMING CHARACTERISTICS
1,
2
Limit at T
MIN
, T
MAX
Parameter
All Versions
Unit
Description
f
SCLK
25
MHz max
SCLK Cycle Frequency
t
1
40
ns min
SCLK Cycle Time
t
2
20
ns min
SCLK High Time
t
3
20
ns min
SCLK Low Time
t
4
15
ns min
CS Low to SCLK High Setup
t
5
15
ns min
CS High to SCLK High Setup
t
6
35
ns min
SCLK High to CS Low Hold Time
t
7
20
ns min
SCLK High to CS High Hold Time
t
8
15
ns min
Data Setup Time
t
9
0
ns min
Data Hold Time
t
10
30
ns min
LDAC Pulsewidth
t
11
30
ns min
CS High to LDAC Low Setup
t
12
30
ns min
CS High Time Between Active Periods
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to
90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Specifications subject to change without notice.
(V
DD
= 5 V 5%, V
REF
= 2.5 V, AGND = DGND = 0 V. All specifications T
A
= T
MIN
to T
MAX,
unless
otherwise noted.)
AD5541/AD5542
4
REV. A
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +6 V
Digital Input Voltage to DGND . . . . . 0.3 V to V
DD
+ 0.3 V
V
OUT
to AGND . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
AGND, AGNDF, AGNDS to DGND . . . . . 0.3 V to +0.3 V
Input Current to Any Pin Except Supplies . . . . . . . .
10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . 40
C to +85
C
Commercial (J, L Versions) . . . . . . . . . . . . . . . 0
C to 70
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
ORDERING GUIDE
Model
INL
DNL
Temperature Range
Package Description
Package Option
AD5541CR
1 LSB
1 LSB
40
C to +85
C
8-Lead Small Outline IC
SO-8
AD5541LR
1 LSB
1 LSB
0
C to 70
C
8-Lead Small Outline IC
SO-8
AD5541BR
2 LSB
1 LSB
40
C to +85
C
8-Lead Small Outline IC
SO-8
AD5541JR
2 LSB
1.5 LSB
0
C to 70
C
8-Lead Small Outline IC
SO-8
AD5541AR
4 LSB
1 LSB
40
C to +85
C
8-Lead Small Outline IC
SO-8
AD5542CR
1 LSB
1 LSB
40
C to +85
C
14-Lead Small Outline IC
R-14
AD5542LR
1 LSB
1 LSB
0
C to 70
C
14-Lead Small Outline IC
R-14
AD5542BR
2 LSB
1 LSB
40
C to +85
C
14-Lead Small Outline IC
R-14
AD5542JR
2 LSB
1.5 LSB
0
C to 70
C
14-Lead Small Outline IC
R-14
AD5542AR
4 LSB
1 LSB
40
C to +85
C
14-Lead Small Outline IC
R-14
Die Size = 80
139 = 11,120 sq mil; Number of Transistors = 1,230.
Maximum Junction Temperature, (T
J
max) . . . . . . . . . 150
C
Package Power Dissipation . . . . . . . . . . . . . (T
J
max T
A
)/
JA
Thermal Impedance
JA
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5
C/W
SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
AD5541/AD5542
5
REV. A
AD5541 PIN FUNCTION DESCRIPTIONS
Mnemonic
Pin No.
Description
V
OUT
1
Analog Output Voltage from the DAC.
AGND
2
Ground Reference Point for Analog Circuitry.
REF
3
This is the voltage reference input for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to V
DD
.
CS
4
This is a logic input signal. The chip select signal is used to frame the serial data input.
SCLK
5
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
DIN
6
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
DGND
7
Digital Ground. Ground reference for digital circuitry.
V
DD
8
Analog Supply Voltage, 5 V
10%.
Mnemonic
Pin No.
Description
RFB
1
Feedback Resistor. In bipolar mode connect this pin to external op amp output.
V
OUT
2
Analog Output Voltage from the DAC.
AGNDF
3
Ground Reference Point for Analog Circuitry (Force).
AGNDS
4
Ground Reference Point for Analog Circuitry (Sense).
REFS
5
This is the voltage reference input (sense) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to V
DD
.
REFF
6
This is the voltage reference input (force) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to V
DD
.
CS
7
This is a logic input signal. The chip select signal is used to frame the serial data input.
SCLK
8
Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
NC
9
No Connect.
DIN
10
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC
11
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
DGND
12
Digital Ground. Ground reference for digital circuitry.
INV
13
Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
inverting input in bipolar mode.
V
DD
14
Analog Supply Voltage, 5 V
10%.
AD5542 PIN FUNCTION DESCRIPTIONS
AD5541 PIN CONFIGURATION
SOIC
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
V
OUT
AGND
REF
V
DD
DGND
DIN
SCLK
CS
AD5541
AD5542 PIN CONFIGURATION
SOIC
TOP VIEW
(Not to Scale)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
NC = NO CONNECT
RFB
V
OUT
AGNDF
AGNDS
REFS
REFF
CS
V
DD
INV
DGND
LDAC
DIN
NC
SCLK
AD5542
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