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Электронный компонент: AD5547BRU

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Dual Current Output, Parallel Input, 16-/14-Bit
Multiplying DACs with 4-Quadrant Resistors
AD5547/AD5557
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Dual channel
16-bit resolution: AD5547
14-bit resolution: AD5557
2- or 4-quadrant, 4 MHz BW multiplying DAC
1 LSB DNL
1 LSB INL for AD5557, 2 LSB INL for AD5547
Operating supply voltage: 2.7 V to 5.5 V
Low noise: 12 nV/Hz
Low power: I
DD
= 10 A max
0.5 s settling time
Built-in R
FB
facilitates current-to-voltage conversion
Built-in 4-quadrant resistors allow 0 V to 10 V, 0 V to +10 V,
or 10 V outputs
2 mA full-scale current 20%, with V
REF
= 10 V
Extended automotive operating temperature range:
40C to +125C
Selectable zero-scale/midscale power-on presets
Compact TSSOP-38 package
APPLICATIONS
Automatic test equipment
Instrumentation
Digitally controlled calibration
Digital waveform generation
GENERAL DESCRIPTION
The AD5547/AD5557 are dual precision, 16-/14-bit,
multiplying, low power, current-output, parallel input, digital-
to-analog converters. They are designed to operate from single
+5 V supply with 10 V multiplying references for 4-quadrant
outputs with up to 4 MHz bandwidth.
FUNCTIONAL BLOCK DIAGRAM
DAC A
D0..D15
OR
D0..D13
DAC A
DAC B
ADDR
DECODE
INPUT
REGISTER
RS
DAC A
REGISTER
RS
DAC B
REGISTER
RS
POWER
ON
RESET
V
DD
R
COMB
R
COMA
R
1A
R
OFSA
V
REFA
R
1B
R
OFSB
04452-0-013
R
FBA
AGNDA
AGNDB
V
REFB
I
OUTA
R
FBB
I
OUTB
D0D15
(AD5547)
D0D13
(AD5557)
A0, A1
MSB
LDAC
DGND
WR
RS
INPUT
REGISTER
RS
DAC B
AD5547/AD5557
Figure 1.
The built-in 4-quadrant resistors facilitate resistance matching
and temperature tracking, which minimize the numbers of
components needed for multiquadrant applications. In addition,
the feedback resistor (R
FB
) simplifies the I-V conversion with an
external buffer.
The AD5547/AD5557 are available in a compact TSSOP-38
package and operate at the extended automotive temperature
range of 40C to +125C.
VREF
VREF
VREF TO +VREF
04452-0-002
U1
C1
R
1A
16/14 DATA
R
COMA
R1
R2
R
OFSA
R
FBA
C2
RFB
ROFS
16-/14-BIT
DAC A
MSB A0, A1
2
POWER-ON
RESET
AD5547/AD5557
IOUTA
AGNDA
(ONE CHANNEL SHOWN ONLY)
U2
VOUTA
V
REFA
MSB
A0, A1
LDAC
WR
RS
WR
RS
LDAC
Figure 2. 16/14-Bit 4-Quadrant Multiplying DAC with Minimum of External Components (Only One Channel Shown)
AD5547/AD5557
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 9
Circuit Operation ........................................................................... 12
D/A Converter Section .............................................................. 12
Digital Section............................................................................. 13
PCB Layout, Power Supply Bypassing, and Ground
Connections ................................................................................ 13
Applications..................................................................................... 14
Unipolar Mode ........................................................................... 14
Bipolar Mode .............................................................................. 16
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
Revision 0: Initial Version
AD5547/AD5557
Rev. 0 | Page 3 of 20
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, I
OUT
= Virtual GND, GND = 0 V, V
REF
= 10 V to +10 V, T
A
= 40C to +125C, unless otherwise noted.
Table 1. Electrical Characteristics
Parameter Symbol
Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE
1
Resolution
N
AD5547, 1 LSB = V
REF
/2
16
= 153 V at V
REF
= 10 V
16
Bits
AD5557, 1 LSB = V
REF
/2
14
= 610 V at V
REF
= 10 V
14
Bits
Relative Accuracy
INL
Grade: AD5557C
1
LSB
Grade:
AD5547B
2
LSB
Differential Nonlinearity
DNL
Monotonic
1
LSB
Output Leakage Current
I
OUT
Data = zero scale, T
A
= 25C
10
nA
Data = zero scale, T
A
= T
A
maximum
20
nA
Full-Scale Gain Error
G
FSE
Data = full scale
1
4
mV
Bipolar Mode Gain Error
G
E
Data = full scale
1
4
mV
Bipolar Mode Zero-Scale Error
G
ZSE
Data = full scale
1
3
mV
Full-Scale Tempco
2
TCV
FS
1
ppm/C
REFERENCE INPUT
V
REF
Range
V
REF
18
+18
V
REF Input Resistance
REF
4
5
6
k
R1 and R2 Resistance
R1 and R2
4
5
6
k
R1-to-R2 Mismatch
(R1 to R2)
0.5
1.5
Feedback and Offset Resistance
R
FB
, R
OFS
8 10
12 k
Input Capacitance
2
C
REF
5
pF
ANALOG OUTPUT
Output Current
I
OUT
Data = full scale
2
mA
Output Capacitance
2
C
OUT
Code
dependent
200
pF
LOGIC INPUT AND OUTPUT
Logic Input Low Voltage
V
IL
V
DD
= 5 V
0.8
V
V
DD
= 3 V
0.4
V
Logic Input High Voltage
V
IH
V
DD
= 5 V
2.4
V
V
DD
= 3 V
2.1
V
Input Leakage Current
I
IL
10
A
Input Capacitance
2
C
IL
10
pF
INTERFACE TIMING
2, 3
Data to WR Setup Time
t
DS
V
DD
= 5 V
20
ns
V
DD
= 3 V
35
ns
Data to WR Hold Time
t
DH
V
DD
= 5 V
0
ns
V
DD
= 3 V
0
ns
WR Pulse Width
t
WR
V
DD
= 5 V
20
ns
V
DD
= 3 V
35
ns
LDAC Pulse Width
t
LDAC
V
DD
= 5 V
20
ns
V
DD
= 3 V
35
ns
RS Pulse Width
t
RS
V
DD
= 5 V
20
ns
V
DD
= 3 V
35
ns
WR to LDAC Delay Time
t
LWD
V
DD
= 5 V
0
ns
V
DD
= 3 V
0
ns
SUPPLY CHARACTERISTICS
Power Supply Range
V
DD RANGE
2.7
5.5 V
Positive Supply Current
I
DD
Logic inputs = 0 V
10
A
Power Dissipation
P
DISS
Logic inputs = 0 V
0.055
mW
Power Supply Sensitivity
P
SS
V
DD
= 5%
0.003
%/%
AD5547/AD5557
Rev. 0 | Page 4 of 20
Parameter Symbol
Conditions
Min
Typ
Max
Unit
AC CHARACTERISTICS
4
Output Voltage Settling Time
t
S
To 0.1% of full scale, data cycles from zero scale
to full scale to zero scale
0.5
s
Reference Multiplying BW
BW
V
REF
= 5 V p-p, data = full scale
4
MHz
DAC Glitch Impulse
Q
V
REF
= 0 V, midscale to midscale 1
7
nV-s
Multiplying Feedthrough Error
V
OUT
/V
REF
V
REF
= 100 mV rms, f = 10 kHz
65
dB
Digital Feedthrough
Q
D
WR = 1, LDAC toggles at 1 MHz
7 nV-s
Total Harmonic Distortion
THD
V
REF
= 5 V p-p, data = full scale, f = 1 kHz
85
dB
Output Noise Density
e
N
f = 1 kHz, BW = 1 Hz
12
nV/Hz
Analog Crosstalk
C
AT
Signal input at Channel A and measure the output
at Channel B, f = 1 kHz
95
dB
1
All static performance tests (except I
OUT
) are performed in a closed-loop system using an external precision OP97 I-V converter amplifier. The device R
FB
terminal is tied
to the amplifier output. The OP97's +IN pin is grounded, and the DAC's I
OUT
is tied to the OP97's IN pin. Typical values represent average readings measured at 25C.
2
Guaranteed by design; not subject to production testing.
3
All input control signals are specified with t
R
= t
F
= 2.5 ns (10% to 90% of 3 V), and are timed from a voltage level of 1.5 V.
4
All ac characteristic tests are performed in a closed-loop system using an AD841 I-V converter amplifier.
03810-0-005
t
WR
t
DS
t
DH
t
LWD
t
LDAC
t
RS
WR
DATA
LDAC
RS
Figure 3. AD5547/AD5557 Timing Diagram
AD5547/AD5557
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
V
DD
to GND
0.3 V, +8 V
R
FB
, R
OFS
, R1, R
COM
, and VREF to GND
18 V, 18 V
Logic Inputs to GND
0.3 V, +8 V
V(I
OUT
) to GND
0.3 V, V
DD
+ 0.3 V
Input Current to Any Pin except Supplies
50 mA
Thermal Resistance (
JA
)
1
Maximum Junction Temperature (T
J
MAX
) 150C
Operating Temperature Range
40C to +125C
Storage Temperature Range
65C to +150C
Lead Temperature
Vapor Phase, 60 s
215C
Infrared, 15 s
220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Package power dissipation = (T
J MAX
T
A
)/
JA
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5547/AD5557
Rev. 0 | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5547
TOP VIEW
(Not to Scale)
D1
1
D0
2
R
OFSA
3
R
FBA
4
R
1A
5
V
REFA
7
I
OUTA
8
AGNDA
9
DGND
10
AGNDA
11
I
OUTB 12
V
REFB 13
R
COMB 14
R
1B 15
R
FBB 16
R
OFSB 17
18
A0
19
D2
38
D3
37
D4
36
D5
35
D6
34
D7
33
D8
32
D9
31
D10
30
VDD
29
D11
28
D12
27
D13
26
D14
25
D15
24
23
MSB
22
LDAC
21
A1
20
R
COMA
6
WR
RS
04452-0-003
NC
1
NC
2
R
OFSA
3
R
FBA
4
R
1A
5
V
REFA
7
I
OUTA
8
AGNDA
9
DGND
10
AGNDB
11
I
OUTB 12
V
REFB 13
R
COMB 14
R
1B 15
R
FBB 16
R
OFSB 17
18
A0
19
R
COMA
6
WR
NC = NO CONNECT
D0
38
D1
37
D2
36
D3
35
D4
34
D5
33
D6
32
D7
31
D8
30
VDD
29
D9
28
D10
27
D11
26
D12
25
D13
24
23
MSB
22
LDAC
21
A1
20
RS
04452-0-004
AD5557
TOP VIEW
(Not to Scale)
Figure 4. AD5547 TSSOP-38 Pin Configuration
Figure 5. AD5557 TSSOP-38 Pin Configuration
Table 3. AD5547 Pin Function Descriptions
Pin No.
Mnemonic
Function
1, 2, 24
28, 3038
D0D15
Digital Input Data Bits D0 to D15. Signal level must be V
DD
+ 0.3 V.
3 R
OFSA
Bipolar Offset Resistor A. Accepts up to 18 V. In 2-quadrant mode, R
OFSA
ties to R
FBA
. In 4-quadrant mode, R
OFSA
ties to R
1A
and the external reference.
4 R
FBA
Internal Matching Feedback Resistor A. Connects to the external op amp for I-V conversion.
5 R
1A
4-Quandrant Resistor. In 2-quadrant mode, R
1A
shorts to the V
REFA
pin. In 4-quadrant mode, R
1A
ties to R
OFSA
. Do
not connect when operating in unipolar mode.
6 R
COMA
Center Tap Point of the Two 4-Quadrant Resistors, R
1A
and R
2A
. In 4-quadrant mode, R
COMA
ties to the inverting
node of the reference amplifier. In 2-quadrant mode, R
COMA
shorts to the VREF pin. Do not connect if operating in
unipolar mode.
7 V
REFA
DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, V
REFA
is the
reference input with constant input resistance versus code. In 4-quadrant mode, V
REFA
is driven by the external
reference amplifier.
8 I
OUTA
DAC A Current Output. Connects to the inverting terminal of external precision I-V op amp for voltage output.
9
AGNDA
DAC A Analog Ground.
10 DGND
Digital
Ground.
11
AGNDB
DAC B Analog Ground.
12 I
OUTB
DAC B Current Output. Connects to inverting terminal of external precision I-V op amp for voltage output.
13 V
REFB
DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance versus code. If
configured with an external op amp for 4-quadrant multiplying, V
REFB
becomes V
REF
.
14 R
COMB
Center Tap Point of the Two 4-Quadrant Resistors, R
1B
and R
2B
. In 4-quadrant mode, R
COMB
ties to the inverting
node of the reference amplifier. In 2-quadrant mode, R
COMB
shorts to the VREF pin. Do not connect if operating in
unipolar mode.
15 R
1B
4-Quandrant Resistor. In 2-quadrant mode, R
1B
shorts to the V
REFB
pin. In 4-quadrant mode, R
1B
ties to R
OFSB
. Do not
connect if operating in unipolar mode.
16 R
FBB
Internal Matching Feedback Resistor B. Connects to external op amp for I-V conversion.
17 R
OFSB
Bipolar Offset Resistor B. Accepts up to 18 V. In 2-quadrant mode, R
OFSB
ties to R
FBB
. In 4-quadrant mode, R
OFSB
ties to R
1B
and an external reference.
AD5547/AD5557
Rev. 0 | Page 7 of 20
Pin No.
Mnemonic
Function
18
WR
Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC register on the rising edge.
Signal level must be V
DD
+ 0.3 V.
19
A0
Address Pin 0. Signal level must be V
DD
+ 0.3 V.
20
A1
Address Pin 1. Signal level must be V
DD
+ 0.3 V.
21
LDAC
Digital Input Load DAC Control. Signal level must be V
DD
+ 0.3 V.
22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The
signal level must be V
DD
+ 0.3 V.
23
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0, and to midscale if MSB = 1. Signal
level must be V
DD
+ 0.3 V.
29
VDD
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
Table 4. AD5557 Pin Function Descriptions
Pin No.
Mnemonic
Function
1, 2
NC
No Connection. Do not connect anything other than dummy pads to these pins.
3 R
OFSA
Bipolar Offset Resistor A. Accepts up to 18 V. In 2-quadrant mode, R
OFSA
ties to R
FBA
. In 4-quadrant mode, R
OFSA
ties
to R
1A
and the external reference.
4 R
FBA
Internal Matching Feedback Resistor A. Connects to the external op amp for I-V conversion.
5 R
1A
4-Quandrant Resistor. In 2-quadrant mode, R
1A
shorts to the V
REFA
pin. In 4-quadrant mode, R
1A
ties to R
OFSA
. Do not
connect when operating in unipolar mode.
6 R
COMA
Center Tap Point of the Two 4-Quadrant Resistors, R
1A
and R
2A
. In 4-quadrant mode, R
COMA
ties to the inverting node
of the reference amplifier. In 2-quadrant mode, R
COMA
shorts to the VREF pin. Do not connect if operating in
unipolar mode.
7 V
REFA
DAC A Reference Input in 2-Quadrant Mode, R2 Terminal in 4-Quadrant Mode. In 2-quadrant mode, V
REFA
is the
reference input with constant input resistance versus code. In 4-quadrant mode, V
REFA
is driven by the external
reference amplifier.
8 I
OUTA
DAC A Current Output. Connects to the inverting terminal of external precision I-V op amp for voltage output.
9
AGNDA
DAC A Analog Ground.
10 DGND Digital
Ground.
11
AGNDB
DAC B Analog Ground.
12 I
OUTB
DAC B Current Output. Connects to inverting terminal of external precision I-V op amp for voltage output.
13 V
REFB
DAC B Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance versus code. If configured
with an external op amp for 4-quadrant multiplying, V
REFB
becomes V
REF
.
14 R
COMB
Center Tap Point of the Two 4-Quadrant Resistors, R
1B
and R
2B
. In 4-quadrant mode, R
COMB
ties to the inverting node
of the reference amplifier. In 2-quadrant mode, R
COMB
shorts to the VREF pin. Do not connect if operating in
unipolar mode.
15 R
1B
4-Quandrant Resistor. In 2-quadrant mode, R
1B
shorts to the V
REFB
pin. In 4-quadrant mode, R
1B
ties to R
OFSB
. Do not
connect if operating in unipolar mode.
16 R
FBB
Internal Matching Feedback Resistor B. Connects to external op amp for I-V conversion.
17 R
OFSB
Bipolar Offset Resistor B. Accepts up to 18 V. In 2-quadrant mode, R
OFSB
ties to R
FBB
. In 4-quadrant mode, R
OFSB
ties
to R
1B
and an external reference.
18
WR
Write Control Digital Input In, Active Low. Transfers shift register data to the DAC register on the rising edge. Signal
level must be V
DD
+ 0.3 V.
19
A0
Address Pin 0. Signal level must be V
DD
+ 0.3 V.
20
A1
Address Pin 1. Signal level must be V
DD
+ 0.3 V.
21
LDAC
Digital Input Load DAC Control. Signal level must be V
DD
+ 0.3 V.
22 MSB Power-On Reset State. MSB = 0 corresponds to zero-scale reset; MSB = 1 corresponds to midscale reset. The signal
level must be V
DD
+ 0.3 V.
23
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0, and to midscale if MSB = 1. Signal
level must be V
DD
+ 0.3 V.
2428,
3038
D13 to D0
Digital Input Data Bits D13 to D0. Signal level must be V
DD
+ 0.3 V.
29
VDD
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
AD5547/AD5557
Rev. 0 | Page 8 of 20
Table 5. Address Decoder Pins
A1 A0 Output
Update
0 0 DAC
A
0 1 None
1
0
DAC A and B
1 1 DAC
B
Table 6. Control Inputs
RS
WR
LDAC Register
Operation
0
X
X
Reset the output to 0 with MSB pin = 0; reset the output to midscale with MSB pin = 1.
1
0
0
Load the input register with data bits.
1
1
1
Load the DAC register with the contents of the input register.
1
0
1
The input and DAC registers are transparent.
1
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse, and are then loaded into the DAC register on the rising edge of the pulse.
1
1
0
No register operation.
AD5547/AD5557
Rev. 0 | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
03810-0-006
1.0
0.8
0.6
0
8192
16384 24576 32768 40960 49152 57344 65536
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
INL
(
LSB)
CODE (Decimal)
Figure 6. AD5547 Integral Nonlinearity Error
03810-0-007
1.0
0.8
0.6
0
8192
16384 24576 32768 40960 49152 57344 65536
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
DNL (LS
B
)
CODE (Decimal)
Figure 7. AD5547 Differential Nonlinearity Error
03810-0-008
1.0
0.8
0.6
0
2048
4096
6144
8192
10240 12288 14336 16384
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
INL (LSB)
CODE (Decimal)
Figure 8. AD5557 Integral Nonlinearity Error
04452-0-010
1.0
0.8
0.6
0
2048
4096
6144
8192
10240 12288 14336 16384
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
DNL (LS
B
)
CODE (Decimal)
Figure 9. AD5557 Differential Nonlinearity Error
03810-0-010
1.5
1.0
2
4
GE
DNL
INL
6
8
0.5
0
0.5
1.0
1.5
LINE
ARITY
E
RROR (LS
B
)
SUPPLY VOLTAGE V
DD
(V)
V
REF
= 2.5V
T
A
= 25
C
10
Figure 10. Linearity Error vs. V
DD
03810-0-011
5
4
0
0.5
1.0
1.5
2.0
3.0
3.5
2.5
4.0
4.5
5.0
3
2
1
0
S
U
P
P
L
Y
CURRE
NT I
DD
(LS
B
)
LOGIC INPUT VOLTAGE V
IH
(V)
V
DD
= 5V
T
A
= 25
C
Figure 11. Supply Current vs. Logic Input Voltage
AD5547/AD5557
Rev. 0 | Page 10 of 20
03810-0-012
3.0
2.5
10k
100k
1M
10M
100M
2.0
1.5
1.0
0.5
0
S
U
P
P
L
Y
CURRE
NT (mA)
CLOCK FREQUENCY (Hz)
0x5555
0x8000
0xFFFF
0x0000
Figure 12. AD5547 Supply Current vs. Clock Frequency
04452-0-014
90
70
10
100
1k
10k
100k
1M
50
40
60
80
30
10
20
0
P
S
RR (dB)
FREQUENCY (Hz)
V
DD
= 5V
10%
V
REF
= 10V
Figure 13. Power Supply Rejection Ratio vs. Frequency
03810-0-014
LDAC
V
OUT
1
2
CH1
5.00V CH2 2.00V M 200ns
A CH1 2.70V
B CH1
6.20V
400.00ns
Figure 14. Settling Time from Full Scale to Zero Scale
03810-0-015
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
DD
= 5V
V
REF
= 10V
CODES 0x8000
0x7FFF
TIME (
s)
V
OUT
(50mV/DIV)
LDAC (5V/DIV)
Figure 15. AD5547 Midscale Transition and Digital Feedthrough
03810-0-016
0xFFFF
0x8000
0x4000
12dB
24dB
36dB
48dB
60dB
72dB
84dB
96dB
108dB
0x2000
0x1000
0x0800
0x0400
0x0200
0x0100
0x0080
0x0040
0x0020
0x0010
0x0008
0x0004
0x0002
0x0001
0x0000
10
100
1k
100k
10k
1M
10M
START 10.000Hz
STOP 50 000 000.000Hz
REF LEVEL
0.000dB
/DIV
12.000dB
MARKER 4 41 677.200Hz
MAG (A/R) 2.939db
Figure 16. AD5547 Unipolar Reference Multiplying Bandwidth
03810-0-017
0
12
24
36
48
60
72
84
96
108
120
10
100
1k
100k
10k
1M
10M
START 10.000Hz
STOP 10 000 000.000Hz
REF LEVEL
0.000dB
/DIV
12.000dB
ALL BITS ON
D15 AND D14 ON
D15 AND D13 ON
D15 AND D12 ON
D15 AND D11 ON
D15 AND D10 ON
D15 AND D9 ON
D15 AND D8 ON
D15 AND D7 ON
D15 AND D6 ON
D15 AND D5 ON
D15 AND D4 ON
D15 AND D3 ON
D15 AND D2 ON
D15 AND D1 ON
D15 AND D0 ON
D15 ON
Figure 17. AD5547 Bipolar Reference Multiplying Bandwidth (Codes from
Midscale to Full Scale)
AD5547/AD5557
Rev. 0 | Page 11 of 20
03810-0-018
0
12
24
36
48
60
72
84
96
108
120
10
100
1k
100k
10k
1M
10M
START 10.000Hz
STOP 10 000 000.000Hz
REF LEVEL
0.000dB
/DIV
12.000dB
ALL BITS OFF
D14 ON
D14 AND D13 ON
D14 AND D12 ON
D14 AND D11 ON
D14 AND D10 ON
D14 AND D9 ON
D14 AND D8 ON
D14 AND D7 ON
D14 AND D6 ON
D14 AND D5 ON
D14 AND D4 ON
D14 AND D3 ON
D14 AND D2 ON
D14 AND D1 ON
D14 AND D0 ON
D14 ON
Figure 18. AD5547 Bipolar Reference Multiplying Bandwidth (Codes from
Midscale to Zero Scale)
AD5547/AD5557
Rev. 0 | Page 12 of 20
CIRCUIT OPERATION
D/A CONVERTER SECTION
The AD5547/AD5557 are 16-/14-bit, multiplying, current
output, parallel input DACs. The devices operate from a single
2.7 V to 5.5 V supply, and provide both unipolar (0 V to V
REF
or 0 V to +V
REF
), and bipolar (V
REF
) output ranges from 18 V
to +18 V references. In addition to the precision conversion R
FB
commonly found in current output DACs, there are three addi-
tional precision resistors for 4-quadrant bipolar applications.
The AD5547/AD5557 consist of two groups of precision R-2R
ladders, which make up the 12/10 LSBs, respectively. Further-
more, the 4 MSBs are decoded into 15 segments of resistor value
2R. Figure 19 shows the architecture of the 16-bit AD5547. Each
of the 16 segments and the R-2R ladder carries an equally
weighted current of one-sixteenth of full scale. The feedback
resistor R
FB
and 4-quadrant resistor R
OFS
have values of 10 k.
Each 4-quadrant resistor, R1 and R2, equals 5 k. In 4-quadrant
operation, R1, R2, and an external op amp work together to
invert the reference voltage and apply it to the VREF input.
With R
OFS
and R
FB
connected as shown in Figure 2, the output
can swing from V
REF
to +V
REF
.
The reference voltage inputs exhibit a constant input resistance
of 5 k 20%. The impedance of I
OUT
, the DAC output, is code
dependent. External amplifier choice should take into account
the variation of the AD5547/AD5557 output impedance. The
feedback resistance in parallel with the DAC ladder resistance
dominates output voltage noise. To maintain good analog
performance, it is recommended that the power supply is
bypassed with a 0.01 F to 0.1 F ceramic or chip capacitor in
parallel with a 1 F tantalum capacitor. Also, to minimize gain
error, PCB metal traces between V
REF
and R
FB
should match.
Every code change of the DAC corresponds to a step function;
gain peaking at each output step may occur if the op amp has
limited GBP and excessive parasitic capacitance present at the
op amp's inverting node. A compensation capacitor, therefore,
may be needed between the I-V op amp inverting and output
nodes to smooth the step transition. Such a compensation
capacitor should be found empirically, but a 20 pF capacitor is
generally adequate for the compensation.
The V
DD
power is used primarily by the internal logic to drive
the DAC switches. Note that the output precision degrades if the
operating voltage falls below the specified voltage. Users should
also avoid using switching regulators because device power
supply rejection degrades at higher frequencies.
04452-0-011
2R
80k
R
40k
2R
80k
2R
80k
2R
80k
2R
80k
2R
80k
R
40k
2R
80k
R
2R
80k
R
2R
80k
R
2R
80k
R
2R
80k
2R
80k
R
40k
R2
5k
R1
5k
V
REF
2R
80k
R
40k
2R
80k
R
40k
2R
80k
R
40k
2R
80k
R
40k
2R
80k
R
40k
2R
80k
RCOM
R1
ADDRESS DECODER
DAC REGISTER
INPUT REGISTER
LDAC
WR
RS
RS
4 MSB
15 SEGMENTS
8-BIT R2R
4-BIT R2R
15
8
4
LDAC
WR
D15 D14
D0
RS
10k
10k
ROFS
RFB
IOUT
AGND
RA
RB
Figure 19. 16-Bit AD5547 Equivalent R-2R DAC Circuit with Digital Section, One Channel Shown
AD5547/AD5557
Rev. 0 | Page 13 of 20
DIGITAL SECTION
The AD5547/AD5557 have 16-/14-bit parallel inputs. The
devices are double-buffered with 16-/14-bit registers. The dou-
ble-buffered feature allows the simultaneous update of several
AD5547/AD5557s. For the AD5547, the input register is loaded
directly from a 16-bit controller bus when WR is brought low.
The DAC register is updated with data from the input register
when LDAC is brought high. Updating the DAC register
updates the DAC output with the new data (see Figure 19). To
make both registers transparent, tie WR low and LDAC high.
The asynchronous RS pin resets the part to zero scale if the
MSB pin = 0, and to midscale if the MSB pin = 1.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
connected to ground (GND) and V
DD
, as shown in Figure 20. As
a result, the voltage level of the logic input should not be greater
than the supply voltage.
03810-0-020
5k
DIGITAL
INPUTS
DGND
V
DD
Figure 20. Equivalent ESD Protection Circuits
Amplifier Selection
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. A 30 nA input
bias current in the op amp contributes to 1 LSB in the AD5547's
full-scale error. The OP1177 and AD8628 op amps are good
candidates for the I-V conversion.
Reference Selection
The initial accuracy and rated output of the voltage reference
determine the full-span adjustment. The initial accuracy of the
reference is usually a secondary concern because it can be
trimmed. Figure 26 shows an example of a trimming circuit.
The zero-scale error can also be minimized by standard op amp
nulling techniques.
The voltage reference temperature coefficient and long-term
drift are primary considerations. For example, a 5 V reference
with a TC of 5 ppm/C means the output changes by 25 V/C.
As a result, a reference operating at 55C contributes an
additional 750 V full-scale error.
Similarly, the same 5 V reference with a 50 ppm long-term
drift means the output may change by 250 V over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
PCB LAYOUT, POWER SUPPLY BYPASSING, AND
GROUND CONNECTIONS
It is a good practice to employ a compact, minimum-lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
The PCB metal traces between V
REF
and R
FB
should also be
matched to minimize gain error.
It is also essential to bypass the power supply with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 F to 0.1 F disc or chip ceramic
capacitors. Low ESR 1 F to 10 F tantalum or electrolytic
capacitors should also be applied at the supply in parallel with
the ceramic capacitor to minimize transient disturbance and
filter out low frequency ripple.
To minimize the digital ground bounce, the AD5547/AD5557
DGND terminal should be joined with the AGND terminal at a
single point. Figure 21 illustrates the basic supply-bypassing
configuration and AGND/DGND connection for the
AD5547/AD5557.
V
DD
AGND
DGND
C1
C2
5V
+
1
F
0.1
F
04452-0-015
AD5547/AD5557
Figure 21. Power Supply Bypassing
AD5547/AD5557
Rev. 0 | Page 14 of 20
APPLICATIONS
UNIPOLAR MODE
2-Quadrant Multiplying Mode, V
OUT
= 0 V to V
REF
The AD5547/AD5557 DAC architecture uses a current-steering
R-2R ladder design that requires an external reference and op
amp to convert the unipolar mode of output voltage to
V
OUT
= V
REF
D/65,536 (AD5547) (1)
V
OUT
= V
REF
D/16,384 (AD5557) (2)
where D is the decimal equivalent of the input code.
In this case, the output voltage polarity is opposite the V
REF
polarity (see Figure 22). Table 7 shows the negative output
versus code for the AD5547.
Table 7. AD5547 Unipolar Mode Negative Output vs. Code
D in Binary
V
OUT
(V)
1111 1111 1111 1111
V
REF
(65,535/65,536)
1000 0000 0000 0000
V
REF
/2
0000 0000 0000 0001
V
REF
(1/65,536)
0000 0000 0000 0000
0
WR
WR
RS
RS
2
LDAC
+2.5V
04452-0-007
AD8628
AD5547/AD5557
R
1A
16/14 DATA
VDD
R
COMA
R2
U1
R1
R
OFSA
R
FBA
C6
RFB
ROFS
MSB A0, A1
I
OUTA
AGNDA
2.2pF
C1
1
F
C2
0.1
F
C3
0.1
F
V
OUTA
V
REFA
MSB
A0, A1
LDAC
+V
V
GND
4
VOUT
TRIM
ADR03
5
6
VIN
U3
2
+5V
16-/14-BIT
2.5V
C4
1
F
0.1
F
C5
5V
2.5V TO 0V
Figure 22. Unipolar 2-Quadrant Multiplying Mode, V
OUT
= 0 to V
REF
AD5547/AD5557
Rev. 0 | Page 15 of 20
2-Quadrant Multiplying Mode, V
OUT
= 0 V to +V
REF
The AD5547/AD5557 are designed to operate with either
positive or negative reference voltages. As a result, a positive
output can be achieved with an additional op amp, (see
Figure 23); the output becomes
V
OUT
= +V
REF
D/65,536 (AD5547) (3)
V
OUT
= +V
REF
D/16,384 (AD5557) (4)
Table 8 shows the positive output versus code for the AD5547.
Table 8. AD5547 Unipolar Mode Positive Output vs. Code
D in Binary
V
OUT
(V)
1111 1111 1111 1111
+V
REF
(65,535/65,536)
1000 0000 0000 0000
+V
REF
/2
0000 0000 0000 0001
+V
REF
(1/65,536)
0000 0000 0000 0000
0
WR
WR
RS
RS
2
LDAC
2.5V
+2.5V
0V TO +2.5V
+5V
04452-0-005
AD8628
AD8628
AD5547/AD5557
C7
R
1A
16/14 DATA
VDD
R
COMA
R2
R1
R
OFSA
R
FBA
C6
RFB
ROFS
MSB A0, A1
I
OUTA
AGNDA
U2B
C4
1
F
0.1
F
C1
1
F
C2
1
F
C3
0.1
F
C5
V
OUTA
V
REFA
MSB
A0, A1
LDAC
+V
V
GND
ADR03
4
VOUT
TRIM
5
6
VIN
U3
U2A
2
+5V
16-/14-BIT
Figure 23. Unipolar 2-Quadrant Multiplying Mode, V
OUT
= 0 to +V
REF
AD5547/AD5557
Rev. 0 | Page 16 of 20
WR
WR
RS
RS
C6 0.1
F
C7 1
F
2
+10V
10V
15V
10V TO +10V
+15V
04452-0-006
AD8512
AD8512
AD5547/AD5557
C8
U2A
R
1A
16/14 DATA
VDD
R
COMA
R2
U1
R1
R
OFSA
R
FBA
C9
RFB
ROFS
MSB A0, A1
I
OUTA
AGNDA
U2B
C4 1
F
C1
1
F
C2
0.1
F
C3
0.1
F
C5 0.1
F
VOUT
V
REFA
MSB
A0, A1
LDAC
LDAC
+V
V
GND
ADR01
4
VOUT
TRIM
5
6
VIN
U3
2
+15V
+5V
16-/14-BIT
DAC A
Figure 24. 4-Quadrant Multiplying Mode, V
OUT
= V
REF
to +V
REF
BIPOLAR MODE
4-Quadrant Multiplying Mode, V
OUT
= V
REF
to +V
REF
The AD5547/AD5557 contain on-chip all the 4-quadrant
resistors necessary for precision bipolar multiplying operation.
Such a feature minimizes the number of exponent components
to only a voltage reference, dual op amp, and compensation
capacitor (see Figure 24). For example, with a +10 V reference,
the circuit yields a precision, bipolar 10 V to +10 V output.
Table 9 shows some of the results for the 16-bit AD5547.
V
OUT
= (D/32768 - 1) V
REF
(AD5547) (5)
V
OUT
= (D/16384 - 1) V
REF
(AD5557) (6)
Table 9. AD5547 Output vs. Code
D in Binary
V
OUT
1111 1111 1111 1111
+V
REF
(32,767/32,768)
1000 0000 0000 0001
+V
REF
(1/32,768)
1000 0000 0000 0000
0
0111 1111 1111 1111
V
REF
(1/32,768)
0000 0000 0000 0000
V
REF
AD5547/AD5557
Rev. 0 | Page 17 of 20
AC Reference Signal Attenuator
Besides handling the digital waveform decoded from the
parallel input data, the AD5547/AD5557 can also handle low
frequency ac reference signals for signal attenuation, channel
equalization, and waveform generation applications. The
maximum signal range can be up to 18 V (See Figure 25).
System Calibration
The initial accuracy of the system can be adjusted by trimming
the voltage reference ADR0x with a digital potentiometer (see
Figure 26). The AD5170 provides a one-time programmable
(OTP), 8-bit adjustment that is ideal and reliable for such
calibration. ADI's OTP digital potentiometer comes with
programmable software that simplifies factory calibration.
WR
WR
RS
RS
2
LDAC
04452-0-008
AD5547/AD5557
16/14 DATA
VDD
R
OFSA
R
FBA
C6
RFB
ROFS
MSB A0, A1
I
OUTA
AGNDA
C2
0.1
F
C1
1
F
V
OUTA
MSB
A0, A1
LDAC
+10V
10V
+5V
OP2177
C7
R
1A
R
COMA
R2
R1
V
REFA
16-/14-BIT
C4
+15V
U2B
1
F
0.1
F
C5
C8
1
F
0.1
F
C9
OP2177
+V
V
U2A
U1
15V
Figure 25. Signal Attenuator with AC Reference
WR
WR
RS
RS
2
LDAC
04452-0-009
AD5547/AD5557
16/14 DATA
VDD
R
OFSA
R
FBA
C6
RFB
ROFS
MSB A0, A1
I
OUTA
U2B
+5V
AGNDA
C1
1
F
C2
0.1
F
C3
0.1
F
V
OUTA
MSB
A0, A1
LDAC
REF 01/AD
4
5
10k
1k
6
U3
AD5170
R7
R3
+2.5V
U4
U2
B
470k
2
+5V
0V TO +2.5V
2.5V
AD8628
C7
R
1A
R
COMA
R2
U1
R1
V
REFA
16-/14-BIT
GND
ADR03
VOUT
TRIM
VIN
C4
1
F
0.1
F
C5
AD8628
+V
V
Figure 26. Full-Span Calibration
AD5547/AD5557
Rev. 0 | Page 18 of 20
Table 10 lists the latest DACS available from Analog Devices.
Table 10. ADI Current Output DACs
Model Bits
Outputs
Interface
Package Comments
AD5425
8
1
SPI, 8-Bit Load
MSOP-10
Fast 8-bit load; see also AD5426.
AD5426
8
1
SPI
MSOP-10
See also AD5425 fast load.
AD5450
8
1
SPI
SOT23-8
See also AD5425 fast load.
AD5424 8 1
Parallel
TSSOP-16
AD5429 8 2
SPI
TSSOP-16
AD5428 8 2
Parallel
TSSOP-20
AD5432 10 1
SPI
MSOP-10
AD5451 10 1
SPI
SOT23-8
AD5433 10 1
Parallel
TSSOP-20
AD5439 10 2
SPI
TSSOP-16
AD5440 10 2
Parallel
TSSOP-24
AD5443
12
1
SPI
MSOP-10
See also AD5452 and AD5444.
AD5452 12 1
SPI
SOT23-8 Higher
accuracy
version of AD5443; see also AD5444.
AD5445 12 1
Parallel
TSSOP-20
AD5444
12
1
SPI
MSOP-10
Higher accuracy version of AD5443; see also AD5452.
AD5449 12 2
SPI
TSSOP-16
AD5415 12 2
SPI
TSSOP-24 Uncommitted
resistors.
AD5447 12 2
Parallel
TSSOP-24
AD5405 12 2
Parallel
LFCSP-40 Uncommitted
resistors.
AD5453 14 1
SPI
SOT23-8
AD5553 14 1
SPI
MSOP-8
AD5556 14 1
Parallel
TSSOP-28
AD5446
14
1
SPI
MSOP-10
MSOP version of AD5453; compatible with AD5443, AD5432, and AD5426.
AD5555 14 2
SPI
TSSOP-16
AD5557 14 2
Parallel
TSSOP-38
AD5543 16 1
SPI
MSOP-8
AD5546 16 1
Parallel
TSSOP-28
AD5545 16 2
SPI
TSSOP-16
AD5547 16 2
Parallel
TSSOP-38
AD5547/AD5557
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
38
20
19
1
9.80
9.70
9.60
PIN 1
SEATING
PLANE
0.15
0.05
0.50
BSC
1.20
MAX
0.27
0.17
0.20
0.09
8
0
4.50
4.40
4.30
6.40 BSC
0.70
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153BD-1
COPLANARITY
0.10
Figure 27. 38-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-38)
Dimension s shown in millimeters
ORDERING GUIDE
Model
Resolution
(Bits)
DNL
(LSB)
INL
(LSB)
Temperature
Range
Ordering
Quantity
Package Description
Package
Option
AD5547BRU
16
1
2
40C to +125C
50
Thin Shrink Small Outline Package (TSSOP)
RU-38
AD5547BRU-REEL7
16
1 2 40C
to
+125C
1,000 Thin Shrink Small Outline Package (TSSOP)
RU-38
AD5557CRU
14
1
1
40C to +125C
50
Thin Shrink Small Outline Package (TSSOP)
RU-38
AD5557CRU-REEL7
14
1 1 40C
to
+125C
1,000 Thin Shrink Small Outline Package (TSSOP)
RU-38
AD5547/AD5557
Rev. 0 | Page 20 of 20
NOTES
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0445204/04(0)