Document Outline
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2.7 V to 5.5 V, 250 A, Rail-to-Rail Output,
Dual 16-Bit nanoDAC
AD5663
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Low power, dual 16-bit nanoDAC
Relative accuracy: 12 LSBs maximum
Guaranteed monotonic by design
10-lead MSOP and 3 mm 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Per channel power-down
Power-on reset to zero scale or midscale
Hardware LDAC and CLR functions
Serial interface; up to 50 MHz
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
INTERFACE
LOGIC
SCLK
SYNC
DIN
CLR
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
V
DD
GND
POWER-ON
RESET
STRING
DAC A
STRING
DAC B
BUFFER
BUFFER
V
REF
POWER-DOWN
LOGIC
V
OUT
A
V
OUT
B
AD5663
LDAC
LDAC
058
55-
001
Figure 1.
Table 1. Related Devices
Part No.
Description
AD5623R/AD5643R/AD5663R
2.7 V to 5.5 V, dual 12-/14-/16-bit
DACs with internal reference
GENERAL DESCRIPTION
The AD5663, a member of the nanoDAC family, is a low power,
dual, 16-bit buffered voltage-out DAC that operates from a single
2.7 V to 5.5 V supply and is guaranteed monotonic by design.
The AD5663 requires an external reference voltage to set the
output range of the DAC. The part incorporates a power-on
reset circuit that ensures the DAC output powers up to 0 V or
midscale (AD5663-1) and remains there until a valid write takes
place. The part contains a power-down feature that reduces the
current consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The low power consumption of this part in normal operation
makes it ideally suited to portable, battery-operated equipment.
The power consumption is 1.25 mW at 5 V, going down to
2.4 W in power-down mode.
The on-chip precision output amplifier of the AD5663 allows
rail-to-rail output swing to be achieved.
The AD5663 uses a versatile, 3-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPI, QSPITM, MICROWIRETM, and DSP interface
standards.
PRODUCT HIGHLIGHTS
1.
Dual 16-bit DAC; relative accuracy of 12 LSBs maximum.
2.
Available in 10-lead MSOP and 10-lead, 3 mm 3 mm
LFCSP_WD packages.
3.
Low power; typically consumes 0.6 mW at 3 V and
1.25 mW at 5 V.
4.
7 s maximum settling time.
AD5663
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 14
D/A Section................................................................................. 14
Resistor String ............................................................................. 14
Output Amplifier........................................................................ 14
Serial Interface ............................................................................ 14
Input Shift Register .................................................................... 14
SYNC Interrupt .......................................................................... 15
Power-On Reset.......................................................................... 15
Software Reset............................................................................. 15
Power-Down Modes .................................................................. 16
LDAC Function .......................................................................... 16
Microprocessor Interfacing....................................................... 18
Applications..................................................................................... 19
Choosing a Reference for the AD5663 .................................... 19
Using a Reference as a Power Supply for the AD5663 .......... 19
Bipolar Operation Using the AD5663 ..................................... 20
Using the AD5663 with a Galvanically Isolated Interface .... 20
Power Supply Bypassing and Grounding................................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
4/06--Revision 0: Initial Version
AD5663
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; V
REF
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A
Grade
1
B Grade
1
Parameter Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
STATIC PERFORMANCE
2
AD5663
Resolution 16
16
Bits
Relative Accuracy
8
16
6
12
LSB
Differential Nonlinearity
1
1
LSB
Guaranteed monotonic by design
Zero-Scale Error
+2
+10
+2
+10
mV
All 0s loaded to DAC register
Offset Error
1
10
1
10
mV
Full-Scale Error
-0.15
1
-0.15
1
% of FSR
All 1s loaded to DAC register
Gain Error
1.5
1.5
% of FSR
Zero-Scale Error Drift
3
2 2 V/C
Gain Temperature Coefficient
2.5
2.5
ppm
Of FSR/C
DC Power Supply Rejection Ratio
-100
-100
dB
DAC code = midscale, V
DD
10%
DC Crosstalk
10
10
V
Due to full-scale output change
R
L
= 2 k to GND or V
DD
10
10
V/mA
Due to load current change
5
5
V
Due to powering down (per channel)
OUTPUT CHARACTERISTICS
2
Output Voltage Range
0
V
DD
0
V
DD
V
Capacitive Load Stability
2
2
nF
R
L
=
10
10
nF
R
L
= 2 k
DC Output Impedance
0.5
0.5
Short-Circuit Current
30
30
mA
V
DD
= 5 V
Power-Up Time
4
4
s
Coming out of power-down mode;
V
DD
= 5 V
REFERENCE INPUTS
Reference Current
170
200
170
200
A
V
REF
= V
DD
= 5.5 V, 3.6 V
Reference Input Range
0.75
V
DD
0.75
V
DD
V
Reference Input Impedance
26
26
k
LOGIC INPUTS
3
Input Current
2
2
A
All digital inputs
V
INL
, Input Low Voltage
0.8
0.8
V
V
DD
= 5 V, 3 V
V
INH
, Input High Voltage
2
2
V
V
DD
= 5 V, 3 V
Pin Capacitance
3
3
pF
DIN, SCLK, and SYNC
19
19
pF
LDAC and CLR
POWER REQUIREMENTS
V
DD
2.7
5.5 2.7
5.5 V
I
DD
(Normal Mode)
4
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
250
450
250
450
A
V
DD
= 2.7 V to 3.6 V
200
425
200
425
A
I
DD
(All Power-Down
Modes)
5
V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V
0.48
1
0.48
1
A
V
DD
= 2.7 V to 3.6 V
0.2
1
0.2
1
A
1
Temperature range: A grade and B grade are both equal to -40C to +105C.
2
Linearty calculated using a reduced code range: AD5663 (Code 512 to Code 65024). Output unloaded.
3
Guaranteed by design and characterization, not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
Both DACs powered down.
AD5663
Rev. 0 | Page 4 of 24
AC CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; V
REF
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
1
Table 3.
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
4
7
s
1/4 to 3/4 scale settling to 2 LSB
Slew Rate
1.8
V/s
Digital-to-Analog Glitch Impulse
10
nV-s
1 LSB change around major carry
Digital Feedthrough
0.1
nV-s
Reference Feedthrough
-90
dBs
V
REF
= 2 V 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk
0.1
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
1
nV-s
Multiplying Bandwidth
340
kHz
V
REF
= 2 V 0.1 V p-p
Total Harmonic Distortion
-80
dB
V
REF
= 2 V 0.1 V p-p; frequency = 10 kHz
Output Noise Spectral Density
120
nV/Hz
DAC code = midscale, 1 kHz
100
nV/Hz
DAC code = midscale, 10 kHz
Output Noise
15
V p-p
0.1 Hz to 10 Hz
1
Guaranteed by design and characterization, not production tested.
2
See the Terminology section.
AD5663
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
1
Table 4.
Limit
at
T
MIN
, T
MAX
Parameter
V
DD
= 2.7 V to 5.5 V
Unit
Conditions/Comments
t
1
2
20
ns min
SCLK cycle time
t
2
9
ns min
SCLK high time
t
3
9
ns min
SCLK low time
t
4
13
ns min
SYNC to SCLK falling edge setup time
t
5
5
ns min
Data setup time
t
6
5
ns min
Data hold time
t
7
0
ns min
SCLK falling edge to SYNC rising edge
t
8
15
ns min
Minimum SYNC high time
t
9
13
ns min
SYNC rising edge to SCLK fall ignore
t
10
0
ns min
SCLK falling edge to SYNC fall ignore
t
11
10
ns min
LDAC pulse width low
t
12
15
ns min
SCLK falling edge to LDAC rising edge
t
13
5
ns min
CLR pulse width low
t
14
0
ns min
SCLK falling edge to LDAC falling edge
t
15
300 ns
max
CLR pulse activation time
1
Guaranteed by design and characterization; not production tested.
2
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
TIMING DIAGRAM
05
85
5-
00
2
t
4
t
3
SCLK
SYNC
DIN
t
1
t
2
t
5
t
6
t
7
t
8
DB23
t
9
t
10
t
11
t
12
LDAC
1
LDAC
2
t
14
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
CLR
t
13
t
15
V
OUT
DB0
Figure 2. Serial Write Operation
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