Quad, 16 Bit Dac with 10ppm/C Max On-
Chip Reference in 14-Lead TSSOP
Preliminary Technical Data
AD5666
FEATURES
Low Power Quad 16 Bit DAC
12-Bit Accuracy Guaranteed
14-Lead TSSOP Package
On-chip 1.25/2.5V, 10ppm/C Reference
Power-Down to 200 nA @ 5V, 50 nA @ 3V
3V/5V Power Supply
Guaranteed Monotonic by Design
Power-On-Reset to Zero or Midscale
Three Power-Down Functions
Hardware /LDAC and /CLR functions
SDO Daisy-Chaining Option
Rail-to-Rail Operation
Temperature Range -40C to +125C
APPLICATIONS
ProcessControl
Data Acquisition Systems
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
POWER-
ON
RESET
LDAC CLR
INTERFACE
LOGIC
DIN
SYNC
SCLK
I
NPUT
REGISTER
I
NPUT
REGISTER
I
NPUT
REGISTER
I
NPUT
REGISTER
D
AC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC C
STRING
DAC A
STRING
DAC B
STRING
DAC D
BUFFER
BUFFER
BUFFER
BUFFER
LDAC
POWER-DOWN
LOGIC
VOUTB
VOUTC
VOUTD
VDD
VOUTA
V
REF
),#$$$
1.25/2.5V
Ref
SDO
POR
GND
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD5666 DAC is a low power, quad, 16-bit buffered
voltage-out DAC. The part operates from a single +2.7V to
+5.5V, and is guaranteed monotonic by design.
The AD5666 has an on-chip reference with an internal gain of
two. The AD5666-1 has a 1.25V 10ppm/C max reference and
the AD5666-2 has a 2.5V 10ppm/C max reference. The on-
board reference is off at power-up allowing the use of an
external reference. The internal reference is turned on by
writing to the DAC. The part incorporates a power-on-reset
circuit that ensures that the DAC output powers up to zero
volts (POR pin low) or midscale (POR pin high) and remains
there until a valid write takes place. The part contains a
power-down feature that reduces the current consumption of
the device to 200nA at 5V and provides software selectable
output loads while in power-down mode for any or all DACs
channels.
The outputs of all DACs may be updated simultaneously using
the /LDAC function, with the added functionality of selecting
through software any number of DAC channels to synchronize.
There is also an asynchronous active low /CLR that clears all
DACs to a software selectable code - 0 V, midscale or fullscale .
The AD5666 utilizes a versatile three-wire serial interface that
operates at clock rates up to 50 MHz and is compatible with
standard SPITM, QSPITM, MICROWIRETM and DSP interface
standards. Its on-chip precision output amplifier allows rail-to-
rail output swing to be achieved.
PRODUCT HIGHLIGHTS
1.
Quad 16-Bit DAC; 12-Bit Accuracy Guaranteed.
2.
On-chip 1.25/2.5V, 10ppm/C max Reference.
3.
Available in 14-lead TSSOP package.
4.
Selectable Power-On-Reset to Zero volts or Midscale.
5.
Power-down capability. When powered down, the
DAC typically consumes 50nA at 3V and 200nA at 5V.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
Rev. PrA
AD5666
Preliminary Technical Data
Rev.PrA | Page 2 of 23
TABLE OF CONTENTS
Features .......................................................................................... 1
Applications................................................................................... 1
General Description..................................................................... 1
Product Highlights ....................................................................... 1
AD5666Specifications.................................................................... 3
Timing Characteristics..................................................................... 3
Pin Configuration and Function Descriptions........................... 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Terminology................................................................................ 11
AD5666Typical Performance Characteristics .......................... 13
General Description................................................................... 16
Serial Interface ............................................................................ 16
Microprocessor Interfacing............................................................
Applications .....................................................................................
Outline Dimensions ....................................................................... 23
Ordering Guide ...............................................................................
REVISION HISTORY
Revision 0: Initial Version
Preliminary Technical Data
AD5666
Rev. PrA| Page 3 of 23
AD5666SPECIFICATIONS
(V
DD
= +4.5 V to +5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; External VREF = Vdd; all specifications T
MIN
to T
MAX
unless otherwise
noted)
Table 1.
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
B Version
1
,
2
Conditions/Comments
STATIC PERFORMANCE
3,4
Resolution
16
16
Bits
Relative Accuracy
32
16
LSB
See Figure 4
Differential
Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design.
See Figure 5.
Load
Regulation 2
2
LSB/mA
VDD=Vref=5V, Midscale
Iout=0mA to 15mA
sourcing/sinking
Zero Code Error
+1
+9
+1
+9
mV
All Zeroes Loaded to DAC Register.
See Figure 8.
Zero Code Error Drift
3
20
20
V/C
Full-Scale Error
-0.15
-1.25
-0.15
-1.25
% of FSR
All Ones Loaded to DAC Register.
See Figure 8.
Gain Error
0.7
0.7
% of FSR
Gain Temperature
Coefficient
5
5
ppm
of
FSR/C
Offset Error
1
9
1
9
mV
Offset Temperature
Coefficient
1.7
1.7
V/C
DC Power Supply
Rejection Ratio
6
80
80
dB
V
DD
10%
DC Crosstalk
6
28 28
V
R
L
= 2 k. to GND or V
DD
3.5
3.5
V/mA
Due to Load current change
-7.3
-7.3
V
Due to Powering Down (per
channel)
OUTPUT
CHARACTERISTICS
6
Output Voltage Range
0
V
DD
0
V
DD
V
Capacitive Load
Stability
470
470
pF
R
L
=
1000
1000
pF
R
L
=2 k
DC Output Impedance
1
1
Short Circuit Current
50
50
mA
V
DD
=+5V
Power-Up Time
10
10
s
Mode. V
DD
=+5V
REFERENCE INPUTS
3
Reference Input voltage
Vdd
Vdd
V
1% for specified performance
Reference
Current 20 30 20 30
A V
REF
= V
DD
= +5.5V
Reference Input Range
0
V
DD
0
V
DD
1
Temperature ranges are as follows: B Version: -40C to +125C, typical at 25C.
2
Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
3
DC specifications tested with the outputs unloaded unless stated otherwise.
4
Linearity is tested using a reduced code range: AD5628 (Code 48 to Code 4047), AD5648 (Code / to Code /), and AD5668 (Code 485 to 64714).
6
Guaranteed by design and characterization; not production tested.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All eight DACs powered down.
Specifications subject to change without notice.
AD5666
Preliminary Technical Data
Rev.PrA | Page 4 of 23
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
B Version
1
,
2
Conditions/Comments
Reference Input
Impedance
14.6
14.6
k
Per Dac Channel
REFERENCE
OUTPUT
Output Voltage
2.495
2.5
2.505
2.495
2.5
2.505
V
Reference TC
10
10
ppm/C
Reference Output
Impedance
2 2 k
LOGIC INPUTS
3
Input Current
1
1
A
V
INL
,
Input
Low
Voltage
0.8
0.8
V
V
DD
=+5 V
V
INH
,
Input
High
Voltage
2
2
V V
DD
=+5 V
Pin Capacitance
3
3
pF
LOGIC OUTPUTS (SDO)
3
Output Low Voltage,
V
OL
0.4
0.4
V
I
SINK
= 2 mA
Output High Voltage,
V
OH
V
DD
1
V
DD
1
I
SOURCE
= 2 mA
High Impedance
Leakage Current
1
1
A
High Impedance
Leakage Current
5
5
pF
POWER
REQUIREMENTS
V
DD
4.5
5.5
4.5
5.5
V
All Digital Inputs at 0 or V
DD
DAC Active and Excluding Load
Current
I
DD
(Normal Mode)
8
0.5
4
0.5
4
mA
V
IH
=V
DD
and V
IL
=GND
I
DD
(All Power-Down
Modes)
9
0.2
1
0.2
1
A
V
IH
=V
DD
and V
IL
=GND
POWER
EFFICIENCY
I
OUT
/I
DD
89
89
%
I
LOAD
=2 mA, V
DD
=+5 V
Preliminary Technical Data
AD5666
Rev. PrA| Page 5 of 23
AC CHARACTERISTICS
1
(V
DD
= +4.5 V to +5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; External VREF = Vdd; all
specifications T
MIN
to T
MAX
unless otherwise noted)
NOTES
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range (Y Version): 40
C to +125C; typical at +25C.
Specifications subject to change without notice.
Parameter
2
Min
Typ
Max
Unit
B Version
1
Conditions/Comments
Output Voltage Settling Time
AD5666
8
10
s
to scale settling to 2LSB
Settling Time for 1LSB Step
Slew Rate
1
V/s
Digital-to-Analog Glitch Impulse
10
nV-s
1 LSB Change Around Major Carry. See Figure 21.
Reference Feedthrough
100
dB
SDO Feedthrough
4
nV-s
Daisy Chain Mode; SDO Load is 10pF
Digital Feedthrough
0.5
nV-s
Digital Crosstalk
0.5
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2V 0.1 V p-p.
Total Harmonic Distortion
-80
dB
VREF = 2V 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density
120
nV/Hz
DAC code=8400
H
, 1kHz
100
nV/Hz
DAC code=8400
H
, 10kHz
Output Noise
15
Vp-p
0.1Hz to 10Hz;
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