AD620 Data Sheet
CONNECTION DIAGRAM
8-Lead Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
IN
R
G
V
S
+IN
R
G
+V
S
OUTPUT
REF
1
2
3
4
8
7
6
5
AD620
TOP VIEW
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Cost, Low Power
Instrumentation Amplifier
AD620
FEATURES
EASY TO USE
Gain Set with One External Resistor
(Gain Range 1 to 1000)
Wide Power Supply Range ( 2.3 V to 18 V)
Higher Performance than Three Op Amp IA Designs
Available in 8-Lead DIP and SOIC Packaging
Low Power, 1.3 mA max Supply Current
EXCELLENT DC PERFORMANCE ("B GRADE")
50 V max, Input Offset Voltage
0.6
V/ C max, Input Offset Drift
1.0 nA max, Input Bias Current
100 dB min Common-Mode Rejection Ratio (G = 10)
LOW NOISE
9 nV/
Hz, @ 1 kHz, Input Voltage Noise
0.28 V p-p Noise (0.1 Hz to 10 Hz)
EXCELLENT AC SPECIFICATIONS
120 kHz Bandwidth (G = 100)
15 s Settling Time to 0.01%
APPLICATIONS
Weigh Scales
ECG and Medical Instrumentation
Transducer Interface
Data Acquisition Systems
Industrial Process Controls
Battery Powered and Portable Equipment
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
PRODUCT DESCRIPTION
The AD620 is a low cost, high accuracy instrumentation ampli-
fier that requires only one external resistor to set gains of 1 to
0
5
10
15
20
30,000
5,000
10,000
15,000
20,000
25,000
0
TOTAL ERROR, PPM OF FULL SCALE
SUPPLY CURRENT mA
AD620A
R
G
3 OP-AMP
IN-AMP
(3 OP-07s)
Figure 1. Three Op Amp IA Designs vs. AD620
SOURCE RESISTANCE
100M
10k
1k
10M
1M
100k
10,000
0.1
100
1,000
10
1
RTI VOLTAGE NOISE
(0.1 10Hz)
V p-p
TYPICAL STANDARD
BIPOLAR INPUT
IN-AMP
AD620 SUPER ETA
BIPOLAR INPUT
IN-AMP
G = 100
Figure 2. Total Voltage Noise vs. Source Resistance
1000. Furthermore, the AD620 features 8-lead SOIC and DIP
packaging that is smaller than discrete designs, and offers lower
power (only 1.3 mA max supply current), making it a good fit
for battery powered, portable (or remote) applications.
The AD620, with its high accuracy of 40 ppm maximum
nonlinearity, low offset voltage of 50
V max and offset drift of
0.6
V/
C max, is ideal for use in precision data acquisition
systems, such as weigh scales and transducer interfaces. Fur-
thermore, the low noise, low input bias current, and low power
of the AD620 make it well suited for medical applications such
as ECG and noninvasive blood pressure monitors.
The low input bias current of 1.0 nA max is made possible with
the use of Super
eta processing in the input stage. The AD620
works well as a preamplifier due to its low input voltage noise of
9 nV/
Hz at 1 kHz, 0.28
V p-p in the 0.1 Hz to 10 Hz band,
0.1 pA/
Hz input current noise. Also, the AD620 is well suited
for multiplexed applications with its settling time of 15
s to
0.01% and its cost is low enough to enable designs with one in-
amp per channel.
AD620SPECIFICATIONS
(Typical @ +25 C, V
S
= 15 V, and R
L
= 2 k , unless otherwise noted)
AD620A
AD620B
AD620S
1
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
GAIN
G = 1 + (49.4 k/R
G
)
Gain Range
1
10,000
1
10,000
1
10,000
Gain Error
2
V
OUT
=
10 V
G = 1
0.03
0.10
0.01
0.02
0.03
0.10
%
G = 10
0.15
0.30
0.10
0.15
0.15
0.30
%
G = 100
0.15
0.30
0.10
0.15
0.15
0.30
%
G = 1000
0.40
0.70
0.35
0.50
0.40
0.70
%
Nonlinearity,
V
OUT
= 10 V to +10 V,
G = 11000
R
L
= 10 k
10
40
10
40
10
40
ppm
G = 1100
R
L
= 2 k
10
95
10
95
10
95
ppm
Gain vs. Temperature
G =1
10
10
10
ppm/
C
Gain >1
2
50
50
50
ppm/
C
VOLTAGE OFFSET
(Total RTI Error = V
OSI
+ V
OSO
/G)
Input Offset, V
OSI
V
S
=
5 V to
15 V
30
125
15
50
30
125
V
Over Temperature
V
S
=
5 V to
15 V
185
85
225
V
Average TC
V
S
=
5 V to
15 V
0.3
1.0
0.1
0.6
0.3
1.0
V/
C
Output Offset, V
OSO
V
S
=
15 V
400
1000
200
500
400
1000
V
V
S
=
5 V
1500
750
1500
V
Over Temperature
V
S
=
5 V to
15 V
2000
1000
2000
V
Average TC
V
S
=
5 V to
15 V
5.0
15
2.5
7.0
5.0
15
V/
C
Offset Referred to the
Input vs.
Supply (PSR)
V
S
=
2.3 V to
18 V
G = 1
80
100
80
100
80
100
dB
G = 10
95
120
100
120
95
120
dB
G = 100
110
140
120
140
110
140
dB
G = 1000
110
140
120
140
110
140
dB
INPUT CURRENT
Input Bias Current
0.5
2.0
0.5
1.0
0.5
2
nA
Over Temperature
2.5
1.5
4
nA
Average TC
3.0
3.0
8.0
pA/
C
Input Offset Current
0.3
1.0
0.3
0.5
0.3
1.0
nA
Over Temperature
1.5
0.75
2.0
nA
Average TC
1.5
1.5
8.0
pA/
C
INPUT
Input Impedance
Differential
10 2
10 2
10 2
G
pF
Common-Mode
10 2
10 2
10 2
G
pF
Input Voltage Range
3
V
S
=
2.3 V to
5 V
V
S
+ 1.9
+V
S
1.2
V
S
+ 1.9
+V
S
1.2
V
S
+ 1.9
+V
S
1.2
V
Over Temperature
V
S
+ 2.1
+V
S
1.3
V
S
+ 2.1
+V
S
1.3
V
S
+ 2.1
+V
S
1.3
V
V
S
=
5 V to
18 V
V
S
+ 1.9
+V
S
1.4
V
S
+ 1.9
+V
S
1.4
V
S
+ 1.9
+V
S
1.4
V
Over Temperature
V
S
+ 2.1
+V
S
1.4
V
S
+ 2.1
+V
S
1.4
V
S
+ 2.3
+V
S
1.4
V
Common-Mode Rejection
Ratio DC to 60 Hz with
I k
Source Imbalance
V
CM
= 0 V to
10 V
G = 1
73
90
80
90
73
90
dB
G = 10
93
110
100
110
93
110
dB
G = 100
110
130
120
130
110
130
dB
G = 1000
110
130
120
130
110
130
dB
OUTPUT
Output Swing
R
L
= 10 k
,
V
S
=
2.3 V to
5 V
V
S
+ 1.1
+V
S
1.2
V
S
+ 1.1
+V
S
1.2
V
S
+ 1.1
+V
S
1.2
V
Over Temperature
V
S
+ 1.4
+V
S
1.3
V
S
+ 1.4
+V
S
1.3
V
S
+ 1.6
+V
S
1.3
V
V
S
=
5 V to
18 V
V
S
+ 1.2
+V
S
1.4
V
S
+ 1.2
+V
S
1.4
V
S
+ 1.2
+V
S
1.4
V
Over Temperature
V
S
+ 1.6
+V
S
1.5
V
S
+ 1.6
+V
S
1.5
V
S
+ 2.3
+V
S
1.5
V
Short Current Circuit
18
18
18
mA
REV. E
2
AD620
AD620A
AD620B
AD620S
1
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
DYNAMIC RESPONSE
Small Signal 3 dB Bandwidth
G = 1
1000
1000
1000
kHz
G = 10
800
800
800
kHz
G = 100
120
120
120
kHz
G = 1000
12
12
12
kHz
Slew Rate
0.75
1.2
0.75
1.2
0.75
1.2
V/
s
Settling Time to 0.01%
10 V Step
G = 1100
15
15
15
s
G = 1000
150
150
150
s
NOISE
Voltage Noise, 1 kHz
Total RTI Noise
=
(e
2
ni )
+
(eno / G)
2
Input, Voltage Noise, e
ni
9
13
9
13
9
13
nV/
Hz
Output, Voltage Noise, e
no
72
100
72
100
72
100
nV/
Hz
RTI, 0.1 Hz to 10 Hz
G = 1
3.0
3.0
6.0
3.0
6.0
V p-p
G = 10
0.55
0.55
0.8
0.55
0.8
V p-p
G = 1001000
0.28
0.28
0.4
0.28
0.4
V p-p
Current Noise
f = 1 kHz
100
100
100
fA/
Hz
0.1 Hz to 10 Hz
10
10
10
pA p-p
REFERENCE INPUT
R
IN
20
20
20
k
I
IN
V
IN+
, V
REF
= 0
+50
+60
+50
+60
+50
+60
A
Voltage Range
V
S
+ 1.6
+V
S
1.6
V
S
+ 1.6
+V
S
1.6
V
S
+ 1.6
+V
S
1.6
V
Gain to Output
1
0.0001
1
0.0001
1
0.0001
POWER SUPPLY
Operating Range
4
2.3
18
2.3
18
2.3
18
V
Quiescent Current
V
S
=
2.3 V to
18 V
0.9
1.3
0.9
1.3
0.9
1.3
mA
Over Temperature
1.1
1.6
1.1
1.6
1.1
1.6
mA
TEMPERATURE RANGE
For Specified Performance
40 to +85
40 to +85
55 to +125
C
NOTES
1
See Analog Devices military data sheet for 883B tested specifications.
2
Does not include effects of external resistor R
G
.
3
One input grounded. G = 1.
4
This is defined as the same supply range which is used to specify PSR.
Specifications subject to change without notice.
REV. E
3
AD620
REV. E
4
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package:
JA
= 95
C/W
8-Lead Cerdip Package:
JA
= 110
C/W
8-Lead SOIC Package:
JA
= 155
C/W
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q) . . . . . . . . . . 65
C to +150
C
Storage Temperature Range (N, R) . . . . . . . . 65
C to +125
C
Operating Temperature Range
AD620 (A, B) . . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
AD620 (S) . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125
C
Lead Temperature Range
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . +300
C
ORDERING GUIDE
Model
Temperature Ranges Package Options*
AD620AN
40
C to +85
C
N-8
AD620BN
40
C to +85
C
N-8
AD620AR
40
C to +85
C
SO-8
AD620AR-REEL
40
C to +85
C
13" REEL
AD620AR-REEL7 40
C to +85
C
7" REEL
AD620BR
40
C to +85
C
SO-8
AD620BR-REEL
40
C to +85
C
13" REEL
AD620BR-REEL7 40
C to +85
C
7" REEL
AD620ACHIPS
40
C to +85
C
Die Form
AD620SQ/883B
55
C to +125
C
Q-8
*N = Plastic DIP; Q = Cerdip; SO = Small Outline.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
+V
S
OUTPUT
REFERENCE
+IN
V
S
IN
*FOR CHIP APPLICATIONS: THE PADS 1R
G
AND 8R
G
MUST BE CONNECTED IN PARALLEL
TO THE EXTERNAL GAIN REGISTER R
G
. DO NOT CONNECT THEM IN SERIES TO R
G
. FOR
UNITY GAIN APPLICATIONS WHERE R
G
IS NOT REQUIRED, THE PADS 1R
G
MAY SIMPLY
BE BONDED TOGETHER, AS WELL AS THE PADS 8R
G
.
4
5
6
7
8
8
R
G
*
1
1
2
3
R
G
*
0.125
(3.180)
0.0708
(1.799)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD620 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD620
REV. E
5
Typical Characteristics
(@ +25 C, V
S
= 15 V, R
L
= 2 k , unless otherwise noted)
INPUT OFFSET VOLTAGE V
20
30
40
50
40
0
+40
+80
PERCENTAGE OF UNITS
80
SAMPLE SIZE = 360
10
0
Figure 3. Typical Distribution of Input Offset Voltage
INPUT BIAS CURRENT pA
0
10
20
30
40
50
600
0
+600
PERCENTAGE OF UNITS
1200
+1200
SAMPLE SIZE = 850
Figure 4. Typical Distribution of Input Bias Current
10
20
30
40
50
200
0
+200
+400
INPUT OFFSET CURRENT pA
PERCENTAGE OF UNITS
400
0
SAMPLE SIZE = 850
Figure 5. Typical Distribution of Input Offset Current
TEMPERATURE C
INPUT BIAS CURRENT nA
+I
B
I
B
2.0
2.0
175
1.0
1.5
75
0.5
0
0.5
1.0
1.5
125
75
25
25
Figure 6. Input Bias Current vs. Temperature
CHANGE IN OFFSET VOLTAGE
V
1.5
0.5
WARM-UP TIME Minutes
2
0
0
5
1
1
4
3
2
Figure 7. Change in Input Offset Voltage vs.
Warm-Up Time
FREQUENCY Hz
1000
1
1
100k
100
10
10k
1k
100
VOLTAGE NOISE nV/
Hz
GAIN = 1
GAIN = 10
10
GAIN = 100, 1,000
GAIN = 1000
BW LIMIT
Figure 8. Voltage Noise Spectral Density vs. Frequency,
(G = 11000)
AD620Typical Characteristics
FREQUENCY Hz
1000
100
10
1
10
1000
100
CURRENT NOISE fA/
Hz
Figure 9. Current Noise Spectral Density vs. Frequency
RTI NOISE 2.0
V/DIV
TIME 1 SEC/DIV
Figure 10a. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
RTI NOISE 0.1
V/DIV
TIME 1 SEC/DIV
Figure 10b. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 11. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
100
1000
AD620A
FET INPUT
IN-AMP
SOURCE RESISTANCE
TOTAL DRIFT FROM 25
C TO 85
C, RTI
V
100,000
10
1k
10M
10,000
10k
1M
100k
Figure 12. Total Drift vs. Source Resistance
FREQUENCY Hz
CMR dB
+160
0
1M
+80
+40
1
+60
0.1
+140
+100
+120
100k
10k
1k
100
10
G = 1000
G = 100
G = 10
G = 1
+20
Figure 13. CMR vs. Frequency, RTI, Zero to 1 k
Source
Imbalance
REV. E
6
AD620
REV. E
7
FREQUENCY Hz
PSR dB
160
1M
80
40
1
60
0.1
140
100
120
100k
10k
1k
100
10
20
G = 1000
G = 100
G = 10
G = 1
180
Figure 14. Positive PSR vs. Frequency, RTI (G = 11000)
FREQUENCY Hz
PSR dB
160
1M
80
40
1
60
0.1
140
100
120
100k
10k
1k
100
10
20
180
G = 10
G = 100
G = 1
G = 1000
Figure 15. Negative PSR vs. Frequency, RTI (G = 11000)
1000
100
10M
100
1
1k
10
100k
1M
10k
FREQUENCY Hz
GAIN V/V
0.1
Figure 16. Gain vs. Frequency
OUTPUT VOLTAGE Volts p-p
FREQUENCY Hz
35
0
1M
15
5
10k
10
1k
30
20
25
100k
G = 10, 100, 1000
G = 1
G = 1000
G = 100
BW LIMIT
Figure 17. Large Signal Frequency Response
INPUT VOLTAGE LIMIT Volts
(REFERRED TO SUPPLY VOLTAGES)
20
+1.0
+0.5
5
0
+1.5
1.5
1.0
0.5
15
10
SUPPLY VOLTAGE Volts
+V
S
0.0
V
S
+0.0
Figure 18. Input Voltage Range vs. Supply Voltage, G = 1
20
+1.0
+0.5
5
0
+1.5
1.5
1.0
0.5
15
10
SUPPLY VOLTAGE Volts
R
L
= 10k
R
L
= 2k
R
L
= 10k
OUTPUT VOLTAGE SWING Volts
(REFERRED TO SUPPLY VOLTAGES)
R
L
= 2k
+V
S
0.0
V
S
+0.0
Figure 19. Output Voltage Swing vs. Supply Voltage,
G = 10
AD620
REV. E
8
OUTPUT VOLTAGE SWING Volts p-p
LOAD RESISTANCE
30
0
0
10k
20
10
100
1k
V
S
= 15V
G = 10
Figure 20. Output Voltage Swing vs. Load Resistance
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21. Large Signal Pulse Response and Settling Time
G = 1 (0.5 mV = 0.01%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22. Small Signal Response, G = 1, R
L
= 2 k
,
C
L
= 100 pF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23. Large Signal Response and Settling Time,
G = 10 (0.5 mV = 001%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24. Small Signal Response, G = 10, R
L
= 2 k
,
C
L
= 100 pF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25. Large Signal Response and Settling Time,
G = 100 (0.5 mV = 0.01%)
AD620
REV. E
9
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26. Small Signal Pulse Response, G = 100,
R
L
= 2 k
, C
L
= 100 pF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27. Large Signal Response and Settling Time,
G = 1000 (0.5 mV = 0.01%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28. Small Signal Pulse Response, G = 1000,
R
L
= 2 k
, C
L
= 100 pF
OUTPUT STEP SIZE Volts
SETTLING TIME
s
TO 0.01%
TO 0.1%
20
0
0
20
15
5
5
10
10
15
Figure 29. Settling Time vs. Step Size (G = 1)
GAIN
SETTLING TIME
s
1000
1
1
1000
100
10
10
100
Figure 30. Settling Time to 0.01% vs. Gain, for a 10 V Step
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31a. Gain Nonlinearity, G = 1, R
L
= 10 k
(10
V = 1 ppm)
AD620
REV. E
10
V
B
V
S
A1
A2
A3
C2
R
G
R1
R2
GAIN
SENSE
GAIN
SENSE
R3
400
10k
10k
I2
I1
10k
REF
10k
+IN
IN
20 A
20 A
R4
400
OUTPUT
C1
Q2
Q1
Figure 33. Simplified Schematic of AD620
THEORY OF OPERATION
The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately (to
0.15% at G = 100) with only one resistor. Monolithic construc-
tion and laser wafer trimming allow the tight matching and
tracking of circuit components, thus ensuring the high level of
performance inherent in this circuit.
The input transistors Q1 and Q2 provide a single differential-
pair bipolar input for high precision (Figure 33), yet offer 10
lower Input Bias Current thanks to Super
eta processing. Feed-
back through the Q1-A1-R1 loop and the Q2-A2-R2 loop main-
tains constant collector current of the input devices Q1, Q2
thereby impressing the input voltage across the external gain
setting resistor R
G
. This creates a differential gain from the
inputs to the A1/A2 outputs given by G = (R1 + R2)/R
G
+ 1.
The unity-gain subtracter A3 removes any common-mode sig-
nal, yielding a single-ended output referred to the REF pin
potential.
The value of R
G
also determines the transconductance of the
preamp stage. As R
G
is reduced for larger gains, the transcon-
ductance increases asymptotically to that of the input transistors.
This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gain-
related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The
input voltage noise is reduced to a value of 9 nV/
Hz, deter-
mined mainly by the collector current and base resistance of the
input devices.
The internal gain resistors, R1 and R2, are trimmed to an abso-
lute value of 24.7 k
, allowing the gain to be programmed
accurately with a single external resistor.
The gain equation is then
G
=
49.4 k
R
G
+
1
so that
R
G
=
49.4 k
G
-
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31b. Gain Nonlinearity, G = 100, R
L
= 10 k
(100
V = 10 ppm)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 31c. Gain Nonlinearity, G = 1000, R
L
= 10 k
(1 mV = 100 ppm)
AD620
V
OUT
G=1
G=1000
49.9
10k *
1k
10T
10k
499
G=10
G=100
5.49k
+V
S
11k
1k
100
100k
INPUT
10V p-p
V
S
*ALL RESISTORS 1% TOLERANCE
7
1
2
3
8
6
4
5
Figure 32. Settling Time Test Circuit
AD620
REV. E
11
Make vs. Buy: A Typical Bridge Application Error Budget
The AD620 offers improved performance over "homebrew"
three op amp IA designs, along with smaller size, fewer compo-
nents and 10
lower supply current. In the typical application,
shown in Figure 34, a gain of 100 is required to amplify a bridge
output of 20 mV full scale over the industrial temperature range
of 40
C to +85
C. The error budget table below shows how to
calculate the effect various error sources have on circuit accuracy.
Regardless of the system in which it is being used, the AD620
provides greater accuracy, and at low power and price. In simple
R = 350
+10V
PRECISION BRIDGE TRANSDUCER
AD620A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100
"HOMEBREW" IN-AMP, G = 100
*0.02% RESISTOR MATCH, 3PPM/ C TRACKING
**DISCRETE 1% RESISTOR, 100PPM/ C TRACKING
SUPPLY CURRENT = 15mA MAX
100 **
10k *
10k **
10k *
10k *
10k **
10k *
SUPPLY CURRENT = 1.3mA MAX
OP07D
OP07D
OP07D
AD620A
R
G
499
REFERENCE
R = 350
R = 350
R = 350
Figure 34. Make vs. Buy
Table I. Make vs. Buy Error Budget
AD620 Circuit
"Homebrew" Circuit
Error, ppm of Full Scale
Error Source
Calculation
Calculation
AD620
Homebrew
ABSOLUTE ACCURACY at T
A
= +25
C
Input Offset Voltage,
V
125
V/20 mV
(150
V
2)/20 mV
1
6,250
10,607
Output Offset Voltage,
V
1000
V/100/20 mV
((150
V
2)/100)/20 mV
14,
500
10,
150
Input Offset Current, nA
2 nA
350
/20 mV
(6 nA
350
)/20 mV
14,1
18
14,1
53
CMR, dB
110 dB
3.16 ppm, 5 V/20 mV (0.02% Match 5 V)/20 mV/100
14,
791
10,
500
Total Absolute Error
1
7,558
11,310
DRIFT TO +85
C
Gain Drift, ppm/
C
(50 ppm + 10 ppm)
60
C
100 ppm/
C Track
60
C
1
3,600
1
6,000
Input Offset Voltage Drift,
V/
C
1
V/
C
60
C/20 mV
(2.5
V/
C
2
60
C)/20 mV
1
3,000
10,607
Output Offset Voltage Drift,
V/
C
15
V/
C
60
C/100/20 mV
(2.5
V/
C
2 60
C)/100/20 mV
14,
450
10,
150
Total Drift Error
1
7,050
16,757
RESOLUTION
Gain Nonlinearity, ppm of Full Scale
40 ppm
40 ppm
14,1
40
10,1
40
Typ 0.1 Hz10 Hz Voltage Noise,
V p-p 0.28
V p-p/20 mV
(0.38
V p-p
2)/20 mV
141,
14
13,1
27
Total Resolution Error
14,1
54
101,
67
Grand Total Error
14,662
28,134
G = 100, V
S
=
15 V.
(All errors are min/max and referred to input.)
systems, absolute accuracy and drift errors are by far the most
significant contributors to error. In more complex systems with
an intelligent processor, an autogain/autozero cycle will remove all
absolute accuracy and drift errors leaving only the resolution
errors of gain nonlinearity and noise, thus allowing full 14-bit
accuracy.
Note that for the homebrew circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by
2. This
is because a three op amp type in-amp has two op amps at its
inputs, both contributing to the overall input error.
AD620
REV. E
12
3k
+5V
DIGITAL
DATA
OUTPUT
ADC
REF
IN
AGND
20k
10k
20k
AD620B
G=100
1.7mA
0.10mA
0.6mA
MAX
499
3k
3k
3k
2
1
8
3
7
6
5
4
1.3mA
MAX
AD705
Figure 35. A Pressure Monitor Circuit which Operates on a +5 V Single Supply
Pressure Measurement
Although useful in many bridge applications such as weigh
scales, the AD620 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small size and
low power become more significant.
Figure 35 shows a 3 k
pressure transducer bridge powered
from +5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the
signal to be conditioned for only 3.8 mA of total supply current.
Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic non-
invasive blood pressure measurement.
Medical ECG
The low current noise of the AD620 allows its use in ECG
monitors (Figure 36) where high source resistances of 1 M
or
higher are not uncommon. The AD620's low power, low supply
voltage requirements, and space-saving 8-lead mini-DIP and
SOIC package offerings make it an excellent choice for battery
powered data recorders.
Furthermore, the low bias currents and low current noise
coupled with the low voltage noise of the AD620 improve the
dynamic range for better performance.
The value of capacitor C1 is chosen to maintain stability of the
right leg drive loop. Proper safeguards, such as isolation, must
be added to this circuit to protect the patient from possible
harm.
G = 7
AD620A
0.03Hz
HIGH
PASS
FILTER
OUTPUT
1V/mV
+3V
3V
R
G
8.25k
24.9k
24.9k
AD705J
G = 143
C1
1M
R4
10k
R1
R3
R2
OUTPUT
AMPLIFIER
PATIENT/CIRCUIT
PROTECTION/ISOLATION
Figure 36. A Medical ECG Monitor Circuit
AD620
REV. E
13
Precision V-I Converter
The AD620, along with another op amp and two resistors, makes
a precision current source (Figure 37). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
V
X
of the AD620 appears across R1, which converts it to a
current. This current less only, the input bias current of the op
amp, then flows out to the load.
AD620
R
G
V
S
V
IN+
V
IN
LOAD
R1
I
L
V
x
I =
L
R1
=
IN+
[(V ) (V )] G
IN
R1
6
5
+ V
X
4
2
1
8
3
7
+V
S
AD705
Figure 37. Precision Voltage-to-Current Converter
(Operates on 1.8 mA,
3 V)
GAIN SELECTION
The AD620's gain is resistor programmed by R
G
, or more pre-
cisely, by whatever impedance appears between Pins 1 and 8.
The AD620 is designed to offer accurate gains using 0.1%1%
resistors. Table II shows required values of R
G
for various gains.
Note that for G = 1, the R
G
pins are unconnected (R
G
=
). For
any arbitrary gain R
G
can be calculated by using the formula:
R
G
=
49.4 k
G
-
1
To minimize gain error, avoid high parasitic resistance in series
with R
G
; to minimize gain drift, R
G
should have a low TC--less
than 10 ppm/
C--for the best performance.
Table II. Required Values of Gain Resistors
1% Std Table
Calculated
0.1% Std Table
Calculated
Value of R
G
,
Gain
Value of R
G
,
Gain
49.9 k
1.990
49.3 k
2.002
12.4 k
4.984
12.4 k
4.984
5.49 k
9.998
5.49 k
9.998
2.61 k
19.93
2.61 k
19.93
1.00 k
50.40
1.01 k
49.91
499
100.0
499
100.0
249
199.4
249
199.4
100
495.0
98.8
501.0
49.9
991.0
49.3
1,003
INPUT AND OUTPUT OFFSET VOLTAGE
The low errors of the AD620 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains and the output errors dominate at low gains. The
total V
OS
for a given gain is calculated as:
Total Error RTI = input error + (output error/G)
Total Error RTO = (input error
G) + output error
REFERENCE TERMINAL
The reference terminal potential defines the zero output voltage,
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output, with an allowable range
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.
INPUT PROTECTION
The AD620 features 400
of series thin film resistance at its
inputs, and will safely withstand input overloads of up to
15 V
or
60 mA for several hours. This is true for all gains, and power
on and off, which is particularly important since the signal
source and amplifier may be powered separately. For longer
time periods, the current should not exceed 6 mA (I
IN
V
IN
/400
). For input overloads beyond the supplies, clamping
the inputs to the supplies (using a low leakage diode such as an
FD333) will reduce the required resistance, yielding lower
noise.
RF INTERFERENCE
All instrumentation amplifiers can rectify out of band signals,
and when amplifying small signals, these rectified voltages act as
small dc offset errors. The AD620 allows direct access to the
input transistor bases and emitters enabling the user to apply
some first order filtering to unwanted RF signals (Figure 38),
where RC 1/(2
f) and where f
the bandwidth of the
AD620; C
150 pF. Matching the extraneous capacitance at
Pins 1 and 8 and Pins 2 and 3 helps to maintain high CMR.
IN
1
2
3
4
5
6
7
8
R
R
+IN
C
C
R
G
Figure 38. Circuit to Attenuate RF Interference
AD620
REV. E
14
COMMON-MODE REJECTION
Instrumentation amplifiers like the AD620 offer high CMR,
which is a measure of the change in output voltage when both
inputs are changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a speci-
fied source imbalance.
For optimal CMR the reference terminal should be tied to a low
impedance point, and differences in capacitance and resistance
should be kept to a minimum between the two inputs. In many
applications shielded cables are used to minimize noise, and for
best CMR over frequency the shield should be properly driven.
Figures 39 and 40 show active data guards that are configured
to improve ac common-mode rejections by "bootstrapping" the
capacitances of input cable shields, thus minimizing the capaci-
tance mismatch between the inputs.
REFERENCE
V
OUT
AD620
100
100
INPUT
+ INPUT
AD648
R
G
V
S
+V
S
V
S
Figure 39. Differential Shield Driver
100
INPUT
+ INPUT
REFERENCE
V
OUT
AD620
V
S
+V
S
2
R
G
2
R
G
AD548
Figure 40. Common-Mode Shield Driver
GROUNDING
Since the AD620 output voltage is developed with respect to the
potential on the reference terminal, it can solve many grounding
problems by simply tying the REF pin to the appropriate "local
ground."
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 41). It would be conve-
nient to use a single ground line; however, current through
ground wires and PC runs of the circuit card can cause hun-
dreds of millivolts of error. Therefore, separate ground returns
should be provided to minimize the current flow from the sensi-
tive points to the system ground. These ground returns must be
tied together at some point, usually best at the ADC package as
shown.
DIGITAL P.S.
+5V
C
ANALOG P.S.
+15V C 15V
AD574A
DIGITAL
DATA
OUTPUT
+
1 F
AD620
0.1 F
AD585
S/H
ADC
0.1 F
1 F 1 F
Figure 41. Basic Grounding Practice
AD620
REV. E
15
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
for these currents; therefore, when amplifying "floating" input
V
OUT
AD620
INPUT
R
G
TO POWER
SUPPLY
GROUND
REFERENCE
+ INPUT
+V
S
V
S
LOAD
Figure 42a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figure 42.
Refer to the Instrumentation Amplifier Application Guide (free
from Analog Devices) for more information regarding in amp
applications.
V
OUT
INPUT
+ INPUT
R
G
LOAD
TO POWER
SUPPLY
GROUND
REFERENCE
+V
S
V
S
AD620
Figure 42b. Ground Returns for Bias Currents with
Thermocouple Inputs
100k
V
OUT
AD620
INPUT
+ INPUT
R
G
LOAD
TO POWER
SUPPLY
GROUND
REFERENCE
100k
V
S
+V
S
Figure 42c. Ground Returns for Bias Currents with AC Coupled Inputs
AD620
REV. E
16
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
8
1
4
5
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
Cerdip (Q-8) Package
8
1
4
5
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.4)
MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.405 (10.29)
MAX
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SOIC (SO-8) Package
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
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