CONNECTION DIAGRAM
8-Lead Plastic Mini-DIP (N), Cerdip (Q)
and SOIC (R) Packages
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
G = 10/100
IN
+IN
G = 10/100
+V
S
OUTPUT
REF
V
S
AD621
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Drift, Low Power
Instrumentation Amplifier
AD621
FEATURES
EASY TO USE
Pin-Strappable Gains of 10 and 100
All Errors Specified for Total System Performance
Higher Performance than Discrete In Amp Designs
Available in 8-Lead DIP and SOIC
Low Power, 1.3 mA Max Supply Current
Wide Power Supply Range ( 2.3 V to 18 V)
EXCELLENT DC PERFORMANCE
0.15% Max, Total Gain Error
5 ppm/ C, Total Gain Drift
125 V Max, Total Offset Voltage
1.0 V/ C Max, Offset Voltage Drift
LOW NOISE
9 nV/
Hz, @ 1 kHz, Input Voltage Noise
0.28 V p-p Noise (0.1 Hz to 10 Hz)
EXCELLENT AC SPECIFICATIONS
800 kHz Bandwidth (G = 10), 200 kHz (G = 100)
12 s Settling Time to 0.01%
APPLICATIONS
Weigh Scales
Transducer Interface and Data Acquisition Systems
Industrial Process Controls
Battery-Powered and Portable Equipment
PRODUCT DESCRIPTION
The AD621 is an easy to use, low cost, low power, high accu-
racy instrumentation amplifier that is ideally suited for a wide
range of applications. Its unique combination of high perfor-
mance, small size and low power, outperforms discrete in amp
implementations. High functionality, low gain errors, and low
SUPPLY CURRENT mA
30,000
25,000
0
0
20
5
T
O
T
A
L ERR
OR,
ppm OF FULL SCALE
10
15
20,000
15,000
10,000
5,000
AD621A
3
OP
AMP
IN
AMP
(3
OP
07
S
)
Figure 1. Three Op Amp IA Designs vs. AD621
gain drift errors are achieved by the use of internal gain setting
resistors. Fixed gains of 10 and 100 can easily be set via external
pin strapping. The AD621 is fully specified as a total system,
therefore, simplifying the design process.
For portable or remote applications, where power dissipation,
size, and weight are critical, the AD621 features a very low
supply current of 1.3 mA max and is packaged in a compact
8-lead SOIC, 8-lead plastic DIP or 8-lead cerdip. The AD621
also excels in applications requiring high total accuracy, such
as precision data acquisition systems used in weigh scales and
transducer interface circuits. Low maximum error specifications
including nonlinearity of 10 ppm, gain drift of 5 ppm/
C, 50 V
offset voltage, and 0.6
V/C offset drift ("B" grade), make
possible total system performance at a lower cost than has been
previously achieved with discrete designs or with other mono-
lithic instrumentation amplifiers.
When operating from high source impedances, as in ECG and
blood pressure monitors, the AD621 features the ideal combina-
tion of low noise and low input bias currents. Voltage noise is
specified as 9 nV/
Hz at 1 kHz and 0.28 V p-p from 0.1 Hz to
10 Hz. Input current noise is also extremely low at 0.1 pA/
Hz.
The AD621 outperforms FET input devices with an input bias
current specification of 1.5 nA max over the full industrial tem-
perature range.
SOURCE RESISTANCE
10,000
0.1
1k
100M
10k
TOTAL INPUT VOLTAGE NOISE, G = 100
Vp-p
(0.1
10Hz)
100k
10M
1,000
100
10
1
1M
TYPICAL STANDARD
BIPOLAR INPUT
IN AMP
AD621 SUPER ETA
BIPOLAR INPUT
IN AMP
Figure 2. Total Voltage Noise vs. Source Resistance
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
AD621SPECIFICATIONS
Gain = 10
AD621A
AD621B
AD621S
1
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
GAIN
Gain Error
V
OUT
=
10 V
0.15
0.05
0.15
%
Nonlinearity,
V
OUT
= 10 V to +10 V
R
L
= 2 k
2
10
2
10
2
10
ppm of FS
Gain vs. Temperature
1.5
5
1.5
5
1
5
ppm/
C
TOTAL VOLTAGE OFFSET
Offset (RTI)
V
S
=
15 V
75
250
50
125
75
250
V
Over Temperature
V
S
=
5 V to 15 V
400
215
500
V
Average TC
V
S
=
5 V to 15 V
1.0
2.5
0.6
1.5
1.0
2.5
V/C
Offset Referred to the
Input vs. Supply (PSR)
2
V
S
=
2.3 V to 18 V 95
120
100
120
95
120
dB
Total NOISE
Voltage Noise (RTI)
1 kHz
13
17
13
17
13
17
nV/
Hz
RTI
0.1 Hz to 10 Hz
0.55
0.55
0.8
0.55
0.8
V p-p
Current Noise
f = 1 kHz
100
100
100
fA/
Hz
0.1 Hz10 Hz
10
10
10
pA p-p
INPUT CURRENT
V
S
=
15 V
Input Bias Current
0.5
2.0
0.5
1.0
0.5
2
nA
Over Temperature
2.5
1.5
4
nA
Average TC
3.0
3.0
8.0
pA/
C
Input Offset Current
0.3
1.0
0.3
0.5
0.3
1.0
nA
Over Temperature
1.5
0.75
2.0
nA
Average TC
1.5
1.5
8.0
pA/
C
INPUT
Input Impedance
Differential
10 2
10 2
10 2
G
pF
Common-Mode
10 2
10 2
10 2
G
pF
Input Voltage Range
3
V
S
=
2.3 V to 5 V
V
S
+ 1.9
+V
S
1.2 V
S
+ 1.9
+V
S
1.2
V
S
+ 1.9
+V
S
1.2
V
Over Temperature
V
S
+ 2.1
+V
S
1.3 V
S
+ 2.1
+V
S
1.3
V
S
+ 2.1
+V
S
1.3
V
V
S
=
5 V to 18 V
V
S
+ 1.9
+V
S
1.4 V
S
+ 1.9
+V
S
1.4
V
S
+ 1.9
+V
S
1.4
V
Over Temperature
V
S
+ 2.1
+V
S
1.4 V
S
+ 2.1
+V
S
1.4
V
S
+ 2.3
+V
S
1.4
V
Common-Mode Rejection
Ratio DC to 60 Hz with
1 k
Source Imbalance
V
CM
= 0 V to
10 V
93
110
100
110
93
110
dB
OUTPUT
Output Swing
R
L
= 10 k
,
V
S
=
2.3 V to 5 V
V
S
+ 1.1
+V
S
1.2 V
S
+ 1.1
+V
S
1.2
V
S
+ 1.1
+V
S
1.2
V
Over Temperature
V
S
+ 1.4
+V
S
1.3 V
S
+ 1.4
+V
S
1.3
V
S
+ 1.6
+V
S
1.3
V
V
S
=
5 V to 18 V
V
S
+ 1.2
+V
S
1.4 V
S
+ 1.2
+V
S
1.4
V
S
+ 1.2
+V
S
1.4
V
Over Temperature
V
S
+ 1.6
+V
S
1.5 V
S
+ 1.6
+V
S
1.5
V
S
+ 2.3
+V
S
1.5
V
Short Current Circuit
18
18
18
mA
DYNAMIC RESPONSE
Small Signal,
3 dB Bandwidth
800
800
800
kHz
Slew Rate
0.75
1.2
0.75
1.2
0.75
1.2
V/
s
Settling Time to 0.01%
10 V Step
12
12
12
s
REFERENCE INPUT
R
IN
20
20
20
k
I
IN
V
IN
+, V
REF
= 0
50
60
50
60
+50
+60
A
Voltage Range
V
S
+ 1.6
+V
S
1.6 V
S
+ 1.6
+V
S
1.6
V
S
+ 1.6
+V
S
1.6
V
Gain to Output
1
0.0001
1
0.0001
1
0.0001
POWER SUPPLY
Operating Range
2.3
18
2.3
18
2.3
18
V
Quiescent Current
V
S
=
2.3 V to 18 V
0.9
1.3
0.9
1.3
0.9
1.3
mA
Over Temperature
1.1
1.6
1.1
1.6
1.1
1.6
mA
TEMPERATURE RANGE
For Specified Performance
40 to +85
40 to +85
55 to +125
C
NOTES
1
See Analog Devices' military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSRR is defined.
3
Input Voltage Range = CMV + (Gain
V
DIFF
).
Specifications subject to change without notice.
(Typical @ 25 C, V
S
= 15 V, and R
L
= 2 k
, unless otherwise noted.)
REV. B
2
AD621A
AD621B
AD621S
1
Model
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
GAIN
Gain Error
V
OUT
=
10 V
0.15
0.05
0.15
%
Nonlinearity,
V
OUT
= 10 V to +10 V
R
L
= 2 k
2
10
2
10
2
10
ppm of FS
Gain vs. Temperature
1
5
1
5
1
5
ppm/
C
TOTAL VOLTAGE OFFSET
Offset (RTI)
V
S
=
15 V
35
125
25
50
35
125
V
Over Temperature
V
S
=
5 V to 15 V
185
215
225
V
Average TC
V
S
=
5 V to 15 V
0.3
1.0
0.1
0.6
0.3
1.0
V/C
Offset Referred to the
Input vs. Supply (PSR)
2
V
S
=
2.3 V to 18 V 110
140
120
140
110
140
dB
Total NOISE
Voltage Noise (RTI)
1 kHz
9
13
9
13
9
13
nV/
Hz
RTI
0.1 Hz to 10 Hz
0.28
0.28
0.4
0.28
0.4
V p-p
Current Noise
f = 1 kHz
100
100
100
fA/
Hz
0.1 Hz10 Hz
10
10
10
pA p-p
INPUT CURRENT
V
S
=
15 V
Input Bias Current
0.5
2.0
0.5
1.0
0.5
2
nA
Over Temperature
2.5
1.5
4
nA
Average TC
3.0
3.0
8.0
pA/
C
Input Offset Current
0.3
1.0
0.3
0.5
0.3
1.0
nA
Over Temperature
1.5
0.75
2.0
nA
Average TC
1.5
1.5
8.0
pA/
C
INPUT
Input Impedance
Differential
10 2
10 2
10 2
G
pF
Common-Mode
10 2
10 2
10 2
G
pF
Input Voltage Range
3
V
S
=
2.3 V to 5 V
V
S
+ 1.9
+V
S
1.2 V
S
+ 1.9
+V
S
1.2
V
S
+ 1.9
+V
S
1.2
V
Over Temperature
V
S
+ 2.1
+V
S
1.3 V
S
+ 2.1
+V
S
1.3
V
S
+ 2.1
+V
S
1.3
V
V
S
=
5 V to 18 V
V
S
+ 1.9
+V
S
1.4 V
S
+ 1.9
+V
S
1.4
V
S
+ 1.9
+V
S
1.4
V
Over Temperature
V
S
+ 2.1
+V
S
1.4 V
S
+ 2.1
+V
S
1.4
V
S
+ 2.3
+V
S
1.4
V
Common-Mode Rejection
Ratio DC to 60 Hz with
1 k
Source Imbalance
V
CM
= 0 V to
10 V
110
130
120
130
110
130
dB
OUTPUT
Output Swing
R
L
= 10 k
,
V
S
=
2.3 V to 5 V
V
S
+ 1.1
+V
S
1.2 V
S
+ 1.1
+V
S
1.2
V
S
+ 1.1
+V
S
1.2
V
Over Temperature
V
S
+ 1.4
+V
S
1.3 V
S
+ 1.4
+V
S
1.3
V
S
+ 1.6
+V
S
1.3
V
V
S
=
5 V to 18 V
V
S
+ 1.2
+V
S
1.4 V
S
+ 1.2
+V
S
1.4
V
S
+ 1.2
+V
S
1.4
V
Over Temperature
V
S
+ 1.6
+V
S
1.5 V
S
+ 1.6
+V
S
1.5
V
S
+ 2.3
+V
S
1.5
V
Short Current Circuit
18
18
18
mA
DYNAMIC RESPONSE
Small Signal,
3 dB Bandwidth
200
200
200
kHz
Slew Rate
0.75
1.2
0.75
1.2
0.75
1.2
V/
s
Settling Time to 0.01%
10 V Step
12
12
12
s
REFERENCE INPUT
R
IN
20
20
20
k
I
IN
V
IN
+, V
REF
= 0
50
60
50
60
50
60
A
Voltage Range
V
S
+ 1.6
+V
S
1.6 V
S
+ 1.6
+V
S
1.6
V
S
+ 1.6
+V
S
1.6
V
Gain to Output
1
0.0001
1
0.0001
1
0.0001
POWER SUPPLY
Operating Range
2.3
18
2.3
18
2.3
18
V
Quiescent Current
V
S
=
2.3 V to 18 V
0.9
1.3
0.9
1.3
0.9
1.3
mA
Over Temperature
1.1
1.6
1.1
1.6
1.1
1.6
mA
TEMPERATURE RANGE
For Specified Performance
40 to +85
40 to +85
55 to +125
C
NOTES
1
See Analog Devices' military data sheet for 883B tested specifications.
2
This is defined as the supply range over which PSEE is defined.
3
Input Voltage Range = CMV + (Gain
V
DIFF
).
Specifications subject to change without notice.
Gain = 100
(Typical @ 25 C, V
S
= 15 V, and R
L
= 2 k
, unless otherwise noted.)
AD621
REV. B
3
AD621
REV. B
4
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air:
8-Lead Plastic Package:
JA
= 95
C/W
8-Lead Cerdip Package:
JA
= 110
C/W
8-Lead SOIC Package:
JA
= 155
C/W
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . 650 mW
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .
25 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (Q) . . . . . . . . . 65
C to +150C
Storage Temperature Range (N, R) . . . . . . . 65
C to +125C
Operating Temperature Range
AD621 (A, B) . . . . . . . . . . . . . . . . . . . . . . 40
C to +85C
AD621 (S) . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125C
Lead Temperature Range
(Soldering 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . 300
C
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without
detection. Although the AD621 features proprietary ESD pro-
tection circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
1
AD621AN
40
C to +85C 8-Lead Plastic DIP
N-8
AD621BN
40
C to +85C 8-Lead Plastic DIP
N-8
AD621AR
40
C to +85C 8-Lead Plastic SOIC R-8
AD621BR
40
C to +85C 8-Lead Plastic SOIC R-8
AD621SQ/883B
2
55
C to +125C 8-Lead Cerdip
Q-8
AD621ACHIPS
40
C to +85C Die
NOTES
1
N = Plastic DIP; Q = Cerdip; R = SOIC.
2
See Analog Devices' military data sheet for 883B specifications.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
1.125 (3.57)
0.0708
(2.545)
5
REFERENCE
RG 1
RG 8
+V
S
7
4 V
S
2
IN
3
+IN
OUTPUT
6
Typical Performance CharacteristicsAD621
INPUT OFFSET VOLTAGE V
50
40
0
200
100
PERCENTAGE OF UNITS
0
+100
+200
30
20
10
SAMPLE SIZE = 90
TPC 1. Typical Distribution of V
OS,
Gain = 10
INPUT OFFSET VOLTAGE V
50
40
0
80
40
PERCENTAGE OF UNITS
0
+40
+80
30
20
10
SAMPLE SIZE = 90
TPC 2. Typical Distribution of V
OS
, Gain = 100
INPUT OFFSET CURRENT pA
50
40
0
400
200
PERCENT
A
G
E OF UNITS
0
+200
+400
30
20
10
SAMPLE SIZE = 90
TPC 3. Typical Distribution of Input Offset Current
REV. B
5
INPUT BIAS CURRENT pA
50
40
0
800
400
PERCENT
A
G
E OF UNITS
0
+400
+800
30
20
10
SAMPLE SIZE = 90
TPC 4. Typical Distribution of Input Bias Current
WARM-UP TIME Minutes
2.0
0
0
5
1
CHANGE IN OFFSET VOLTAGE
V
2
3
1.5
1.0
0.5
4
TPC 5. Change in Input Offset Voltage vs. Warm-Up Time
FREQUENCY Hz
1000
100
1
1
100k
10
VOLTAGE NOISE
nV/
Hz
100
1k
10k
10
GAIN = 10
GAIN = 100
TPC 6. Voltage Noise Spectral Density
AD621
REV. B
6
FREQUENCY Hz
1000
100
1
10
CURRENT NOISE
nV/
Hz
100
1000
10
TPC 7. Current Noise Spectral Density vs. Frequency
TIME 1 sec/div
RTI NOISE
0.2
V/div
TPC 8a. 0.1 Hz to 10 Hz RTI Voltage Noise, Gain = 10
TIME 1 sec/div
RTI NOISE
0.1
V/div
TPC 8b. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100
10
0%
100
90
1s
100mV
TPC 9. 0.1 Hz to 10 Hz Current Noise, 5 pA per Vertical
Div, 1 Second per Horizontal Div
100
1000
AD621A
FET INPUT
IN AMP
SOURCE RESISTANCE
TOTAL DRIFT FROM 25
C TO 85
C, RTI
V
100,000
10
1k
10M
10,000
10k
1M
100k
TPC 10. Total Drift vs. Source Resistance
FREQUENCY Hz
0.1
1M
1
10
100
1k
10k
100k
160
0
CMR
dB
140
80
60
40
20
120
100
GAIN = 100
GAIN = 10
TPC 11. CMR vs. Frequency, RTI, for a Zero to 1 k
Source Imbalance
AD621
REV. B
7
FREQUENCY Hz
PSR
dB
160
1M
80
40
1
60
0.1
140
100
120
100k
10k
1k
100
10
20
G = 100
G = 10
180
TPC 12. Positive PSR vs. Frequency
FREQUENCY Hz
PSR
dB
160
1M
80
40
1
60
0.1
140
100
120
100k
10k
1k
100
10
20
G = 100
G = 10
180
TPC 13. Negative PSR vs. Frequency
1000
100
10M
100
1
1k
10
100k
1M
10k
FREQUENCY Hz
CLOSED-LOOP GAIN
V/V
0.1
TPC 14. Closed-Loop Gain vs. Frequency
OUTPUT VOLTAGE
Volts p-p
FREQUENCY Hz
35
0
1M
15
5
10k
10
1k
30
20
25
100k
G = 10 & 100
TPC 15. Large Signal Frequency Response
INPUT VOLTAGE LIMIT
Volts
(REFERRED TO SUPPLY VOLTAGES)
20
+1.0
+0.5
5
0
+1.5
1.5
1.0
0.5
15
10
SUPPLY VOLTAGE Volts
0.0
+0.0
+V
S
V
S
TPC 16. Input Voltage Range vs. Supply Voltage
INPUT VOLTAGE LIMIT
Volts
(REFERRED TO SUPPLY VOLTAGES)
20
+1.0
+0.5
5
0
+1.5
1.5
1.0
0.5
15
10
SUPPLY VOLTAGE Volts
0.0
+0.0
+V
S
V
S
R
L
= 10k
R
L
= 2k
R
L
= 10k
R
L
= 2k
TPC 17. Output Voltage Swing vs. Supply Voltage,
G = 10
AD621
REV. B
8
OUTPUT VOLTAGE SWING
Volts p-p
LOAD RESISTANCE
30
0
0
10k
20
10
100
1k
V
S
= 15V
G = 10
TPC 18. Output Voltage Swing vs. Resistive Load
100
90
10 s
5V
1mV
10
0%
TPC 19. Large Signal Pulse Response and Settling
Time Gain, G = 10 (0.5 mV = 0.01%), R
L
= 1 k
,
C
L
= 100 pF
10
100
90
10 s
20mV
0%
TPC 20. Small Signal Pulse Response, G = 10,
R
L
= 1 k
, C
L
= 100 pF
10
0%
100
90
10 s
5V
1mV
TPC 21. Large Signal Pulse Response and Settling
Time, G = 100 (0.5 mV = 0.1%), R
L
= 2 k
, C
L
= 100 pF
10
0%
100
90
10 s
20mV
TPC 22. Small Signal Pulse Response, G = 100,
R
L
= 2 k
, C
L
= 100 pF
OUTPUT STEP SIZE Volts
SETTLING TIME
s
20
0
0
20
15
5
5
10
10
15
TO 0.01%
TO 0.1%
TPC 23. Settling Time vs. Step Size, G = 10
AD621
REV. B
9
OUTPUT STEP SIZE Volts
SETTLING TIME
s
20
0
0
20
15
5
5
10
10
15
TO 0.01%
TO 0.1%
TPC 24. Settling Time vs. Step Size, Gain = 100
TEMPERATURE C
INPUT CURRENT
nA
+I
B
I
B
2.0
2.0
175
1.0
1.5
75
0.5
0
0.5
1.0
1.5
125
75
25
25
125
TPC 25. Input Bias Current vs. Temperature
10
0%
100
90
100 V
0PW 0
20 WFM AQR WARNING
0 WFM
VZR 0
2V
TPC 26. Gain Nonlinearity, G = 100, R
L
= 10 k
,
C
L
= 0 pF. Vertical Scale: 100
V/Div = 100 ppm/Div
Horizontal Scale: 2 Volts/Div
10
0%
100
90
2V
100 V
TPC 27. Gain Nonlinearity, G = 10, R
L
= 10 k
, Vertical
Scale: 100
V/Div = 100 ppm/Div, Horizontal Scale:
2 Volts/Div
+
AD621
1k
10T
+V
S
V
S
G = 10
G = 100
G = 10
G = 100
INPUT
20V p-p
10k
1%
10k
1%
100k
1%
V
OUT
11k
0.1%
1k
0.1%
TPC 28. Settling Time Test Circuit
AD621
REV. B
10
+V
S
V
S
I1
20 A
A1
C1
C2
R1
25k
R5
5555.6
Q1
G = 100
R6
555.6
R3
400
IN
2
4
1
R4
400
3
+IN
10k
10k
OUTPUT
5
6
A3
+
+
+
I2
20 A
V
B
A2
R2
25k
10k
10k
Q2
G = 100
8
REF
7
Figure 3. Simplified Schematic of AD621
THEORY OF OPERATION
The AD621 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp circuit. Careful layout
of the chip, with particular attention to thermal symmetry builds
in tight matching and tracking of critical components, thus
preserving the high level of performance inherent in this circuit,
at a low price.
On chip gain resistors are pretrimmed for gains of 10 and 100.
The AD621 is preset to a gain of 10. A single external jumper
(between Pins 1 and 8) is all that is needed to select a gain of
100. Special design techniques assure a low gain TC of 5 ppm/
C
max, even at a gain of 100.
Figure 3 is a simplified schematic of the AD621. The input
transistors Q1 and Q2 provide a single differential-pair bipolar
input for high precision, yet offer 10
lower Input Bias Current,
thanks to Super
eta processing. Feedback through the Q1-A1-R1
loop and the Q2-A2-R2 loop maintains constant collector cur-
rent of the input devices Q1 and Q2, thereby impressing the
input voltage across the gain-setting resistor, RG, which equals
R5 at a gain of 10 or the parallel combination of R5 and R6 at a
gain of 100.
This creates a differential gain from the inputs to the A1/A2
outputs given by G = (R1 + R2) / RG + 1. The unity-gain
subtracter A3 removes any common-mode signal, yielding a
single-ended output referred to the REF pin potential.
The value of RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the transcon-
ductance increases asymptotically to that of the input transistors.
This has three important advantages: (a) Open-loop gain is
boosted for increasing programmed gain, thus reducing gain-
related errors. (b) The gain-bandwidth product (determined by
C1, C2 and the preamp transconductance) increases with pro-
grammed gain, thus optimizing frequency response. (c) The
input voltage noise is reduced to a value of 9 nV/
Hz, deter-
mined mainly by the collector current and base resistance of the
input devices.
Make vs. Buy: A Typical Bridge Application Error Budget
The AD621 offers improved performance over discrete three op
amp IA designs, along with smaller size, fewer components and
10 times lower supply current. In the typical application, shown
in Figure 4, a gain of 100 is required to amplify a bridge output of
20 mV full scale over the industrial temperature range of 40
C to
+85
C. The error budget table below shows how to calculate
the effect various error sources have on circuit accuracy.
Regardless of the system it is being used in, the AD621 provides
greater accuracy, and at low power and price. In simple systems,
absolute accuracy and drift errors are by far the most significant
contributors to error. In more complex systems with an intelligent
processor, an autogain/autozero cycle will remove all absolute
accuracy and drift errors leaving only the resolution errors of
gain nonlinearity and noise, thus allowing full 14-bit accuracy.
Note that for the discrete circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by 2. This is
because a three op amp type in amp has two op amps at its inputs,
both contributing to the overall input error.
OP07D
OP07D
+
10k *
10k *
10k *
10k *
OP07D
+
10k **
10k **
+
3 OP AMP, IN AMP, G = 100
* 0.02% RESISTOR MATCH, 3PPM/ C TRACKING
** DISCRETE 1% RESISTOR, 100PPM/ C TRACKING
SUPPLY CURRENT = 15mA MAX
+
AD621A
REFERENCE
AD621A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100
SUPPLY CURRENT = 1.3mA MAX
10V
R = 350
R = 350
R = 350
R = 350
PRECISION BRIDGE TRANSDUCER
100k **
Figure 4. Make vs. Buy
AD621
REV. B
11
+
AD705
5V
3k
3k
3k
3k
AD621B
ADC
REF
IN
AGND
DIGITAL
DATA
OUTPUT
20k
10k
20k
+
0.6mA
MAX
0.10mA
1.3mA
MAX
1.7mA
Figure 5. A Pressure Monitor Circuit which Operates on a 5 V Power Supply
Pressure Measurement
Although useful in many bridge applications such as weigh-scales,
the AD621 is especially suited for higher resistance pressure
sensors powered at lower voltages where small size and low
power become more even significant.
Figure 5 shows a 3 k
pressure transducer bridge powered from
5 V. In such a circuit, the bridge consumes only 1.7 mA. Adding
the AD621 and a buffered voltage divider allows the signal to be
conditioned for only 3.8 mA of total supply current.
Small size and low cost make the AD621 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it will also serve applications such as diagnostic non-
invasion blood pressure measurement.
Wide Dynamic Range Gain Block Suppresses Large Common-
Mode and Offset Signals
The AD621 is especially useful in wide dynamic range applica-
tions such as those requiring the amplification of signals in the
presence of large, unwanted common-mode signals or offsets.
Many monolithic in amps achieve low total input drift and noise
errors only at relatively high gains (~100). In contrast the AD621's
low output errors allow such performance at a gain of 10, thus
allowing larger input signals and therefore greater dynamic
range. The circuit of Figure 6 (
15 V supply, G = 10) has
only 2.5
V/C max. V
OS
drift and 0.55
/V p-p typical 0.1 Hz
to 10 Hz noise, yet will amplify a
0.5 V differential signal while
suppressing a
10 V common-mode signal, or it will amplify a
1.25 V differential signal while suppressing a 1 V offset by use
of the DAC driving the reference pin of the AD621. An added
benefit, the offsetting DAC connected to the reference pin allows
removal of a dc signal without the associated time-constant
of ac coupling. Note the representations of a differential and
common-mode signal shown in Figure 6 such that a single-ended
(or normal mode) signal of 1 V would be composed of a 0.5 V
common-mode component and a 1 V differential component.
Table I. Make vs. Buy Error Budget
AD621 Circuit
Discrete Circuit
Error, ppm of Full Scale
Error Source
Calculation
Calculation
AD621
Discrete
ABSOLUTE ACCURACY at T
A
= +25
C
Input Offset Voltage,
V
125
V/20 mV
(150
V 2/20 mV
1
6,250
15,000
Output Offset Voltage,
V
N/A
((150
V 2)/100)/20 mV
N/A
12,
150
Input Offset Current, nA
2 nA
350 /20 mV
(6 nA
350 )/20 mV
12,1
18
121,
53
CMR, dB
110 dB
3.16 ppm, 5 V/20 mV (0.02% Match 5 V)/20 mV
12,
791
1
4,988
Total Absolute Error
1
7,558
20,191
DRIFT TO +85
C
Gain Drift, ppm/
C
5 ppm
60C
100 ppm/
C Track 60C
13,
300
12,
600
Input Offset Voltage Drift,
V/C
1
V/C 60C/20 mV
(2.5
V/C 2 60C)/20 mV
1
3,000
15,000
Output Offset Voltage Drift,
V/C
N/A
(2.5
V/C 2 60C)/100/20 mV
N/A
12,
150
Total Drift Error
1
3,690
15,750
RESOLUTION
Gain Nonlinearity, ppm of Full Scale
40 ppm
40 ppm
12,1
40
12,1
40
Typ 0.1 Hz10 Hz Voltage Noise,
V p-p 0.28 V p-p/20 mV
(0.38
V p-p 2)120 mV
121,
14
12,1
27
Total Resolution Error
121,
54
121,
67
Grand Total Error
11,472
36,008
G = 100, V
S
=
15 V.
(All errors are min/max and referred to input.)
AD621
REV. B
12
AD548
TO
REF
C
R
TO
V
OUT1
+
+
10
AD621
DAC
0 TO 10V
+
V
DIFF
0.5V
INPUT A:
10V CM
V
COM
10V
+
+
INPUT B:
1V
OFFSET
V
DIFF
+ V
OFFSET
(1.25V + 1V)
V
OUT1
G = 10
+
10
AD621
V
OUT2
TOTAL GAIN = 100
10k
10k
OPTIONAL
USE THIS IN PLACE OF THE DAC FOR ZERO SUPPRESSION FUNCTION.
Figure 6. Suppressing a Large Common-Mode or Offset Voltage in Order to Measure a Small Differential Signal
(V
S
=
15 V)
The AD621, as well as many other monolithic instrumentation
amplifiers, is based on the "three op amp" in amp circuit (Fig-
ure 7) amplifier. Since the input amplifiers (A1 and A2) have a
common-mode gain of unity and a differential gain equal to the
set gain of the overall in amp, the voltages V1 and V2 are defined
by the equations
V
1
= V
CM
+ G
V
DIFF
/2
V
2
= V
CM
G
V
DIFF
/2
The common-mode voltage will drive the outputs of amplifiers
A1 and A2 to the differential-signal voltage, multiplied by the
gain, spreads them apart. For a 10 V common-mode 0.1 V
differential input, V1 would be at 10.5 V and V2 at 9.5 V.
A1
A3
+
10k
10k
10k
10k
A2
+
20k
20k
+
V1
V2
INPUT AMPLIFIER
DIFFERENTIAL GAIN = 10
COMMON MODE GAIN = 1
OUTPUT AMPLIFIER
DIFFERENTIAL GAIN = 1
COMMON MODE GAIN = 1/1000
4.44k
Figure 7. Typical Three Op Amp Instrumentation
Amplifier, Differential Gain = 10
The AD621's input amplifiers can provide output voltage within
2.5 V of the supplies. To avoid saturation of the input amplifier
the input voltage must therefore obey the equations:
V
CM
+ G
V
DIFF
/2
(Upper Supply 2.5 V)
V
CM
G
V
DIFF
/2
(Lower Supply + 2.5 V)
Figure 8 shows the trade-off between common-mode and
differential-mode input for
15 V supplies and G = 10.
By cascading with use of the optional AD621, the circuit of
Figure 6 will provide
1 V of zero suppression at gains of 10
and 100 (at V
OUT1
and V
OUT2
respectively) with maximum TCs
of
4 ppm/C and 8 ppm/C, respectively. Therefore, depend-
ing on the magnitude of the differential input signal, either
V
OUT1
or V
OUT2
may be used as the output.
V
CM
Volts
1.2
0.2
0
10
2
V
DIFF
Volts
4
8
1.0
0.8
0.6
0.4
6
0
12
Figure 8. Trade-Off Between V
CM
and V
DIFF
Range (V
S
=
15 V, G = 10), for Reference Pin at Ground
AD621
REV. B
13
Precision V-I Converter
The AD621 along with another op amp and two resistors make
a precision current source (Figure 9). The op amp buffers the
reference terminal to maintain good CMR. The output voltage
V
X
of the AD621 appears across R1 which converts it to a cur-
rent. This current less only the input bias current of the op amp
then flows out to the load.
+V
S
V
IN
V
IN+
AD621
+V
X
R1
I
L
AD705
LOAD
V
S
I
L
=
V
X
R1
(V
IN+
) (V
IN
) G
R1
=
Figure 9. Precision Voltage to Current Converter
(Operates on 1.8 mA,
3 V)
INPUT AND OUTPUT OFFSET VOLTAGE
The AD621 is fully specified for total input errors at gains of 10
and 100. That is, effects of all error sources within the AD621
are properly included in the guaranteed input error specs, elimi-
nating the need for separate error calculation.
Total Error RTI = Input Error + (Output Error/G)
Total Error RTO = (Input Error
G) + Output Error
REFERENCE TERMINAL
Although usually grounded, the reference terminal may be used
to offset the output of the AD621. This is useful when the load
is "floating" or does not share a ground with the rest of the system.
It also provides a direct means of injecting a precise offset.
Another benefit of having a reference terminal is that it can be
quite effective in eliminating ground loops and noise in a circuit
or system.
V
OL
+V
S
AD621
V
OUT
V
S
V
OL
R
P
R
P
GAIN = 10 OR 100
Figure 10. Input Overload Protection
INPUT OVERLOAD CONSIDERATIONS
Failure of a transducer, faults on input lines, or power supply
sequencing can subject the inputs of an instrumentation ampli-
fier to voltages well beyond their linear range, or even the supply
voltage, so it is essential that the amplifier handle these over-
loads without being damaged.
The AD621 will safely withstand continuous input overloads of
3.0 volts (6.0 mA). This is true for gains of 10 and 100, with
power on or off.
The inputs of the AD621 are protected by high current capacity
dielectrically isolated 400
thin-film resistors R3 and R4 (Fig-
ure 3) and by diodes which protect the input transistors Q1 and
Q2 from reverse breakdown. If reverse breakdown occurred, there
would be a permanent increase in the amplifier's input current.
The input overload capability of the AD621 can be easily increased
while only slightly degrading the noise, common-mode rejection
and offset drift of the device by adding external resistors in series
with the amplifier's inputs as shown in Figure 10.
Table II summarizes the overload voltages and total input
noise for a range of range of r values. Note that a 2 k
resis-
tor in series with each input will protect the AD621 from a
15 volt continuous overload, while only increasing input noise
to 13 nV
Hz--about the same level as would be expected from
a typical unprotected 3 op amp in amp.
Table II. Input Overload Protection vs. Value of Resistor R
P
Total Input Noise
Maximum Continuous
Value of
in nV
Hz @ 1 kHz
Overload Voltage, V
OL
Resistor R
P
G = 10
G = 100
In Volts
0
14
9
3
499
14
10
6
1.00 k
14
11
9
2.00 k
15
13
15
3.01 k
*
16
14
21
4.99 k
*
17
16
33
*1/4 watt, 1% metal-film resistor. All others are 1/8 watt, 1% RN55
or equivalent.
AD621
REV. B
14
Gain Selection
The AD621 has accurate, low temperature coefficient (TC),
gains of 10 and 100 available. The gain of the AD621 is nomi-
nally set at 10; this is easily changed to a gain of 100 by simply
connecting a jumper between Pins 1 and 8.
AD621
555.5
5,555.5
R
EXT
Figure 11. Programming the AD621 for Gains Between
10 and 100
As shown in Figure 11, the device can be programmed for any
gain between 10 and 100 by connecting a single external resistor
between Pins 1 and 8. Note that adding the external resistor will
degrade both the gain accuracy and gain TC. Since the gain
equation of the AD621 yields:
G
= 1+
9 ( R
X
+ 6,111.111)
( R
X
+ 555.555)
This can be solved for the nominal value of external resistor for
gains between 10 and 100:
R
X
=
(G 1) 555.555 55,000
(10 G )
Table III gives practical 1% resistor values for several com-
mon gains.
Table III. Practical 1% External Resistor
Values for Gains Between 10 and 100
Desired Recommended
Temperature
Gain
1% Resistor Value
Gain Error Coefficient (TC)
10
(Pins 1 and 8 Open)
*
5 ppm/
C max
20
4.42 k
10%
0.4 (50 ppm/C
+ Resistor TC)
50
698
10%
0.4 (50 ppm/C
+ Resistor TC)
100
0 (Pins 1 and 8 Shorted)
*
5 ppm/
C max
*Factory trimmedexact value depends on grade.
A High Performance Programmable Gain Amplifier
The excellent performance of the AD621 at a gain of 10 makes
it a good choice to team up with the AD526 programmable gain
amplifier (PGA) to yield a differential input PGA with gains of
10, 20, 40, 80, 160. As shown in Figure 12, the low offset of the
AD621 allows total circuit offset to be trimmed using the offset
null of the AD526, with only a negligible increase in total drift
error. The total gain TC will be 9 ppm/
C max, with 2 V/C
typical input offset drift. Bandwidth is 600 kHz to gains of 10 to
80, and 350 kHz at G = 160. Settling time is 13
s to 0.01%
for a 10 V output step for all gains.
+
V
S
AD621
+V
S
INPUTS
+
0.1 F
G = 10
+
V
S
AD526
+V
S
0.1 F
20k
0.1 F
0.1 F
2
OUTPUT
Figure 12. A High Performance Programmable Gain
Amplifier
COMMON-MODE REJECTION
Instrumentation amplifiers like the AD621 offer high CMR
which is a measure of the change in output voltage when both
inputs arc changed by equal amounts. These specifications are
usually given for a full-range input voltage change and a speci-
fied source imbalance.
For optimal CMR, the reference terminal should be tied to a
low impedance point, and differences in capacitance and resis-
tance should be kept to a minimum between the two inputs. In
many applications shielded cables are used to minimize noise,
and for best CMR over frequency the shield should he properly
driven. Figures 13 and 14 show active data guards that are config-
ured to improve ac common-mode rejections by "bootstrapping"
the capacitances of input cable shields, thus minimizing the
capacitance mismatch between the inputs.
INPUT
+INPUT
100
100
100k
100k
V
S
V
S
+V
S
V
OUT
REFERENCE
AD621
AD648
+
Figure 13. Differential Shield Driver, G = 10
AD548
100
INPUT
+ INPUT
REFERENCE
V
OUT
AD621
4
V
S
+V
S
8
3
1
2
7
5
6
Figure 14. Common-Mode Shield Driver, G = 100
AD621
REV. B
15
GROUNDING
Since the AD621 output voltage is developed with respect to the
potential on the reference terminal, it can solve many ground-
ing problems by simply tying the REF pin to the appropriate
"local ground."
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 15). It would be conve-
nient to use a single ground line; however, current through
ground wires and PC runs of the circuit card can cause hundreds
of millivolts of error. Therefore, separate ground returns should
be provided to minimize the current flow from the sensitive
points to the system ground. These ground returns must be tied
together at some point, usually best at the ADC package as shown.
DIGITAL P.S.
+5V
C
ANALOG P.S.
+15V C 15V
AD574A
+
AD621
AD585
S/H
ADC
5
9
11
15
6
2
4
7
1
11
7
6
4
0.1 F
1 F
3
DIGITAL
DATA
OUTPUT
0.1 F
1 F
1 F
Figure 15. Basic Grounding Practice
GROUND RETURNS FOR INPUT BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of an amplifier. There must be a direct return path
for these currents; therefore when amplifying "floating" input
sources such as transformers, or ac-coupled sources, there must
be a dc path from each input to ground as shown in Figures 16a
through 16c. Refer to the Instrumentation Amplifier Application
Guide (free from Analog Devices) for more information regard-
ing in amp applications.
+V
S
AD621
LOAD
V
S
REFERENCE
TO POWER SUPPLY GROUND
+INPUT
INPUT
V
OUT
Figure 16a. Ground Returns for Bias Currents when Using
Transformer Input Coupling
+V
S
AD621
LOAD
V
S
REFERENCE
TO POWER SUPPLY GROUND
+INPUT
INPUT
V
OUT
Figure 16b. Ground Returns for Bias Currents when Using
a Thermocouple Input
100k
100k
INPUT
AD621
+INPUT
+V
S
V
S
V
OUT
LOAD
REFERENCE
TO POWER SUPPLY GROUND
Figure 16c. Ground Returns for Bias Currents when Using
AC Input Coupling
AD621
REV. B
16
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
0.125 (3.18)
MIN
0.165 0.01
(4.19 0.25)
0.39 (9.91)
MAX
0.25
(6.35)
4
5
8
1
0.035 0.01
(0.89 0.25)
0.018 0.003
(0.46 0.08)
0.30 (7.62)
REF
0 - 15
0.10
(2.54)
TYP
0.011 0.003
(4.57 0.76)
SEATING PLANE
0.31
(7.87)
0.18 0.03
(4.57 0.76)
0.033
(0.84)
NOM
Cerdip (Q-8) Package
0.005 (0.13) MIN
0.055 (1.4) MAX
0.405 (10.29) MAX
0.150
(3.81)
MIN
0.200
(5.08)
MAX
0.310 (7.87)
0.220 (5.59)
0.070 (1.78)
0.030 (0.76)
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.320 (8.13)
0.290 (7.37)
0 - 15
0.015 (0.38)
0.008 (0.20)
0.100 (2.54)
BSC
SEATING PLANE
0.060 (1.52)
0.015 (0.38)
4
1
5
8
SOIC (R-8) Package
0.181 (4.60)
0.205 (5.20)
0.020 (0.50)
0.045 (1.15)
0.007 (0.18)
0.015 (0.38)
0.100 (2.59)
0.094(2.39)
0.004 (0.10)
0.010 (0.25)
1
4
5
8
0.188 (4.77)
0.198 (5.03)
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.200)
0.014 (0.36)
0.018 (0.46)
0.050 (1.27)
TYP
C0077601/01 (rev. B)
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