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REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD6458
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
GSM 3 V Receiver IF Subsystem
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Fully Compliant with Standard and Enhanced GSM
Specification
12 dBm Input 1 dB Compression Point
2 dBm Input Third Order Intercept
10 dB SSB Noise Figure (330 )
DC400 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB and Stable over Temperature Voltage
Gain Control
Quadrature Demodulator
Onboard Phase-Locked Quadrature Oscillator
Demodulates IFs from 5 MHz to 50 MHz
Low Power
9 mA at Midgain
1 A Sleep Mode Operation
3.0 V to 3.6 V Operation
Interfaces to AD7013, AD7015 and AD6421 Baseband
Converters
20-Lead SSOP
GENERAL DESCRIPTION
The AD6458 is a 3 V, low power receiver IF subsystem for
operation at input frequencies as high as 400 MHz and IFs from
5 MHz up to 50 MHz. It is optimized for operation in GSM,
DCS1800 and PCS1900 receivers. It consists of a mixer, IF
amplifier, I and Q demodulators, a phase-locked quadrature
oscillator, precise AGC subsystem, and a biasing system with
external power-down.
The low noise, high intercept mixer of the AD6458 is a
doubly-balanced Gilbert cell type. It has a nominal 12 dBm
input-referred 1 dB compression point and a 2 dBm input-
referred third-order intercept. The mixer section of the AD6458
also includes a local oscillator (LO) preamplifier, which lowers
the required LO drive to 16 dBm.
The gain control input accepts an external gain-control voltage
input from an external AGC detector or a DAC. It provides an
80 dB gain range with 27 mV/dB gain scaling.
The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices' AD7013
(IS54, TETRA, MSAT) and AD7015 and AD6421 (GSM,
DCS1800, PCS1900) baseband converters. An onboard
quadrature VCO which is externally phase-locked to the IF
signal drives the I and Q demodulators. This locked reference
signal is normally provided by an external VCTCXO under the
control of the radio's digital processor. The AD6458 can also
provide demodulation of N-PSK and N-QAM in many non-
TDMA systems when used with external analog carrier recovery
systems such as the Costas Loop. Finally, the VCO can be
phase-locked to a frequency which is deliberately offset from the
IF, as in the case of a Beat-Frequency Oscillator (BFO), result-
ing in the product detection of CW or SSB.
The AD6458 uses supply voltages from 3.0 V to 3.6 V over the
temperature range of 40
C to +85
C. Operation is enabled by
a CMOS logical level; response time is typically <80
s. When
disabled, the standby current is reduced to 1
A.
The AD6458 comes in a 20-lead shrink small outline (SSOP)
surface-mount package.
BPF
LO
I
Q
AGC
FREF
RF
AD6458
PLO
2
REV. 0
AD6458SPECIFICATIONS
(@ T
A
= +25 C, V
P
= 3.0 V, GREF = 1.2 V, unless otherwise noted)
Parameter
Conditions
Min
Typ
Max
Units
MIXER
Maximum RF and LO Frequency
400
MHz
AGC Conversion Gain Variation
0.2 V < V
G
< 2.25 V, Z
S
= 50
, Z
LOAD
= 330
8.5 to +9.5
dB
Input RF Signal Range
95
15
dBm
Input 1 dB Compression Point
@ V
G
= 0.2 V, Z
S
= 50
, Z
LOAD
= 330
11
dBm
Input Third-Order Intercept
@ V
G
= 0.2 V, Z
S
= 50
, Z
LOAD
= 330
2
dBm
SSB Noise Figure
1
@ Z
S
=1 k
, F
RF
= 83 MHz, F
LO
= 96 MHz at 16 dBm
9
dB
Mixer Output Bandwidth at MXOP
@ 3 dB, Z
LOAD
= 330
55
MHz
IF AMPLIFIERS
AGC Gain Variation
0.2 V < V
G
< 2.25 V
9 to +48
dB
Input Referred Noise
AC Short Circuit Input
3
nV/Hz
Input Resistance
@ V
G
= 0.2 V
5
k
Bandwidth
@ 3 dB
50
MHz
I AND Q DEMODULATORS
Demodulation Gain
17
dB
Output Voltage Range
IRXP, IRXN, QRXP, QRXN
0.3
V
P
0.2
V
Output Voltage Common-Mode Level
(Not Power Supply Dependant)
1.5
V
Output Offset Voltage
Differential
150
+150
mV
Output Offset Voltage Variation
Differential, over Gain and Temperature Range
2
1
mV
Output Offset Voltage Variation
Differential, for 0.5 V < V
G
< 2.4 V and
25
C < T
A
< +85
C (See Note 2)
0.5
mV
Error in Quadrature
IF = 13 MHz
1.5
3.7
Degree
Amplitude Match
0.25
dB
I/Q Output Bandwidth
C
LOAD
= 10 pF
2
MHz
Output Resistance
Each Pin
4.7
k
GAIN CONTROL
Total Gain Control Range
Mixer + IF + Demod, 0.2 V < V
G
< 2.25 V
75
dB
Control Voltage Range at GAIN
0.2
2.4
V
Gain Scaling
23
27
32
mV/dB
Gain Law Conformance
0.5
dB
Bias Current at GREF
0.5
A
Input Resistance at GAIN
20
k
PLL
Frequency Range
5
40
MHz
Phase Noise
0.5
Degree rms
Acquisition Time
IF = 13 MHz, Using Ceramic Filter
80
s
Input Drive Level (FREF)
100
VPOS
mV
POWER-DOWN INTERFACE
Logical Threshold
Power-Up On Logical High
1.5
V
Input Current for Logical High
75
A
Turn On Response Time
To Fully Meet Specifications
80
150
s
Stand By Current
(See Note 3)
1
8
A
POWER SUPPLY
Supply Range
3.0
3.3
3.6
V
Worst Case Supply Current
@ V
GAIN
= 0.2 V, T
A
= +85
C, V
P
= 3.6 V
4
16.5
22
mA
Supply Current
@ V
GAIN
= 1.2 V
9
mA
OPERATING TEMPERATURE
T
MIN
to T
MAX
40 to +85
C
NOTES
1
Including IF noise and using 13 MHz ceramic filter, at V
GAIN
= 0.2 V.
2
Histograms of Demodulator Offset Voltage Variation in Gain and Temperature can be found in Figures 23 to 27.
3
Max value represent the value at six times the standard deviation, in the worst case condition (T
A
= +85
C). The value at three times the standard deviation is 5
A.
4
Max value represent the value at six times the standard deviation. The value at three times the standard variation is 19 mA.
Specifications subject to change without notice.
AD6458
3
REV. 0
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . +3.6 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . 600 mW
Operating Temperature Range . . . . . . . . . . . 40
C to +85
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature, Soldering (60 sec) . . . . . . . . . . . +300
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended rating conditions for extended periods may affect device
reliability.
2
Thermal Characteristics: 20-Lead SSOP Package:
JA
= 126
C/W.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD6458ARS 40
C to +85
C 20-Lead Shrink Small Outline RS-20
PIN FUNCTION DESCRIPTIONS
Pin
Pin
Number
Label
Description
Function
1
FREF
Frequency Reference Input
Demodulation LO Input. May be 3 V CMOS input or >100 mV ac coupled for
lowest stand by current.
2
COM1
Common 1
Ground.
3
PRUP
Power-Up Input
CMOS compatible power up control; 0 = OFF, 3 V = ON.
4
LOIP
Local Oscillator Input
AC coupled LO input. Only 50 mV drive needed, 500 mV max.
5
RFLO
RF "Low" Input
Usually connected to ac ground.
6
RFHI
RF "High" Input
AC coupled, 109 dBV to 29 dBV RF input from 1 k
filter for optimal operation.
7
COM2
Common 2
Ground.
8
GREF
Gain Reference Input
High impedance input, sets gain scaling, typically 1.2 V.
9
MXOP
Mixer Output
Output of the Mixer.
10
NC
Not internally connected. Should be grounded.
11
IFIP
IF Input "Plus"
Differential Input of variable gain amplifier.
12
IFIM
IF Input "Minus"
Differential Input of variable gain amplifier.
13
GAIN
Gain Control Input
0.2 V2.4 V using 3 V supply. Max gain at 0.2 V.
14
QRXN
Q Output "Negative"
Differential Q Output.
15
QRXP
Q Output "Positive"
Differential Q Output.
16
IRXN
I Output "Negative"
Differential I Output.
17
IRXP
I Output "Positive"
Differential I Output.
18
VPS2
VPOS Supply 2
Supply Voltage.
19
FLTR
PPL Loop Filter
Series RC loop filter, connected to VPS2.
20
VPS1
VPOS Supply 1
Supply Voltage.
PIN CONNECTION
20-Lead SSOP (RS-20)
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD6458
FREF
IRXP
VPS2
FLTR
VPS1
COM1
PRUP
LOIP
QRXN
QRXP
IRXN
RFLO
RFHI
COM2
GREF
MXOP
NC
IFIP
IFIM
GAIN
NC = NO CONNECT
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6458 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
AD6458
4
REV. 0
10
9
8
1
2
3
4
7
6
5
14
13
12
11
17
16
15
20
19
18
AD6458
FREF
IRXP
VSP2
FLTR
VSP1
COM1
PRUP
LOIP
QRXN
QRXP
IRXN
RFLO
RFHI
COM2
GREF
MXOP
IFIP
IFIM
GAIN
R1
20k
VPOS
C1
0.1F
C10 1nF
R8 1k
C11
0.1F
C10
0.1F
(BOTTOM)
C7
0.01F
C8
0.01F
R6
50
R7
50
R4
54.9
FREF
R9
50
R2
50
PRUP
LOIP
RFHI
GREF
R3
50
C12
220pF
C2
1nF
C4 1nF
C3
1nF
VPOS
IRXP
QRXN
QRXP
IRXN
GAIN
MXOP
IFIP
IFIM
R5
OPEN
C6
1nF
R10
301
Figure1. Characterization Board
C7
0.1pF
V
N
R4
50
I
OUT
C6
0.1pF
V
P
R3
50
Q
OUT
GAIN
FREF
VPOS
GREF
GREF
PRUP
LOIP
RFIP
MXOP
IFIP
IFIM
IRXP
IRXN
QRXP
QRXN
GAIN
AD6458
CHARACTERIZATION
BOARD
PRUP
LOIP
RFIP
FREF
VPOS
R5
50
IFIN
R1
100
MXOP
1
2
3
4
8
7
6
5
V
P
V
N
A=1
Gm
Gm
AD830
C5
0.1pF
V
N
C4
0.1pF
V
P
1
2
3
4
8
7
6
5
V
P
V
N
A=1
Gm
Gm
AD830
C8
0.1pF
V
N
C9
0.1pF
V
P
1
2
3
4
8
7
6
5
V
P
V
N
A=1
Gm
Gm
AD830
R6
50
C10
0.1pF
V
N
C11
0.1pF
V
P
1
2
3
4
8
7
6
5
V
P
V
N
A=1
Gm
Gm
AD830
Figure 2. Characterization Test Set
AD6458
5
REV. 0
HP8657B
SYNTHESIZER
RF OUT
MOD I/O
10MHz OUT
10MHz IN
SYNC
I
EEE
AD6458
MOTHER BOARD
PRUP
VPOS
VIN
VP
FREF
LOIP
RFIP
GREF
MXOP
IFIN
IOUT
QOUT
GAIN
HP6237
+5V
5V
COM
+15V
HP34401
HI
LO
I HI
DMM
I
EEE
HP663X
POWER
SUPPLY
I
EEE
HI
LO
HP8657B
SYNTHESIZER
RF OUT
MOD I/O
10MHz OUT
10MHz IN
SYNC
I
EEE
DP8200
DC SOURCE
HI F
HI S
LO F
LO S
GND
I
EEE
DP8200
DC SOURCE
I
EEE
HI F
HI S
LO F
LO S
GND
CAL OUT
RF I/P
I
EEE
28 VOLT
SWEEP OUT
HP8593E
ANALYSER
SPECTRUM
HP8657B
SYNTHESIZER
RF OUT
MOD I/O
10MHz OUT
10MHz IN
SYNC
I
EEE
Figure 3. Mixer Characterization Setup
C9
10nF
PRUP
C5
0.1F
10
9
8
1
2
3
4
7
6
5
14
13
12
11
17
16
15
20
19
18
AD6458
FREF
IRXP
VSP2
FLTR
VSP1
COM1
PRUP
LOIP
QRXN
QRXP
IRXN
RFLO
RFHI
COM2
GREF
MXOP
IFIP
IFIM
GAIN
VPOS
C1
0.1F
C10 1nF
R8 1k
C11
0.1F
FREF
R2
50
LOIP
RFHI
GREF
R1
50
C12
220pF
C2
1nF
C4 1nF
C7
1nF
VPOS
IRXP
QRXN
QRXP
IRXN
GAIN
R5
330
C13
10nF
BPF2
Figure 4. Typical Connection Diagram
AD6458
6
REV. 0
RF FREQUENCY MHz
22
12
6
80
120
NOISE FIGURE dB
160
200
240
280
320
360
400
440
20
14
10
8
18
16
F
IF
= 13MHz, Z
S
= 50
F
IF
= 26MHz, Z
S
= 50
F
IF
= 13MHz, Z
S
= 400
Figure 5. Mixer Noise Figure vs. RF Frequency
NOISE FIGURE dB
PERCENTAGE
35
0
7.0
8.4
7.2
7.4
7.6
7.8
8.0
8.2
30
20
15
10
5
25
= 7.7dB
= 0.26dB
Figure 6. Mixer Noise Figure Histogram, R
S
= 1 k
,
F
RF
= 83 MHz, F
IF
= 13 MHz
RF FREQUENCY MHz
RESISTANCE k
2.0
1.6
0
50
550
100
150
200
250
300
350
400
450
500
1.2
0.8
0.4
5.5
CAP pF
5.0
3.0
4.5
4.0
3.5
C
SH
, V
GAIN
= 0.2V
R
SH
, V
GAIN
= 2.2V
C
SH
, V
GAIN
= 1.0V
R
SH
, V
GAIN
= 1.0V
C
SH
, V
GAIN
= 2.2V
R
SH
, V
GAIN
= 0.2V
Figure 7. Mixer Input Impedance vs. RF Frequency,
V
POS
= 3.0 V, T
A
= +25
C
RF FREQUENCY MHz
CONVERSION GAIN dB
15
0
15
50
550
100
150
200
250
300
350
400
450
500
10
5
5
10
V
GAIN
= 0.2V
V
GAIN
= 1.2V
V
GAIN
= 2.2V
Figure 8. Mixer Conversion Gain vs. RF Frequency,
T
A
= +25
C, V
POS
= 3.0 V, V
REF
=1.2 V, F
IF
=13 MHz
GAIN dB
IF FREQUENCY MHz
12
2
10
10
54
14
18
22
26
30
34
38
42
46
50
10
0
4
6
8
4
6
2
8
V
GAIN
= 0.2V
V
GAIN
= 1.5V
V
GAIN
= 2.2V
Figure 9. Mixer Conversion Gain vs. IF Frequency,
T
A
= +25
C, V
POS
= 3 V, V
REF
= 1.2 V, F
RF
= 250 MHz
V
GAIN
Volts
GAIN dB
15
10
15
0
2.5
0.5
1.0
1.5
2.0
5
0
5
10
V
POS
= 3V TO 3.6V
T
A
= 25
C TO +85
C
Figure 10. Mixer Conversion Gain vs V
GAIN
, V
REF
= 1.2 V,
F
IF
=13 MHz, F
RF
= 83 MHz
AD6458
7
REV. 0
V
GAIN
Volts
8
9
15
0
2.5
0.5
1.0
1.5
2.0
11
12
13
14
10
V
POS
= 3.6V
T
A
= +85
C
V
POS
= 3.0V
T
A
= +85
C
V
POS
= 3.6V
T
A
= +25
C
V
POS
= 3.0V
T
A
= +25
C
V
POS
= 3.0V
T
A
= 25
C
V
POS
= 3.0V
T
A
= 40
C
INPUT dBm (REFERRED TO 50
)
Figure 11. Mixer Input 1 dB Compression Point vs. V
GAIN
,
V
REF
= 1.2 V, F
RF
= 83 MHz, F
IF
= 13 MHz
INTERMEDIATE FREQUENCY dB
70
0
5
45
10
15
20
25
30
35
40
60
40
30
20
10
50
V
GAIN
= 0.2V
V
GAIN
= 1.0V
V
GAIN
= 1.5V
V
GAIN
= 2.25V
IF AMP/DEMOD GAIN dB
Figure 12. IF Amplifier and Demodulator Gain vs.
Frequency, T
A
= +25
C, V
POS
= 3.0 V, V
REF
=1.2 V
V
GAIN
Volts
GAIN dB
70
60
10
0
2.5
0.5
1.0
1.5
2.0
30
20
10
0
50
40
T
A
= 40
C TO +85
C
Figure 13. IF Amplifier and Demodulator Gain vs.
V
GAIN
, T
A
= +25
C, V
POS
= 3.0 V, F
IF
= 13 MHz, V
REF
= 1.2 V
IF INPUT dBm (REFERRED TO 50
)
V
GAIN
Volts
5
10
60
0
2.5
0.5
1.0
1.5
2.0
25
40
45
50
15
20
35
30
55
T
A
= 40
C
T
A
= 25
C
T
A
= +25
C
T
A
= +85
C
Figure 14. IF Amplifier/Demodulator Input 1 dB Compres-
sion Point vs. V
GAIN
, F
IF
=13 MHz, V
REF
= 1.2 V, T
A
= +25
C,
V
POS
= 3.0 V
IF FREQUENCY MHz
12000
6000
0
0
100
10
RESISTANCE
20
30
40
50
60
70
80
90
10000
8000
4000
2000
R SHUNT, V
GAIN
= 2.2V
C SHUNT, V
GAIN
= 1.0V
R SHUNT, V
GAIN
= 1.0V
R SHUNT, V
GAIN
= 0.2V
C SHUNT, V
GAIN
= 2.2V
C SHUNT, V
GAIN
= 0.2V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
CAPACITANCE pF
Figure 15. IF Amplifier Input Impedance vs. Frequency,
T
A
= +25
C, V
POS
= 3.0 V, V
REF
= 1.2 V
GAIN VOLTAGE Volts
1
0.8
0
0
2.5
0.5
1
1.5
2
0.2
0.6
0.8
1
0.6
0.4
0.4
0.2
MIXER
ERROR dB
IF AMP/DEMOD
Figure 16. AD6458 Gain Error vs. Gain Control Voltage,
Representative Part
AD6458
8
REV. 0
F
REF
FREQUENCY MHz
QUAD_ERROR
4.0
0
10
55
15
20
25
30
35
40
45
50
3.5
2.0
1.5
1.0
0.5
3.0
2.5
Figure 17. Demodulator Quadrature Error vs. F
REF
Frequency, T
A
= +25
C, V
POS
= 3.0 V
PERCENTAGE
ERROR Degrees
16
6
0
1.5
2.9
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8
3.0
14
8
4
2
12
10
= 2.1d
= 0.3d
Figure 18. Demodulator Quadrature Error Histogram
T
A
= +25
C, V
POS
= 3.0 V. F
IF
= 13 MHz
CARRIER FREQUENCY kHz
PHASE NOISE dBc
90
95
120
0.1
10k
1
10
100
1k
100
105
110
115
Figure 19. PLL Phase Noise vs. Frequency, V
POS
= 3 V,
C
FLTR
= 1 nF, R
FLTR
= 1 k
, F
REF
= 13 MHz
PLL FREQUENCY MHz
FLTR PIN VOLTAGE
REFERENCED TO V
POS
Volts
0.1
1.5
5
55
10
15
20
25
30
35
40
45
50
0.3
0.5
0.7
0.9
1.1
1.3
Figure 20. PLL Loop Voltage at FLTR Pin (kVCO) vs. Frequency
V
GAIN
Volts
10
15
65
0
2.5
0.5
1.0
1.5
2.0
30
45
50
60
20
25
40
35
55
INPUT dBm
(REFERRED TO 50
- ie. +10dBm -> 2V p-p)
Figure 21. System [(Mixer + IF Ceramic Filter + IF Ampli-
fier + Demodulator)] Input 1 dB Compression Point vs.
V
GAIN
, T
A
= +25
C, V
POS
= 3.0 V, F
IF
= 13 MHz, F
RF
= 83 MHz,
V
REF
= 1.2 V
V
GAIN
Volts
GAIN dB
80
70
20
0
2.5
0.5
1.0
1.5
2.0
40
10
0
10
60
50
20
30
Figure 22. System (Mixer + IF Ceramic Filter + IF Amplifier
+ Demodulator) Conversion Gain vs. V
GAIN
, T
A
= +25
C,
V
POS
= 3.0 V, F
IF
= 13 MHz, F
RF
= 83 MHz, V
REF
= 1.2 V
AD6458
9
REV. 0
PERCENTAGE
VARIATION mV
100
30
0
4.9
3.9
2.9
1.9
0.9
0.1
1.1
2.1
3.1
4.1
90
40
20
10
70
50
80
60
= 0.03mV
= 0.4mV
Figure 23. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
GAIN
= 1.2 V
and T
A
= +25
C, V
GAIN
= 2.25 V and T
A
= +25
C
VARIATION mV
PERCENTAGE
80
30
0
2.9
3.1
2.4 1.9 1.4 0.9 0.4
0.1
0.6
1.1
1.6
2.1
2.6
70
40
20
10
60
50
= 0.1mV
= 0.6mV
Figure 24. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
GAIN
= 1.2 V
and T
A
= +25
C, V
GAIN
= 0.5 V and T
A
= +25
C C
PERCENTAGE
VARIATION mV
50
15
0
4.9
5.1
3.9
2.9
1.1
1.9
0.9
0.1
2.1
3.1
4.1
45
20
10
5
35
25
40
30
= 0.04mV
= 1.1mV
PERCENTAGE
VARIATION mV
50
15
0
4.9
5.1
3.9
2.9
1.1
1.9
0.9
0.1
2.1
3.1
4.1
45
20
10
5
35
25
40
30
= 0.04mV
= 1.1mV
Figure 25. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
GAIN
=
1.2 V and T
A
= +25
C, V
GAIN
= 0.2 V and T
A
= +25
C
PERCENTAGE
OFFSET DRIFT mV
16
8
0
10
10
8
6
4
2
0
2
4
6
8
14
12
4
2
10
6
= 0.9mV
= 3.4mV
Figure 26. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
GAIN
=
1.2 V and T
A
= +25
C, V
GAIN
= 0.2 V and T
A
= 25
C
OFFSET DRIFT mV
PERCENTAGE
30
15
0
10
10
8
6
4
2
0
2
4
6
8
25
20
10
5
= 0.04mV
= 3.6mV
Figure 27. Demodulation Output Offset Voltage Variation
Histogram with Variation Referred to Offset at V
GAIN
=
1.2 V and T
A
= +25
C, V
GAIN
= 0.2 V and T
A
= +85
C
V
GAIN
Volts
SUPPLY CURRENT mA
18
16
6
0
2.5
0.5
1.0
1.5
2.0
14
12
10
8
V
POS
= 3.0V, T
A
= +85
C
V
POS
= 3.6V, T
A
= +85
C
V
POS
= 3.6V, T
A
= +25
C
V
POS
= 3.6V, T
A
= 40
C
Figure 28. Power Supply Current vs. Gain Control Volt-
age, V
REF
= 1.2 V
AD6458
10
REV. 0
PRODUCT OVERVIEW
The AD6458 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or the latter part of a double-conversion receiver,
at input frequencies up to 400 MHz, with an IF from 5 MHz to
50 MHz. The internal I/Q demodulators, and their associated
phase-locked loop, support a wide variety of modulation modes,
including n-PSK, n-QAM, and GMSK. A single positive supply
voltage of 3.3 V is required (3.0 V minimum, 3.6 V maximum)
at a typical supply current of 9 mA at midgain. In the following
discussion, V
POS
will be used to denote the power supply volt-
age, which will be assumed to be 3.3 V.
Figure 31 shows the main sections of the AD6458. It consists of
a variable-gain UHF mixer and linear two-stage IF strip, which
together provide a calibrated voltage-controlled gain range of
more than 76 dB, followed by dual quadrature demodulators.
These are driven by inphase and quadrature clocks generated by
a Phase-Locked Loop (PLL), which is locked to a corrected
external reference. A CMOS-compatible power-down interface
completes the AD6458.
V
GAIN
Volts
V
PRUP
Volts
2.0
1.9
1.0
0
2.5
0.5
1.0
1.5
2.0
1.6
1.3
1.2
1.1
1.8
1.7
1.4
1.5
T
A
= 40
C
T
A
= 25
C
T
A
= +25
C
T
A
= +85
C
Figure 29. Minimum Power-Up Voltage vs V
GAIN
, V
POS
=
3.0 V, V
REF
= 1.2 V
Mixer
The UHF mixer is an improved Gilbert-cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 400 MHz. The dynamic range at the input of the
mixer is determined at the upper end by the maximum input
signal level of
56 mV (15 dBm in 50
between RFHI and
RFLO) up to which the mixer remains linear and, at the lower
end, by the noise level. It is customary to define the linearity of
a mixer in terms of the 1 dB gain-compression point and third-
order intercept, which for the AD6458 are 12 dBm and
2 dBm, respectively, in a 50
system.
The mixer's RF input port is differential; that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased. The RF port can be modeled as a parallel RC circuit as
shown in Figure 30.
RFHI
RFLO
C
SH
R
SH
Figure 30. Mixer Port Modeled as a Parallel RC Network
The local oscillator (LO) input is internally biased at V
P
0.8 V
and must be ac coupled. The LO interface includes a preampli-
fier which minimizes the drive requirements, thus simplifying
the oscillator design and reducing LO leakage from the RF port.
The LO requires a single-sided drive of
50 mV, or 16 dBm in
a 50
system. For operation above 300 MHz noise figure can
be improved by increasing the LO level.
The output of the mixer is single ended with a 330
impedance
for driving ceramic filters.
The conversion gain is measured between the mixer input and
the input of this filter, and varies between 9 dB and +10 dB as
a function of the voltage at Pin GAIN.
The maximum permissible signal level at Pin MXOP is deter-
mined by the maximum gain control voltage.
The mixer output port is shown in Figure 32.
VPS1
RFHI
AD6458
MXOP
IFIP
IFIM
0
90
4.7k
4.7k
4.7k
4.7k
AGC VOLTAGE
BIAS
CIRCUIT
VPS2
PRUP
RFLO
LOIP
IRXP
IRXN
FREF
FLTR
QRXP
QRXN
GAIN
GREF
19
20
13
14
15
16
18
6
7
8
1
2
3
4
5
COM1
COM2
9
12
RF INPUT
95dBm TO
15dBm
330
0.1F
LO INPUT
16dBm
17
11
GAIN TC
COMPENSATION
PLL
13MHz
CERAMIC
BANDPASS
FILTER
Figure 31. Functional Block Diagram
AD6458
11
REV. 0
MXP
275
275
25k
V
BIAS
160k
MXM
VPOS
FROM
MIXER
CORE
MXOP
330
Figure 32. Mixer Output Port
IF Amplifier
Most of the gain in the AD6458 resides in the IF amplifier strip,
which comprises two stages. Both are fully differential and each
has a gain span of 26 dB for the AGC voltage range of 0.2 V to
2.25 V. Thus, in conjunction with the variable gain of the mixer,
the total gain span is 76 dB. The overall IF gain varies from 9
dB to 48 dB for the nominal AGC voltage of 0.2 V to 2.25 V.
Maximum gain is at V
GAIN
= 0.2 V.
The IF input is differential at IFIP and IFIM. Figure 33 shows a
simplified schematic of the IF interface modeled as parallel RC
network.
The IF's small-signal bandwidth is approximately 50 MHz from
IFIP and IFIM through the demodulator.
IFHI
IFLO
C
SH
R
SH
Figure 33. IF Amplifier Port Modeled as a Parallel RC
Network
Gain Scaling
The AD6458's overall gain, expressed in decibels, is linear with
respect to the AGC voltage V
GAIN
at pin GAIN. The gain of all
sections is maximum when V
GAIN
is 0.2, and falls off as the bias
is increased to V
GAIN
= 2.25 and is independent of the power
supply voltage. The gain of all stages changes simultaneously.
The AD6458's gain scaling is also temperature compensated.
The GAIN pin of the AD6458 is an input driven by an external
low impedance voltage source, normally a DAC, under the
control of radio's digital processor.
The gain-control scaling is directly proportional to the reference
voltage applied to the pin GREF and is independent of the
power supply voltage. When this input is set to the nominal
value of 1.2 V, the scale is nominally 27 mV/dB (37 dB/V).
Under these conditions, 76 dB of gain range (mixer plus IF)
corresponds to a control voltage of 0.2 V <= V
G
<= 2.25 V. The
final centering of this 2.05 V range depends on the insertion
losses of the IF filters used.
Pin GREF can be tied to an external voltage reference, V
REF
,
provided, for example, by a AD1580 (1.21 V) voltage reference.
AD6458
IRXP
IRXN
QRXP
QRXN
GREF
GAIN
FREF
AD6421
100pF
100pF
100pF
100pF
0.1F
160
1nF
VCTCXO
IRXP
IRXN
QRXP
QRXN
BREFOUT
BREFCAP
AGC DAC
AFC DAC
Figure 34. Interfacing the AD6458 to the AD6421
Baseband Converter
When using the Analog Devices AD7013 (IS54, TETRA and
satellite receiver applications) and AD7015 or AD6421 (GSM,
DCS1800, PCS1900) baseband converters, the external ref-
erence may also be provided by the reference output of the
baseband converters. The interface between the AD6458 and
the AD6421 baseband converter is shown in Figure 34. The
AD6421 baseband converter provides a V
REF
of 1.23 V; an
auxiliary DAC in the AD6421 can be used to generate the AGC
voltage. Since it uses the same reference voltage, the numerical
input to this DAC provides an accurate RSSI value in digital
form, no longer requiring the reference voltage to have high
absolute accuracy.
I/Q Demodulators
Both demodulators (I and Q) receive their inputs internally
from the IF amplifiers. Each demodulator comprises a full-wave
synchronous detector followed by an 8 MHz, two-pole low-pass
filter, producing differential outputs at pins IRXP and IRXN,
and QRXP and QRXN. Using the I and Q demodulators for IFs
above 50 MHz is precluded by the 5 MHz to 50 MHz range of
the PLL used in the demodulator section.
The I and Q outputs are differential and can swing up to
2.2 V p-p at the low supply voltage of 3.0 V. They are nominally
centered at 1.5 V independently of power supply. They can
therefore directly drive the RX ADCs in the AD6421 baseband
converter, which require an amplitude of 1.23 V to fully load
them when driven by a differential signal. The conversion gain
of the I and Q demodulators is 17 dB.
For IFs of less than 8 MHz, the on-chip low-pass filters (8 MHz
cutoff) do not adequately attenuate the IF or feedthrough prod-
ucts; the maximum input voltage must thus be limited to allow
sufficient headroom at the I and Q outputs, not only for the de-
sired baseband signal but also the unattenuated higher order
demodulation products. These products can be removed by an
external low-pass filter. A simple 1-pole RC filter, with its cor-
ner above the modulation bandwidth, is sufficient to attenuate
undesired outputs. The design of the RC filter is eased by the
4.7 k
resistor integrated at each I and Q output pin.
AD6458
12
REV. 0
I/Q Convention
The AD6458 is a complete IF receive subsystem. Although not
a requirement for using the AD6458, most applications will use
a high-side LO injection on pin LOIP (Pin 4) of the mixer. The
I and Q convention is such that when a spectrum with I leading
Q is presented to the input of the mixer, and a high-side LO is
presented on pin LOIP, I still leads Q at the baseband output of
the AD6458.
Phase-Locked Loop
The demodulators are driven by quadrature signals provided by
a variable frequency quadrature oscillator (VFQO), phase-
locked to a reference signal applied to Pin FREF. When this
signal is at the IF, in-phase and quadrature baseband outputs
are generated at the I output (IRXP and IRXN) and Q output
(QRXP and QRXN), respectively. The quadrature accuracy of
this VFQO is typically 2
at 13 MHz. A simplified diagram of
the FREF input is shown in Figure 35.
FREF
50A PTAT
V
POS
5k
20k
5k
Figure 35. Simplified Schematic of the FREF Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C305224/97
PRINTED IN U.S.A.
20-Lead Plastic SSOP
(RS-20)
20
11
10
1
0.295 (7.50)
0.271 (6.90)
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
PIN 1
SEATING
PLANE
0.008 (0.203)
0.002 (0.050)
0.07 (1.78)
0.066 (1.67)
0.0256
(0.65)
BSC
0.078 (1.98)
0.068 (1.73)
0.009 (0.229)
0.005 (0.127)
0.037 (0.94)
0.022 (0.559)
8
0
The VFQO operates from 5 MHz to 50 MHz and is controlled
by the voltage between V
POS
and FLTR. In normal operation, a
series RC network, forming the PLL loop filter, is connected
from FLTR to V
POS
. The use of an integral sample-hold system
ensures that the frequency-control voltage on pin FLTR re-
mains held during power-down, so reacquisition of the carrier
occurs in less than 80
s.
In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs to
be considered in making filter choices. This is typically < 80
s
for a quadrature phase error of
3
at an IF of 13 MHz. Note
that the VFQO always provides quadrature between its own I
and Q outputs, but the phasing between it and the reference
carrier will swing around the final value during the PLL's set-
tling time.
Bias System
The AD6458 operates from a single supply, V
POS
, usually 3.3 V,
at a typical supply current of 9 mA at midgain and T
A
= +25
C.
Any voltage from 3.0 V to 3.6 V may be used.
The bias system includes a fast acting active high CMOS-
compatible power-up switch, allowing the part to idle at 1
A
when disabled. Biasing is generally proportional-to-absolute-
temperature (PTAT) to ensure stable gain with temperature.
Other special biasing techniques are used to ensure very accu-
rate gain, stable over the full temperature range.
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