CONNECTION DIAGRAMS
8-Lead Plastic Mini-DIP
8-Lead SOIC
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Single Supply, Rail to Rail
Low Power FET-Input Op Amp
AD820
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
FEATURES
True Single Supply Operation
Output Swings Rail-to-Rail
Input Voltage Range Extends Below Ground
Single Supply Capability from +3 V to +36 V
Dual Supply Capability from 1.5 V to 18 V
Excellent Load Drive
Capacitive Load Drive Up to 350 pF
Minimum Output Current of 15 mA
Excellent AC Performance for Low Power
800 A Max Quiescent Current
Unity Gain Bandwidth: 1.8 MHz
Slew Rate of 3.0 V/ s
Excellent DC Performance
800 V Max Input Offset Voltage
1 V/ C Typ Offset Voltage Drift
25 pA Max Input Bias Current
Low Noise
13 nV/
Hz @ 10 kHz
APPLICATIONS
Battery Powered Precision Instrumentation
Photodiode Preamps
Active Filters
12- to 14-Bit Data Acquisition Systems
Medical Instrumentation
Low Power References and Regulators
PRODUCT DESCRIPTION
The AD820 is a precision, low power FET input op amp that
can operate from a single supply of +3.0 V to 36 V, or dual
supplies of
1.5 V to
18 V. It has true single supply capability
with an input voltage range extending below the negative rail,
50
0
10
15
5
1
10
0
30
20
25
35
40
45
9
8
7
6
5
4
3
2
INPUT BIAS CURRENT pA
NUMBER OF UNITS
Figure 1. Typical Distribution of Input Bias Current
allowing the AD820 to accommodate input signals below
ground in the single supply mode. Output voltage swing extends
to within 10 mV of each rail providing the maximum output
dynamic range.
Offset voltage of 800
V max, offset voltage drift of 1
V/
C, typ
input bias currents below 25 pA and low input voltage noise
provide dc precision with source impedances up to a Gigaohm.
1.8 MHz unity gain bandwidth, 93 dB THD at 10 kHz and
3 V/
s slew rate are provided for a low supply current of
800
A. The AD820 drives up to 350 pF of direct capacitive
load and provides a minimum output current of 15 mA. This
allows the amplifier to handle a wide range of load conditions.
This combination of ac and dc performance, plus the outstand-
ing load drive capability, results in an exceptionally versatile
amplifier for the single supply user.
The AD820 is available in three performance grades. The A and
B grades are rated over the industrial temperature range of
40
C to +85
C. There is 3 V grade--the AD820A-3V, rated
over the industrial temperature range.
The AD820 is offered in two varieties of 8-lead package: plastic
DIP, and surface mount (SOIC).
Figure 2. Gain of +2 Amplifier; V
S
= +5, 0, V
IN
= 2.5 V Sine
Centered at 1.25 Volts
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD820
NULL
IN
+IN
V
S
NC
+V
S
V
OUT
NULL
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
AD820
NC
IN
+IN
V
S
NC
+V
S
V
OUT
NC
NC = NO CONNECT
REV. B
2
AD820SPECIFICATIONS
(V
S
= 0, 5 volts @ T
A
= +25 C, V
CM
= 0 V, V
OUT
= 0.2 V unless otherwise noted)
AD820A
AD820B
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Units
DC PERFORMANCE
Initial Offset
0.1
0.8
0.1
0.4
mV
Max Offset over Temperature
0.5
1.2
0.5
0.9
mV
Offset Drift
2
2
V/
C
Input Bias Current
V
O
= 0 V to 4 V
2
25
2
10
pA
at T
MAX
0.5
5
0.5
2.5
nA
Input Offset Current
2
20
2
10
pA
at T
MAX
0.5
0.5
nA
Open-Loop Gain
V
O
= 0.2 V to 4 V
R
L
= 100k
400
1000
500
1000
V/mV
T
MIN
to T
MAX
400
400
V/mV
R
L
= 10k
80
150
80
150
V/mV
T
MIN
to T
MAX
80
80
V/mV
R
L
= 1k
15
30
15
30
V/mV
T
MIN
to T
MAX
10
10
V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
2
V p-p
f = 10 Hz
25
25
nV/
Hz
f = 100 Hz
21
21
nV/
Hz
f = 1 kHz
16
16
nV/
Hz
f = 10 kHz
13
13
nV/
Hz
Input Current Noise
0.1 Hz to 10 Hz
18
18
fA p-p
f = 1 kHz
0.8
0.8
fA/
Hz
Harmonic Distortion
R
L
= 10k to 2.5 V
f = 10 kHz
V
O
= 0.25 V to 4.75 V
93
93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
1.8
1.8
MHz
Full Power Response
V
O
p-p = 4.5 V
210
210
kHz
Slew Rate
3
3
V/
s
Settling Time
to 0.1%
V
O
= 0.2 V to 4.5 V
1.4
1.4
s
to 0.01%
1.8
1.8
s
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
0.2
4
0.2
4
V
T
MIN
to T
MAX
0.2
4
0.2
4
V
CMRR
V
CM
= 0 V to +2 V
66
80
72
80
dB
T
MIN
to T
MAX
66
66
dB
Input Impedance
Differential
10
13
0.5
10
13
0.5
pF
Common Mode
10
13
2.8
10
13
2.8
pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
V
OL
V
EE
I
SINK
= 20
A
5
7
5
7
mV
T
MIN
to T
MAX
10
10
mV
V
CC
V
OH
I
SOURCE
= 20
A
10
14
10
14
mV
T
MIN
to T
MAX
20
20
mV
V
OL
V
EE
I
SINK
= 2 mA
40
55
40
55
mV
T
MIN
to T
MAX
80
80
mV
V
CC
V
OH
I
SOURCE
= 2 mA
80
110
80
110
mV
T
MIN
to T
MAX
160
160
mV
V
OL
V
EE
I
SINK
= 15 mA
300
500
300
500
mV
T
MIN
to T
MAX
1000
1000
mV
V
CC
V
OH
I
SOURCE
= 15 mA
800
1500
800
1500
mV
T
MIN
to T
MAX
1900
1900
mV
Operating Output Current
15
15
mA
T
MIN
to T
MAX
12
12
mA
Short Circuit Current
25
25
mA
Capacitive Load Drive
350
350
pF
POWER SUPPLY
Quiescent Current
T
MIN
to T
MAX
620
800
620
800
A
Power Supply Rejection
V
S
+ = 5 V to 15 V
70
80
66
80
dB
T
MIN
to T
MAX
70
66
dB
AD820
3
REV. B
(V
S
= +5 volts @ T
A
= +25 C, V
CM
= 0 V, V
OUT
= 0 V unless otherwise noted)
AD820A
AD820B
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Units
DC PERFORMANCE
Initial Offset
0.1
0.8
0.3
0.4
mV
Max Offset over Temperature
0.5
1.5
0.5
1
mV
Offset Drift
2
2
V/
C
Input Bias Current
V
CM
= 5 V to 4 V
2
25
2
10
pA
at T
MAX
0.5
5
0.5
2.5
nA
Input Offset Current
2
20
2
10
pA
at T
MAX
0.5
0.5
nA
Open-Loop Gain
V
O
= 4 V to 4 V
R
L
= 100k
400
1000
400
1000
V/mV
T
MIN
to T
MAX
400
400
V/mV
R
L
= 10k
80
150
80
150
V/mV
T
MIN
to T
MAX
80
80
V/mV
R
L
= 1k
20
30
20
30
V/mV
T
MIN
to T
MAX
10
10
V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
2
V p-p
f = 10 Hz
25
25
nV/
Hz
f = 100 Hz
21
21
nV/
Hz
f = 1 kHz
16
16
nV/
Hz
f = 10 kHz
13
13
nV/
Hz
Input Current Noise
0.1 Hz to 10 Hz
18
18
fA p-p
f = 1 kHz
0.8
0.8
fA/
Hz
Harmonic Distortion
R
L
= 10k
f = 10 kHz
V
O
=
4.5 V
93
93
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
1.9
1.8
MHz
Full Power Response
V
O
p-p = 9 V
105
105
kHz
Slew Rate
3
3
V/
s
Settling Time
to 0.1%
V
O
= 0 V to
4.5 V
1.4
1.4
s
to 0.01%
1.8
1.8
s
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
5.2
4
5.2
4
V
T
MIN
to T
MAX
5.2
4
5.2
4
V
CMRR
V
CM
= 5 V to +2 V
66
80
72
80
dB
T
MIN
to T
MAX
66
66
dB
Input Impedance
Differential
10
13
0.5
10
13
0.5
pF
Common Mode
10
13
2.8
10
13
2.8
pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
V
OL
V
EE
I
SINK
= 20
A
5
7
5
7
mV
T
MIN
to T
MAX
10
10
mV
V
CC
V
OH
I
SOURCE
= 20
A
10
14
10
14
mV
T
MIN
to T
MAX
20
20
mV
V
OL
V
EE
I
SINK
= 2 mA
40
55
40
55
mV
T
MIN
to T
MAX
80
80
mV
V
CC
V
OH
I
SOURCE
= 2 mA
80
110
80
110
mV
T
MIN
to T
MAX
160
160
mV
V
OL
V
EE
I
SINK
= 15 mA
300
500
300
500
mV
T
MIN
to T
MAX
1000
1000
mV
V
CC
V
OH
I
SOURCE
= 15 mA
800
1500
800
1500
mV
T
MIN
to T
MAX
1900
1900
mV
Operating Output Current
15
15
mA
T
MIN
to T
MAX
12
12
mA
Short Circuit Current
30
30
mA
Capacitive Load Drive
350
350
pF
POWER SUPPLY
Quiescent Current
T
MIN
to T
MAX
650
800
620
800
A
Power Supply Rejection
V
S
+ = 5 V to 15 V
70
80
70
80
dB
T
MIN
to T
MAX
70
70
dB
AD820A
AD820B
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Units
DC PERFORMANCE
Initial Offset
0.4
2
0.3
1.0
mV
Max Offset over Temperature
0.5
3
0.5
2
mV
Offset Drift
2
2
V/
C
Input Bias Current
V
CM
= 0 V
2
25
2
10
pA
V
CM
= 10 V
40
40
pA
at T
MAX
V
CM
= 0 V
0.5
5
0.5
2.5
nA
Input Offset Current
2
20
2
10
pA
at T
MAX
0.5
0.5
nA
Open-Loop Gain
V
O
= +10 V to 10 V
R
L
= 100k
500
2000
500
2000
V/mV
T
MIN
to T
MAX
500
500
V/mV
R
L
= 10k
100
500
100
500
V/mV
T
MIN
to T
MAX
100
100
V/mV
R
L
= 1k
30
45
30
45
V/mV
T
MIN
to T
MAX
20
20
V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
2
V p-p
f = 10 Hz
25
25
nV/
Hz
f = 100 Hz
21
21
nV/
Hz
f = 1 kHz
16
16
nV/
Hz
f = 10 kHz
13
13
nV/
Hz
Input Current Noise
0.1 Hz to 10 Hz
18
18
fA p-p
f = 1 kHz
0.8
0.8
fA/
Hz
Harmonic Distortion
R
L
= 10k
f = 10 kHz
V
O
=
10 V
85
85
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
1.9
1.9
MHz
Full Power Response
V
O
p-p = 20 V
45
45
kHz
Slew Rate
3
3
V/
s
Settling Time
to 0.1%
V
O
= 0 V to
10 V
4.1
4.1
s
to 0.01%
4.5
4.5
s
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
15.2
14
15.2
14
V
T
MIN
to T
MAX
15.2
14
15.2
14
V
CMRR
V
CM
= 15 V to 12 V
70
80
74
90
dB
T
MIN
to T
MAX
70
74
dB
Input Impedance
Differential
10
13
0.5
10
13
0.5
pF
Common Mode
10
13
2.8
10
13
2.8
pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
V
OL
V
EE
I
SINK
= 20
A
5
7
5
7
mV
T
MIN
to T
MAX
10
10
mV
V
CC
V
OH
I
SOURCE
= 20
A
10
14
10
14
mV
T
MIN
to T
MAX
20
20
mV
V
OL
V
EE
I
SINK
= 2 mA
40
55
40
55
mV
T
MIN
to T
MAX
80
80
mV
V
CC
V
OH
I
SOURCE
= 2 mA
80
110
80
110
mV
T
MIN
to T
MAX
160
160
mV
V
OL
V
EE
I
SINK
= 15 mA
300
500
300
500
mV
T
MIN
to T
MAX
1000
1000
mV
V
CC
V
OH
I
SOURCE
= 15 mA
800
1500
800
1500
mV
T
MIN
to T
MAX
1900
1900
mV
Operating Output Current
20
20
mA
T
MIN
to T
MAX
15
15
mA
Short Circuit Current
45
45
mA
Capacitive Load Drive
350
350
POWER SUPPLY
Quiescent Current
T
MIN
to T
MAX
700
900
700
900
A
Power Supply Rejection
V
S
+ = 5 V to 15 V
70
80
70
80
dB
T
MIN
to T
MAX
70
70
dB
AD820SPECIFICATIONS
4
REV. B
(V
S
= 15 volts @ T
A
= +25 C, V
CM
= 0 V, V
OUT
= 0 V unless otherwise noted)
(V
S
= 0, 3 volts @ T
A
= +25 C, V
CM
= 0 V, V
OUT
= 0.2 V unless otherwise noted)
AD820A-3V
Parameter
Conditions
Min
Typ
Max
Units
DC PERFORMANCE
Initial Offset
0.2
1
mV
Max Offset over Temperature
0.5
1.5
mV
Offset Drift
1
V/
C
Input Bias Current
V
CM
= 0 V to +2 V
2
25
pA
at T
MAX
0.5
5
nA
Input Offset Current
2
20
pA
at T
MAX
0.5
nA
Open-Loop Gain
V
O
= 0.2 V to 2 V
R
L
= 100k
300
1000
V/mV
T
MIN
to T
MAX
400
V/mV
R
L
= 10k
60
150
V/mV
T
MIN
to T
MAX
80
V/mV
R
L
= 1k
10
30
V/mV
T
MIN
to T
MAX
8
V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
0.1 Hz to 10 Hz
2
V p-p
f = 10 Hz
25
nV/
Hz
f = 100 Hz
21
nV/
Hz
f = 1 kHz
16
nV/
Hz
f = 10 kHz
13
nV/
Hz
Input Current Noise
0.1 Hz to 10 Hz
18
fA p-p
f = 1 kHz
0.8
fA/
Hz
Harmonic Distortion
R
L
= 10k to 1.5 V
f = 10 kHz
V
O
=
1.25 V
92
dB
DYNAMIC PERFORMANCE
Unity Gain Frequency
1.5
MHz
Full Power Response
V
O
p-p = 2.5 V
240
kHz
Slew Rate
3
V/
s
Settling Time
to 0.1%
V
O
= 0.2 V to 2.5 V
1
s
to 0.01%
1.4
s
INPUT CHARACTERISTICS
Common-Mode Voltage Range
1
0.2
2
V
T
MIN
to T
MAX
0.2
2
V
CMRR
V
CM
= 0 V to +1 V
60
74
dB
T
MIN
to T
MAX
60
dB
Input Impedance
Differential
10
13
0.5
pF
Common Mode
10
13
2.8
pF
OUTPUT CHARACTERISTICS
Output Saturation Voltage
2
V
OL
V
EE
I
SINK
= 20
A
5
7
mV
T
MIN
to T
MAX
10
mV
V
CC
V
OH
I
SOURCE
= 20
A
10
14
mV
T
MIN
to T
MAX
20
mV
V
OL
V
EE
I
SINK
= 2 mA
40
55
mV
T
MIN
to T
MAX
80
mV
V
CC
V
OH
I
SOURCE
= 2 mA
80
110
mV
T
MIN
to T
MAX
160
mV
V
OL
V
EE
I
SINK
= 10 mA
200
400
mV
T
MIN
to T
MAX
400
mV
V
CC
V
OH
I
SOURCE
= 10 mA
500
1000
mV
T
MIN
to T
MAX
1000
mV
Operating Output Current
15
mA
T
MIN
to T
MAX
12
mA
Short Circuit Current
18
25
mA
T
MIN
to T
MAX
15
mA
Capacitive Load Drive
350
pF
POWER SUPPLY
Quiescent Current
T
MIN
to T
MAX
620
800
A
Power Supply Rejection
V
S
+ = 3 V to 15 V
70
80
dB
T
MIN
to T
MAX
70
dB
AD820
REV. B
5
REV. B
6
AD820SPECIFICATIONS
NOTES
1
This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+ V
S
1 V) to +V
S
.
Common-mode error voltage is typically less than 5 mV with the common-mode voltage set at 1 volt below the positive supply.
2
V
OL
V
EE
is defined as the difference between the lowest possible output voltage (V
OL
) and the minus voltage supply rail (V
EE
).
V
CC
V
OH
is defined as the difference between the highest possible output voltage (V
OH
) and the positive supply voltage (V
CC
).
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
Plastic DIP (N) . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Watts
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 Watts
Input Voltage . . . . . . . . . . . . . . (+V
S
+ 0.2 V) to (20 V + V
S
)
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .
30 V
Storage Temperature Range (N) . . . . . . . . . 65
C to +125
C
Storage Temperature Range (R) . . . . . . . . . 65
C to +150
C
Operating Temperature Range
AD820A/B . . . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
Lead Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +260
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
8-Lead Plastic DIP Package:
JA
= 90
C/Watt
8-Lead SOIC Package:
JA
= 160
C/Watt
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Options
AD820AN
40
C to +85
C
8-Lead Plastic Mini-DIP
N-8
AD820BN
40
C to +85
C
8-Lead Plastic Mini-DIP
N-8
AD820AR
40
C to +85
C
8-Lead SOIC
R-8
AD820BR
40
C to +85
C
8-Lead SOIC
R-8
AD820AR-3V
40
C to +85
C
8-Lead SOIC
R-8
AD820AN-3V
40
C to +85
C
8-Lead Plastic Mini-DIP
N-8
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD820 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
0.5
50
0
0
30
10
0.4
20
0.5
40
0.4
0.3
0.2
0.1
0.1
0.2
0.3
OFFSET VOLTAGE mV
NUMBER OF UNITS
V
S
= 0V, 5V
Figure 3. Typical Distribution of Offset Voltage (248 Units)
V
S
= 5V
V
S
= 15V
OFFSET VOLTAGE DRIFT V/ C
48
0
10
24
8
8
16
10
40
32
8
4
2
0
6
2
4
6
% IN BIN
Figure 4. Typical Distribution of Offset Voltage Drift
(120 Units)
50
0
10
15
5
1
10
0
30
20
25
35
40
45
9
8
7
6
5
4
3
2
INPUT BIAS CURRENT pA
NUMBER OF UNITS
Figure 5. Typical Distribution of Input Bias Current
(213 Units)
INPUT BIAS CURRENT pA
5
0
5
5
4
5
4
3
2
1
0
1
2
3
COMMON-MODE VOLTAGE Volts
V
S
= 5V
V
S
= 0V, +5V AND 5V
Figure 6. Input Bias Current vs. Common-Mode
Voltage; V
S
= +5 V, 0 V and V
S
=
5 V
INPUT BIAS CURRENT pA
COMMON-MODE VOLTAGE Volts
1k
10
0.1
16
12
16
12
8
4
0
4
8
100
1
Figure 7. Input Bias Current vs. Common-Mode
Voltage; V
S
=
15 V
100k
100
0.1
20
40
140
120
100
80
60
1k
10k
1
10
TEMPERATURE C
INPUT BIAS CURRENT pA
Figure 8. Input Bias Current vs. Temperature;
V
S
= 5 V, V
CM
= 0
Typical CharacteristicsAD820
REV. B
7
V
S
= 0V, 3V
V
S
= 15V
10M
100k
10k
100
1k
100k
10k
1M
LOAD RESISTANCE
OPEN-LOOP GAIN V/V
V
S
= 0V, 5V
Figure 9. Open-Loop Gain vs. Load Resistance
R
L
= 10k
R
L
= 100k
140
10M
100k
10k
1M
60
40
120
100
80
60
40
20
0
20
TEMPERATURE C
OPEN-LOOP GAIN V/V
R
L
= 600
V
S
= 0V, 5V
V
S
= 0V, 5V
V
S
= 0V, 5V
V
S
= 15V
V
S
= 15V
V
S
= 15V
Figure 10. Open-Loop Gain vs. Temperature
R
L
= 100k
R
L
= 600
300
300
16
0
200
12
100
16
200
100
12
4
0
4
8
8
OUTPUT VOLTAGE Volts
INPUT VOLTAGE
V
R
L
= 10k
Figure 11. Input Error Voltage vs. Output Voltage for
Resistive Loads
NEG RAIL
POS RAIL
R
L
= 2k
R
L
= 20k
POS
RAIL
R
L
= 100k
40
40
0
300
20
20
60
0
180
240
120
OUTPUT VOLTAGE FROM VOLTAGE RAILS mV
INPUT VOLTAGE
V
NEG RAIL
NEG RAIL
POS RAIL
Figure 12. Input Error Voltage with Output Voltage within
300 mV of Either Supply Rail for Various Resistive Loads;
V
S
=
5 V
1k
100
1
10
10k
1k
100
1
FREQUENCY Hz
10
INPUT VOLTAGE NOISE nV/
Hz
Figure 13. Input Voltage Noise vs. Frequency
R
L
= 10k
A
CL
= 1
V
S
= 0V, 5V; V
OUT
= 4.5V p-p
V
S
= 0V, 3V; V
OUT
= 2.5V p-p
V
S
= 5V; V
OUT
= 9V p-p
40
90
110
100
1k
100k
10k
60
100
80
70
50
FREQUENCY Hz
THD dB
V
S
= 15V; V
OUT
= 20V p-p
Figure 14. Total Harmonic Distortion vs. Frequency
AD820Typical Characteristics
REV. B
8
AD820
REV. B
9
100
40
20
10
100
10M
1M
100k
10k
1k
60
80
0
20
FREQUENCY Hz
OPEN-LOOP GAIN dB
100
40
20
60
80
0
20
PHASE MARGIN IN DEGREES
GAIN
PHASE
R
L
= 2k
C
L
= 100pF
Figure 15. Open-Loop Gain and Phase Margin vs.
Frequency
A
CL
= +1
V
S
= 15V
1k
100
0.01
100
1k
10M
1M
100k
10k
10
1
0.1
FREQUENCY Hz
OUTPUT IMPEDANCE
Figure 16. Output Impedance vs. Frequency
1%
1%
ERROR
0.01%
0.1%
16
16
5.0
8
12
1.0
0.0
0
4
4
8
12
4.0
3.0
2.0
SETTLING TIME s
OUTPUT SWING FROM 0 TO
Volts
Figure 17. Output Swing and Error vs. Settling Time
100
50
0
10
100
10M
1M
100k
10k
1k
60
70
80
90
10
20
30
40
FREQUENCY Hz
COMMON-MODE REJECTION dB
V
S
= 0V, 5V
AND
V
S
= 0V, 3V
V
S
= 15V
Figure 18. Common-Mode Rejection vs. Frequency
POSITIVE
RAIL
+125 C
+125 C
+25 C
NEGATIVE
RAIL
55 C
COMMON-MODE VOLTAGE FROM SUPPLY RAILS Volts
COMMON-MODE ERROR VOLTAGE mV
5
0
3
3
1
2
1
4
2
1
0
55 C
Figure 19. Absolute Common-Mode Error vs. Common-
Mode Voltage from Supply Rails (V
S
V
CM
)
V
OL
V
S
1000
100
0
0.001
0.01
100
10
1
0.1
10
LOAD CURRENT mA
OUTPUT SATURATION VOLTAGE mV
V
S
V
OH
Figure 20. Output Saturation Voltage vs Load Current
-
AD820
REV. B
10
I
SOURCE
= 10mA
I
SINK
= 10mA
I
SOURCE
= 1mA
I
SINK
= 1mA
I
SOURCE
= 10 A
I
SINK
= 10 A
1000
100
1
60
40
140
120
100
80
60
40
20
0
20
10
TEMPERATURE C
OUTPUT SATURATION VOLTAGE mV
Figure 21. Output Saturation Voltage vs. Temperature
OUT
V
S
= 15V
V
S
= 15V
V
S
= 0V, 5V
V
S
= 0V, 3V
V
S
= 0V, 3V
V
S
= 0V, 5V
TEMPERATURE C
SHORT CIRCUIT CURRENT LIMIT mA
80
0
140
20
10
40
60
40
30
50
60
70
120
100
80
60
40
20
0
20
+
+
+
Figure 22. Short Circuit Current Limit vs. Temperature
T = +125 C
T = +25 C
T = 55 C
TOTAL SUPPLY VOLTAGE Volts
QUIESCENT CURRENT
A
800
0
36
200
100
4
0
400
300
500
600
700
30
28
24
20
16
12
8
Figure 23. Quiescent Current vs. Supply Voltage vs.
Temperature
FREQUENCY Hz
POWER SUPPLY REJECTION dB
120
60
0
10
100
10M
1M
100k
10k
1k
30
90
80
20
50
110
70
10
40
100
PSRR
+PSRR
Figure 24. Power Supply Rejection vs. Frequency
R1 = 2k
FREQUENCY Hz
OUTPUT VOLTAGE Volts
30
15
0
10k
100k
10M
1M
10
5
20
25
V
S
= 15V
V
S
= 0V ,3V
V
S
= 0V, 5V
Figure 25. Large Signal Frequency Response
AD820Typical Characteristics
REV. B
10
AD820
REV. B
11
Figure 29. Large Signal Response Unity Gain Follower;
V
S
=
15 V, R
L
= 10 k
Figure 30. Small Signal Response Unity Gain Follower;
V
S
=
15 V, R
L
= 10 k
GND
Figure 31. V
S
= +5 V, 0 V; Unity Gain Follower Response
to 0 V to 5 V Step
AD820
R
L
100pF
V
OUT
0.01 F
+V
S
V
IN
0.01 F
V
S
3
2
4
7
6
Figure 26. Unity-Gain Follower
Figure 27. 20 V, 25 kHz Sine Input; Unity Gain Follower;
R
L
= 600
, V
S
=
15 V
GND
Figure 28. V
S
= +5 V, 0 V; Unity Gain Follower Response
to 0 V to 4 V Step
AD820
REV. B
12
GND
Figure 35. V
S
= +5 V, 0 V; Unity Gain Follower Response
to 40 mV Step Centered 40 mV Above Ground
100
GND
Figure 36. V
S
= +5 V, 0 V; Gain of Two Inverter Response
to 20 mV Step, Centered 20 mV Below Ground
GND
Figure 37. V
S
= 3 V, 0 V; Gain of Two Inverter, V
IN
= 1.25 V,
25 kHz, Sine Wave Centered at 0.75 V, R
L
= 600
AD820
R
L
100pF
V
OUT
0.01 F
+V
S
V
IN
3
2
4
7
6
Figure 32. Unity-Gain Follower
10k
20k
V
IN
AD820
R
L
100pF
V
OUT
0.01 F
+V
S
3
2
4
7
6
Figure 33. Gain of Two Inverter
GND
Figure 34. V
S
= +5 V, 0 V; Gain of Two Inverter Response
to 2.5 V Step Centered 1.25 V Below Ground
AD820
REV. B
13
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD820, n-channel JFETs are used to provide a low off-
set, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below V
S
to 1 V
less than +V
S
. Driving the input voltage closer to the positive
rail will cause a loss of amplifier bandwidth (as can be seen by
comparing the large signal responses shown in Figures 28 and
31) and increased common-mode voltage error as illustrated in
Figure 19.
The AD820 does not exhibit phase reversal for input voltages
up to and including +V
S
. Figure 38a shows the response of an
AD820 voltage follower to a 0 V to +5 V (+V
S
) square wave
input. The input and output are superimposed. The output
polarity tracks the input polarity up to +V
S
--no phase reversal.
The reduced bandwidth above a 4 V input causes the rounding
of the output wave form. For input voltages greater than +V
S
, a
resistor in series with the AD820's plus input will prevent phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 38b.
Since the input stage uses n-channel JFETs, input current dur-
ing normal operation is negative; the current flows out from the
input terminals. If the input voltage is driven more positive than
+V
S
0.4 V, the input current will reverse direction as internal
device junctions become forward biased. This is illustrated in
Figure 6.
R
P
AD820
V
OUT
V
IN
+5V
GND
(a)
+V
S
GND
(b)
Figure 38. (a) Response with R
P
= 0; V
IN
from 0 to +V
S
Figure 36.
(b) V
IN
= 0 to +V
S
+ 200 mV
V
OUT
= 0 to +V
S
R
P
= 49.9 k
A current limiting resistor should be used in series with the
input of the AD820 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage will be applied to the AD820 when
V
S
= 0. The
amplifier will be damaged if left in that condition for more than
10 seconds. A 1 k
resistor allows the amplifier to withstand up
to 10 volts of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
Input voltages less than V
S
are a completely different story.
The amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In
addition, the input stage typically maintains picoamp level input
currents across that input voltage range.
The AD820 is designed for 13 nV/
Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 13). This noise performance, along with the
AD820's low input current and current noise means that the
AD820 contributes negligible noise for applications with source
resistances greater than 10 k
and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 39.
AMPLIFIER-GENERATED
NOISE
RESISTOR JOHNSON
NOISE
WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
100k
0.1
10G
100
1
100k
10
10k
10k
1k
1G
100M
10M
1M
SOURCE IMPEDANCE
INPUT VOLTAGE NOISE
V
RMS
1kHz
10Hz
Figure 39. Total Noise vs. Source Impedance
OUTPUT CHARACTERISTICS
The AD820's unique bipolar rail-to-rail output stage swings
within 5 mV of the minus supply and 10 mV of the positive
supply with no external resistive load. The AD820's approxi-
mate output saturation resistance is 40
sourcing and 20
sinking. This can be used to estimate output saturation voltage
when driving heavier current loads. For instance, when sourcing
5 mA, the saturation voltage to the positive supply rail will be
200 mV, when sinking 5 mA, the saturation voltage to the
minus rail will he 100 mV.
The amplifier's open-loop gain characteristic will change as a
function of resistive load, as shown in Figures 9 through 12. For
load resistances over 20 k
, the AD820's input error voltage is
virtually unchanged until the output voltage is driven to 180 mV
of either supply.
If the AD820's output is driven hard against the output satura-
tion voltage, it will recover within 2
s of the input returning to
the amplifier's linear operating region.
AD820
REV. B
14
Direct capacitive load will interact with the amplifier's effective
output impedance to form an additional pole in the amplifier's
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figure 40 shows the AD820's
pulse response as a unity gain follower driving 350 pF. This
amount of overshoot indicates approximately 20 degrees of
phase margin--the system is stable, but is nearing the edge.
Configurations with less loop gain, and as a result less loop
bandwidth, will be much less sensitive to capacitance load ef-
fects. Figure 41 is a plot of capacitive load that will result in a
20 degree phase margin versus noise gain for the AD820. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
Figure 40. Small Signal Response of AD820 as Unity Gain
Follower Driving 350 pF Capacitive Load
R
I
R
F
CAPACITIVE LOAD FOR 20 PHASE MARGIN pF
5
4
1
300
NOISE GAIN 1+
R
F
R
I
3
2
1k
3k
10k
30k
Figure 41. Capacitive Load Tolerance vs. Noise Gain
Figure 42 shows a possible configuration for extending capaci-
tance load drive capability for a unity gain follower. With these
component values, the circuit will drive 5,000 pF with a 10%
overshoot.
100
20k
AD820
V
OUT
0.01 F
+V
S
V
IN
0.01 F
V
S
3
2
4
7
6
20pF
Figure 42. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
OFFSET VOLTAGE ADJUSTMENT
The AD820's offset voltage is low, so external offset voltage
nulling is not usually required. Figure 43 shows the recom-
mended technique for AD820's packaged in plastic DIPs.
Adjusting offset voltage in this manner will change the offset
voltage temperature drift by 4
V/
C for every millivolt of in-
duced offset. The null pins are not functional for AD820s in the
SO-8 "R" package.
20k
1
AD820
+V
S
V
S
3
2
4
7
6
5
Figure 43. Offset Null
APPLICATIONS
Single Supply Half-Wave and Full-Wave Rectifiers
An AD820 configured as a unity gain follower and operated
with a single supply can be used as a simple half-wave rectifier.
The AD820's inputs maintain picoamp level input currents even
when driven well below the minus supply. The rectifier puts that
behavior to good use, maintaining an input impedance of over
10
11
for input voltages from 1 volt from the positive supply to
20 volts below the negative supply.
The full and half-wave rectifier shown in Figure 44 operates as
follows: when V
IN
is above ground, R1 is bootstrapped through
the unity gain follower A1 and the loop of amplifier A2. This
forces the inputs of A2 to be equal, thus no current flows through
R1 or R2, and the circuit output tracks the input. When V
IN
is
below ground, the output of A1 is forced to ground. The non-
inverting input of amplifier A2 sees the ground level output of
A1, therefore A2 operates as a unity gain inverter. The output at
node C is then a full-wave rectified version of the input. Node B
is a buffered half-wave rectified version of the input. Input volt-
ages up to
18 volts can be rectified, depending on the voltage
supply used.
AD820
REV. B
15
R1
100k
AD820
2
3
6
FULL-WAVE
RECTIFIED OUTPUT
HALF-WAVE
RECTIFIED OUTPUT
R2
100k
A
C
B
AD820
0.01 F
+V
S
V
IN
3
2
4
7
6
A1
A2
0.01 F
+V
S
7
4
A
B
C
Figure 44. Single Supply Half- and Full-Wave Rectifier
4.5 Volt Low Dropout, Low Power Reference
The rail-to-rail performance of the AD820 can be used to pro-
vide low dropout performance for low power reference circuits
powered with a single low voltage supply. Figure 45 shows a
4.5 volt reference using the AD820 and the AD680, a low power
2.5 volt bandgap reference. R2 and R3 set up the required gain
of 1.8 to develop the 4.5 volt output. R1 and C2 form a low-
pass RC filter to reduce the noise contribution of the AD680.
2
3
4
R2
80k
(20k )
U1
AD680
REF
COMMON
+4.5V
OUTPUT
+2.5V
OUTPUT
R3
100k
(25k )
C3
10 F/25V
3
6
7
2
C1
0.1 F
C2
0.1 F FILM
U2
AD820
+5V
+2.5V 10mV
6
R1
100k
4
Figure 45. Single Supply 4.5 Volt Low Dropout Reference
With a 1 mA load, this reference maintains the 4.5 volt output
with a supply voltage down to 4.7 volts. The amplitude of the
recovery transient for a 1 mA to 10 mA step change in load
current is under 20 mV, and settles out in a few microseconds.
Output voltage noise is less than 10
V rms in a 25 kHz noise
bandwidth.
Low Power Three-Pole Sallen Key Low-Pass Filter
The AD820's high input impedance makes it a good selection
for active filters. High value resistors can be used to construct
low frequency filters with capacitors much less than 1
F. The
AD820's picoamp level input currents contribute minimal dc
errors.
Figure 46 shows an example, a 10 Hz three-pole Sallen Key
Filter. The high value used for R1 minimizes interaction with
signal source resistance. Pole placement in this version of the
filter minimizes the Q associated with the two-pole section of
the filter. This eliminates any peaking of the noise contribution
of resistors R1, R2, and R3, thus minimizing the inherent out-
put voltage noise of the filter.
FREQUENCY Hz
0.1
FILTER GAIN RESPONSE dB
0
10
100
20
30
40
50
60
70
80
90
1
10
100
1k
C2
0.022 F
V
OUT
0.01 F
+V
S
V
IN
0.01 F
V
S
3
2
4
7
6
AD820
R1
243k
C3
0.022 F
C1
0.022 F
R2
243k
R3
243k
Figure 46. 10 Hz Sallen Key Low-Pass Filter
AD820
REV. B
16
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP Package
(N-8)
SEATING
PLANE
0.125 (3.18)
MIN
0.035 0.01
(0.89 0.25)
0.033
(0.84)
NOM
0.018 0.003
(0.46 0.08)
0.165 0.01
(4.19 0.25)
0.18 0.03
(4.57 0.75)
8
1
4
5
PIN 1
0.10 (2.54)
BSC
0.39 (9.91)
MAX
0.25
(6.35)
0.31
(7.87)
0.011 0.003
(0.28 0.08)
15
0
0.30 (7.62)
REF
SOIC Package
(R-8)
10
0
0.030 (0.76)
0.018 (0.46)
0.020 (0.051)
45
CHAMF
0.098 (0.2482)
0.075 (0.1905)
8
0
0.190 (4.82)
0.170 (4.32)
0.090
(2.29)
0.244 (6.20)
0.228 (5.79)
8
5
4
1
PIN 1
0.157 (3.99)
0.150 (3.81)
0.150 (3.81)
0.102 (2.59)
0.094 (2.39)
SEATING
PLANE
0.010 (0.25)
0.004 (0.10)
0.019 (0.48)
0.014 (0.36)
0.197 (5.01)
0.189 (4.80)
0.050
(1.27)
BSC
C1792b08/99
PRINTED IN U.S.A.
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