REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Single Supply, Rail-to-Rail
Low Power, FET-Input Op Amp
FEATURES
Single Supply Operation: 3 V to 30 V
Very Low Input Bias Current: 2 pA
Wide Input Voltage Range
Rail-to-Rail Output Swing
Low Supply Current: 500 A/Amp
Wide Bandwidth: 2 MHz
Slew Rate: 2 V/ s
No Phase Reversal
APPLICATIONS
Photo Diode Preamplifier
Battery Powered Instrumentation
Power Supply Control and Protection
Medical Instrumentation
Remote Sensors
Low Voltage Strain Gage Amplifiers
DAC Output Amplifier
GENERAL DESCRIPTION
The AD824 is a quad, FET input, single supply amplifier, fea-
turing rail-to-rail outputs. The combination of FET inputs and
rail-to-rail outputs makes the AD824 useful in a wide variety of
low voltage applications where low input current is a primary
consideration.
The AD824 is guaranteed to operate from a 3 V single supply
up to
15 volt dual supplies.
Fabricated on ADI's complementary bipolar process, the AD824
has a unique input stage that allows the input voltage to safely
extend beyond the negative supply and to the positive supply
without any phase inversion or latchup. The output voltage
swings to within 15 millivolts of the supplies. Capacitive loads
to 350 pF can be handled without oscillation.
The FET input combined with laser trimming provides an input
that has extremely low bias currents with guaranteed offsets be-
low 300
V. This enables high accuracy designs even with high
source impedances. Precision is combined with low noise,
making the AD824 ideal for use in battery powered medical
equipment.
PIN CONFIGURATIONS
14-Lead Epoxy DIP
(N Suffix)
14-Lead Epoxy SO
(R Suffix)
OUT A
IN A
OUT D
IN D
+INB
INB
OUTB
+IN C
IN C
OUT C
+IN A
V+
+IN D
V
1
2
14
13
5
6
7
10
9
8
3
4
12
11
TOP VIEW
(Not to Scale)
AD824
OUT A
IN A
OUT D
IN D
+IN B
IN B
OUT B
+IN C
IN C
OUT C
+IN A
V+
+IN D
V
1
2
14
13
5
6
7
10
9
8
3
4
12
11
TOP VIEW
AD824
AD824
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
Analog Devices, Inc., 1997
16-Lead Epoxy SO
(R Suffix)
1
2
3
4
5
6
7
8
14
13
12
11
10
9
15
16
OUT A
IN A
+IN A
V+
+IN B
IN B
OUT B
IN D
+IN D
V
+IN C
IN C
OUT C
OUT D
NC
NC
NC = NO CONNECT
AD824
Applications for the AD824 include portable medical equipment,
photo diode preamplifiers and high impedance transducer
amplifiers.
The ability of the output to swing rail-to-rail enables designers
to build multistage filters in single supply systems and maintain
high signal-to-noise ratios.
The AD824 is specified over the extended industrial (40
C to
+85
C) temperature range and is available in 14-pin DIP and
narrow 14-pin and 16-pin SO packages.
AD824SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage AD824A
V
OS
0.1
1.0
mV
T
MIN
to T
MAX
1.5
mV
Offset Voltage AD824B
V
OS
300
V
T
MIN
to T
MAX
900
V
Input Bias Current
I
B
2
12
pA
T
MIN
to T
MAX
300
4000
pA
Input Offset Current
I
OS
2
10
pA
T
MIN
to T
MAX
300
pA
Input Voltage Range
0.2
3.0
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 2 V
66
80
dB
V
CM
= 0 V to 3 V
60
74
dB
T
MIN
to T
MAX
60
dB
Input Impedance
10
13
3.3
pF
Large Signal Voltage Gain
A
VO
V
O
= 0.2 V to 4.0 V
R
L
= 2 k
20
40
V/mV
R
L
= 10 k
50
100
V/mV
R
L
= 100 k
250
1000
V/mV
T
MIN
to T
MAX,
R
L
= 100 k
180
400
V/mV
Offset Voltage Drift
V
OS
/
T
2
V/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
SOURCE
= 20
A
4.975
4.988
V
T
MIN
to T
MAX
4.97
4.985
V
I
SOURCE
= 2.5 mA
4.80
4.85
V
T
MIN
to T
MAX
4.75
4.82
V
Output Voltage Low
V
OL
I
SINK
= 20
A
15
25
mV
T
MIN
to T
MAX
20
30
mV
I
SINK
= 2.5 mA
120
150
mV
T
MIN
to T
MAX
140
200
mV
Short Circuit Limit
I
SC
Sink/Source
12
mA
T
MIN
to T
MAX
10
mA
Open-Loop Impedance
Z
OUT
f = 1 MHz, A
V
= 1
100
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 12 V
70
80
dB
T
MIN
to T
MAX
66
dB
Supply Current/Amplifier
I
SY
T
MIN
to T
MAX
500
600
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
, A
V
= 1
2
V/
s
Full-Power Bandwidth
BW
P
1% Distortion, V
O
= 4 V p-p
150
kHz
Settling Time
t
S
V
OUT
= 0.2 V to 4.5 V, to 0.01%
2.5
s
Gain Bandwidth Product
GBP
2
MHz
Phase Margin
o
No Load
50
Degrees
Channel Separation
CS
f = 1 kHz, R
L
= 2 k
123
dB
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
2
V p-p
Voltage Noise Density
e
n
f = 1 kHz
16
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
0.8
fA/
Hz
Total Harmonic Distortion
THD
f = 10 kHz, R
L
= 0, A
V
= +1
0.005
%
(@ V
S
= +5.0 V, V
CM
= 0 V, V
OUT
= 0.2 V, T
A
= +25 C unless otherwise noted)
2
REV. A
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage AD824A
V
OS
0.5
2.5
mV
T
MIN
to T
MAX
0.6
4.0
mV
Offset Voltage AD824B
V
OS
0.5
1.5
mV
T
MIN
to T
MAX
0.6
2.5
mV
Input Bias Current
I
B
V
CM
= 0 V
4
35
pA
T
MIN
to T
MAX
500
4000
pA
Input Bias Current
I
B
V
CM
= 10 V
25
pA
Input Offset Current
I
OS
3
20
pA
T
MIN
to T
MAX
500
pA
Input Voltage Range
15
13
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 15 V to 13 V
70
80
dB
T
MIN
to T
MAX
66
dB
Input Impedance
10
13
3.3
pF
Large Signal Voltage Gain
A
VO
Vo = 10 V to +10 V;
R
L
= 2 k
12
50
V/mV
R
L
= 10 k
50
200
V/mV
R
L
= 100 k
300
2000
V/mV
T
MIN
to T
MAX,
R
L
= 100 k
200
1000
V/mV
Offset Voltage Drift
V
OS
/
T
2
V/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
SOURCE
= 20
A
14.975
14.988
V
T
MIN
to T
MAX
14.970
14.985
V
I
SOURCE
= 2.5 mA
14.80
14.85
V
T
MIN
to T
MAX
14.75
14.82
V
Output Voltage Low
V
OL
I
SINK
= 20
A
14.985
14.975
V
T
MIN
to T
MAX
14.98
14.97
V
I
SINK
= 2.5 mA
14.88
14.85
V
T
MIN
to T
MAX
14.86
14.8
V
Short Circuit Limit
I
SC
Sink/Source, T
MIN
to T
MAX
8
20
mA
Open-Loop Impedance
Z
OUT
f = 1 MHz, A
V
= 1
100
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 15 V
70
80
dB
T
MIN
to T
MAX
68
dB
Supply Current/Amplifier
I
SY
V
O
= 0 V
560
625
A
T
MIN
to T
MAX
675
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
, A
V
= 1
2
V/
s
Full-Power Bandwidth
BW
P
1% Distortion, V
O
= 20 V p-p
33
kHz
Settling Time
t
S
V
OUT
= 0 V to 10 V, to 0.01%
6
s
Gain Bandwidth Product
GBP
2
MHz
Phase Margin
o
50
Degrees
Channel Separation
CS
f = 1 kHz, R
L
=2 k
123
dB
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
2
V p-p
Voltage Noise Density
e
n
f = 1 kHz
16
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
1.1
fA/
Hz
Total Harmonic Distortion
THD
f =10 kHz, V
O
= 3 V rms,
R
L
= 10 k
0.005
%
(@ V
S
= 15.0 V, V
OUT
= 0 V, T
A
= +25 C unless otherwise noted)
AD824
3
REV. A
AD824SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage AD824A -3 V
V
OS
0.2
1.0
mV
T
MIN
to T
MAX
1.5
mV
Input Bias Current
I
B
2
12
pA
T
MIN
to T
MAX
250
4000
pA
Input Offset Current
I
OS
2
10
pA
T
MIN
to T
MAX
250
pA
Input Voltage Range
0
1
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 1 V
58
74
dB
T
MIN
to T
MAX
56
dB
Input Impedance
10
13
3.3
pF
Large Signal Voltage Gain
A
VO
V
O
= 0.2 V to 2.0 V
R
L
= 2 k
10
20
V/mV
R
L
= 10 k
30
65
V/mV
R
L
= 100 k
180
500
V/mV
T
MIN
to T
MAX,
R
L
= 100 k
90
250
V/mV
Offset Voltage Drift
V
OS
/
T
2
V/
C
OUTPUT CHARACTERISTICS
Output Voltage High
V
OH
I
SOURCE
= 20
A
2.975
2.988
V
T
MIN
to T
MAX
2.97
2.985
V
I
SOURCE
= 2.5 mA
2.8
2.85
V
T
MIN
to T
MAX
2.75
2.82
V
Output Voltage Low
V
OL
I
SINK
= 20
A
15
25
mV
T
MIN
to T
MAX
20
30
mV
I
SINK
= 2.5 mA
120
150
mV
T
MIN
to T
MAX
140
200
mV
Short Circuit Limit
I
SC
Sink/Source
8
mA
Short Circuit Limit
I
SC
Sink/Source, T
MIN
to T
MAX
6
mA
Open-Loop Impedance
Z
OUT
f = 1 MHz, A
V
= 1
100
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= 2.7 V to 12 V,
70
dB
T
MIN
to T
MAX
66
dB
Supply Current/Amplifier
I
SY
V
O
= 0.2 V, T
MIN
to T
MAX
500
600
A
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
=10 k
, A
V
= 1
2
V/
s
Full-Power Bandwidth
BW
P
1% Distortion, V
O
= 2 V p-p
300
kHz
Settling Time
t
S
V
OUT
= 0.2 V to 2.5 V, to 0.01%
2
s
Gain Bandwidth Product
GBP
2
MHz
Phase Margin
o
50
Degrees
Channel Separation
CS
f = 1 kHz, R
L
= 2 k
123
dB
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
2
V p-p
Voltage Noise Density
e
n
f = 1 kHz
16
nV/
Hz
Current Noise Density
i
n
0.8
fA/
Hz
Total Harmonic Distortion
THD
f = 10 kHz, R
L
= 0, A
V
= +1
0.01
%
(@ V
S
= +3.0 V, V
CM
= 0 V, V
OUT
= 0.2 V, T
A
= +25 C unless otherwise noted)
4
REV. A
AD824
REV. A
5
WAFER TEST LIMITS
Parameter
Symbol
Conditions
Limit
Units
Offset Voltage
V
OS
1.0
mV max
Input Bias Current
I
B
12
pA max
Input Offset Current
I
OS
20
pA
Input Voltage Range
V
CM
0.2 to 3.0
V min
Common-Mode Rejection Ratio
CMRR
V
CM
= 0 V to 2 V
66
dB min
Power Supply Rejection Ratio
PSRR
V = + 2.7 V to +12 V
70
V/V
Large Signal Voltage Gain
A
VO
R
L
= 2 k
15
V/mV min
Output Voltage High
V
OH
I
SOURCE
= 20
A
4.975
V min
Output Voltage Low
V
OL
I
SINK
= 20
A
25
mV max
Supply Current/Amplifier
I
SY
V
O
= 0 V, R
L
=
600
A max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly
methods and normal yield loss, yield after packaging is not guaranteed for
standard product dice. Consult factory to negotiate specifications based on dice
lot qualifications through sample lot assembly and testing.
(@ V
S
= +5.0 V, V
CM
= 0 V, T
A
= +25 C unless otherwise noted)
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD824 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . V
S
0.2 V to +V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .
30 V
Output Short Circuit Duration to GND . . . . . . . . . Indefinite
Storage Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Operating Temperature Range
AD824A, B . . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
Junction Temperature Range
N, R Package . . . . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300
C
Package Type
JA
2
JC
Units
14-Pin Plastic DIP (N)
76
33
C/W
14-Pin SOIC (R)
120
36
C/W
16-Pin SOIC (R)
92
27
C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts unless
otherwise noted.
2
JA
is specified for the worst case conditions, i.e.,
JA
is specified for device in socket
for P-DIP packages;
JA
is specified for device soldered in circuit board for SOIC
package.
ORDERING GUIDE
Temperature
Model
Range
Package Option
AD824AN
40
C to +85
C
14-Pin Plastic DIP
AD824BN
40
C to +85
C
14-Pin Plastic DIP
AD824AR
40
C to +85
C
14-Pin SOIC
AD824AR-3V
40
C to +85
C
14-Pin SOIC
AD824AN-3V
40
C to +85
C
14-Pin Plastic DIP
AD824AR-14
40
C to +85
C
14-Pin SOIC
AD824AR-14-3V
40
C to +85
C
14-Pin SOIC
AD824AR-16
40
C to +85
C
16-Pin SOIC
AD824AChips
+25
C
DICE
DICE CHARACTERISTICS
AD824 Die Size 0.70 X 0.130 inch, 9,100 sq. mils.
Substrate (Die Backside) Is Connected to V+. Transistor
Count, 143.
I6
R1
R2
R9
R7
R17
R14
R12
R13
R15
V
CC
I5
Q18
Q29
Q27
Q21
Q20
Q23
Q25
Q24
Q31
Q28
Q22
Q19
Q7
Q6
Q5
Q8
Q3
Q2
Q4
I1
I2
I3
I4
+IN
J1
IN
C1
Q26
V
OUT
J2
V
EE
C3
C2
C4
Figure 1. Simplified Schematic of 1/4 AD824
AD824Typical Characteristics
100
10M
1k
10k
100k
1M
80
60
40
20
0
GAIN dB
180
135
90
45
PHASE Degrees
V
S
= +5V
NO LOAD
10
0%
100
90
1s
50mV
Figure 4. Open-Loop Gain/Phase and Small Signal
Response, V
S
= +5 V, No Load
10M
1k
10k
100k
1M
60
40
20
0
20
GAIN dB
180
135
90
45
PHASE Degrees
V
S
= +5V
C
L
= 220pF
10
0%
100
90
1s
50mV
Figure 5. Open-Loop Gain/Phase and Small Signal
Response, V
S
= +5 V, C
L
= 220 pF
100
10M
1k
10k
100k
1M
V
S
=
15V
NO LOAD
80
60
40
20
0
GAIN dB
180
135
90
45
PHASE Degrees
10
0%
100
90
1s
50mV
Figure 2. Open-Loop Gain/Phase and Small Signal
Response, V
S
=
15 V, No Load
V
S
=
15V
C
L
= 100pF
100
10M
1k
10k
100k
1M
80
60
40
20
0
GAIN dB
180
135
90
45
PHASE Degrees
10
0%
100
90
1s
50mV
Figure 3. Open-Loop Gain/Phase and Small Signal
Response, V
S
=
15 V, C
L
= 100 pF
6
REV. A
AD824
10M
1k
10k
100k
1M
60
40
20
0
20
GAIN dB
180
135
90
45
PHASE Degrees
V
S
= +3V
NO LOAD
10
0%
100
90
1s
50mV
Figure 6. Open-Loop Gain/Phase and Small Signal
Response, V
S
= +3 V, No Load
10M
1k
10k
100k
1M
60
40
20
0
20
GAIN dB
180
135
90
45
PHASE Degrees
V
S
= +3V
C
L
= 220pF
10
0%
100
90
1s
50mV
Figure 7. Open-Loop Gain/Phase and Small Signal
Response, V
S
= +3 V, C
L
= 220 pF
10
0%
100
90
2s
5V
10.810
s
t
Figure 8. Slew Rate, R
L
= 10k
10
0%
100
90
2s
5V
9.950
s
t
10
0%
100
90
100s
5V
V
OUT
Figure 9. Phase Reversal with Inputs Exceeding Supply by
1 Volt
LOAD CURRENT A
0.8
0
1
10m
5
10
50
100
500
1m
5m
0.7
0.4
0.3
0.2
0.1
0.6
0.5
SOURCE
SINK
OUTPUT TO RAIL Volts
Figure 10. Output Voltage to Supply Rail vs. Sink and
Source Load Currents
REV. A
7
AD824Typical Characteristics
OFFSET VOLTAGE DRIFT
NUMBER OF UNITS
14
0
2.5
2.5
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
12
10
8
6
4
2
COUNT = 60
Figure 14. TC V
OS
Distribution, 55
C to +125
C, V
S
= 5, 0
TEMPERATURE
C
150
25
60
140
40
20
0
20
40
60
80
100
120
125
100
75
50
25
0
INPUT OFFSET CURRENT pA
V
S
= 5, 0
Figure 15. Input Offset Current vs. Temperature
INPUT BIAS CURRENT pA
TEMPERATURE
C
100k
20
140
40
60
80
100
120
10k
1k
100
10
1
V
S
= 5, 0
Figure 16. Input Bias Current vs. Temperature
+3V
V
S
15V
5 10 15 20
FREQUENCY kHz
60
40
20
NOISE DENSITY nV/
Hz
Figure 11. Voltage Noise Density
0.1
0.010
0.001
0.0001
20
100
1k
10k
20k
R
L
= 0
A
V
= +1
V
S
= +3
V
S
= +5
V
S
=
15
FREQUENCY Hz
THD+N %
Figure 12. Total Harmonic Distortion
OFFSET VOLTAGE mV
NUMBER OF UNITS
280
0
0.5
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
240
200
160
120
80
40
COUNT = 860
Figure 13. Input Offset Distribution, V
S
= 5, 0
REV. A
8
AD824
REV. A
9
FREQUENCY Hz
120
0
10
10M
100
1k
10k
100k
1M
100
80
60
40
20
COMMON-MODE REJECTION dB
Figure 17. Common-Mode Rejection vs. Frequency
THD dB
FREQUENCY Hz
40
60
120
100
100k
1k
10k
80
100
Figure 18. THD vs. Frequency, 3 V rms
FREQUENCY Hz
100
20
10
10M
100
OPEN-LOOP GAIN dB
1k
10k
100k
1M
80
60
40
20
0
100
20
80
60
40
20
0
PHASE MARGIN Degrees
15V
+3, 0V
Figure 19. Open-Loop Gain and Phase vs. Frequency
.
.
.
FREQUENCY Hz
1k
INPUT VOLTAGE NOISE nV/
Hz
100
1
1
100k
10
100
1k
10k
10
Figure 20. Input Voltage Noise Spectral Density vs.
Frequency
FREQUENCY Hz
120
0
10
10M
100
POWER SUPPLY REJECTION dB
1k
10k
100k
1M
100
80
60
40
20
Figure 21. Power Supply Rejection vs. Frequency
INPUT FREQUENCY Hz
30
0
1k
1M
3k
OUTPUT VOLTAGE Volts
10k
30k
100k
300k
25
20
15
10
5
Figure 22. Large Signal Frequency Response
AD824
10
REV. A
FREQUENCY Hz
80
140
10
100
CROSSTALK dB
1k
10k
100k
90
100
110
120
130
1 TO 4
1 TO 2
1 TO 3
Figure 23. Crosstalk vs. Frequency
FREQUENCY Hz
10k
.01
10
10M
100
OUTPUT IMPEDANCE
1k
10k
100k
1M
1k
100
10
1
.1
Figure 24. Output Impedance vs. Frequency, Gain = +1
Figure 25. Small Signal Response, Unity Gain Follower,
10k 100 pF Load
10
0%
100
90
500ns
20mV
Figure 26. Large Signal Response
TEMPERATURE
C
2750
1000
60
140
40
SUPPLY CURRENT A
20
0
20
40
60
80
100
120
2500
2250
2000
1750
1500
1250
V
S
=
15V
V
S
= 3, 0
Figure 27. Supply Current vs. Temperature
OUTPUT SATURATION VOLTAGE mV
LOAD CURRENT mA
1000
100
0
0.01
10.0
0.10
1.0
10
V
OL
V
S
V
S
V
OH
V
S
=
15V
V
S
= 3, 0
Figure 28. Output Saturation Voltage
10
0%
100
90
5s
5V
AD824
REV. A
11
A current-limiting resistor should be used in series with the in-
put of the AD824 if there is a possibility of the input voltage ex-
ceeding the positive supply by more than 300 mV or if an input
voltage will be applied to the AD824 when
V
S
= 0. The ampli-
fier will be damaged if left in that condition for more than 10
seconds. A 1 k
resistor allows the amplifier to withstand up to
10 volts of continuous overvoltage and increases the input volt-
age noise by a negligible amount.
Input voltages less than V
S
are a completely different story.
The amplifier can safely withstand input voltages 20 volts below
the minus supply voltage as long as the total voltage from the
positive supply to the input terminal is less than 36 volts. In ad-
dition, the input stage typically maintains picoamp level input
currents across that input voltage range.
OUTPUT CHARACTERISTICS
The AD824's unique bipolar rail-to-rail output stage swings
within 15 mV of the positive and negative supply voltages. The
AD824's approximate output saturation resistance is 100
for
both sourcing and sinking. This can be used to estimate output
saturation voltage when driving heavier current loads. For
instance, the saturation voltage will be 0.5 volts from either
supply with a 5 mA current load.
For load resistances over 20 k
, the AD824's input error
voltage is virtually unchanged until the output voltage is driven
to 180 mV of either supply.
If the AD824's output is overdriven so as to saturate either of
the output devices, the amplifier will recover within 2
s of its
input returning to the amplifier's linear operating region.
Direct capacitive loads will interact with the amplifier's effective
output impedance to form an additional pole in the amplifier's
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. Worst case is when the amplifier is
used as a unity gain follower. Figures 5 and 7 show the AD824's
pulse response as a unity gain follower driving 220 pF. Configu-
rations with less loop gain, and as a result less loop bandwidth,
will be much less sensitive to capacitance load effects. Noise
gain is the inverse of the feedback attenuation factor provided
by the feedback network in use.
Figure 30 shows a method for extending capacitance load drive
capability for a unity gain follower. With these component val-
ues, the circuit will drive 5,000 pF with a 10% overshoot.
8
4
0.01
F
20pF
20k
100
V
OUT
+V
S
V
S
0.01
F
C
L
1/4
AD824
V
I N
Figure 30. Extending Unity Gain Follower Capacitive Load
Capability Beyond 350 pF
APPLICATION NOTES
INPUT CHARACTERISTICS
In the AD824, n-channel JFETs are used to provide a low
offset, low noise, high impedance input stage. Minimum input
common-mode voltage extends from 0.2 V below V
S
to 1 V less
than +V
S
. Driving the input voltage closer to the positive rail will
cause a loss of amplifier bandwidth.
The AD824 does not exhibit phase reversal for input voltages up
to and including +V
S
. Figure 29a shows the response of an
AD824 voltage follower to a 0 V to +5 V (+V
S
) square wave in-
put. The input and output are superimposed. The output tracks
the input up to +V
S
without phase reversal. The reduced band-
width above a 4 V input causes the rounding of the output wave
form. For input voltages greater than +V
S
, a resistor in series
with the AD824's noninverting input will prevent phase reversal
at the expense of greater input voltage noise. This is illustrated
in Figure 29b.
10
0%
100
90
1V
1V
10s
1V
10
0%
100
90
1V
2s
1V
GND
GND
+V
S
+5V
R
P
V
OUT
V
IN
Figure 29. (a) Response with R
P
= 0; V
IN
from 0 to +V
S
(b) V
IN
= 0 to + V
S
+ 200 m V
V
OUT
= 0 to + V
S
R
P
= 49.9 k
Since the input stage uses n-channel JFETs, input current dur-
ing normal operation is positive; the current flows out from the
input terminals. If the input voltage is driven more positive than
+V
S
0.4 V, the input current will reverse direction as internal
device junctions become forward biased. This is illustrated in
Figure 9.
(b)
(a)
AD824
12
REV. A
APPLICATIONS
Single Supply Voltage-to-Frequency Converter
The circuit shown in Figure 31 uses the AD824 to drive a low
power timer, which produces a stable pulse of width t
1
. The
positive going output pulse is integrated by R1-C1 and used as
one input to the AD824, which is connected as a differential
integrator. The other input (nonloading) is the unknown volt-
age, V
IN
. The AD824 output drives the timer trigger input, clos-
ing the overall feedback loop.
2
6
5
3
4
+10V
0.1
F
C5
R
SCALE
**
10k
R1
499k, 1%
R2
499k, 1%
0V TO 2.5V
FULL SCALE
C1
0.01
F, 2%
C2
0.01
F, 2%
U4
REF02
U1
4
3
U3B
2
1
U3A
C6
390pF
5%
C3
0.1
F
THR
TR
DIS
R
V+
OUT
CV
GND
4
8
6
2
7
1
3
5
(NPO)
C4
0.01
F
R3
*
116k
U2
CMOS 555
OUT2
OUT1
NOTES:
f
OUT
= /(VREF*t
1
), t
1
= 1.1*R3*C6
*
= 1% METAL FILM, <50ppm/
C TC
**
= 10%, 20T FILM, <100ppm/
C TC
t
1
= 33
s FOR f
OUT
= 20kHz @
= 2.0V
= 25kHz f
S
AS SHOWN.
V
REF
= 5V
CMOS
74HCO4
1/4
AD824B
V
I N
V
IN
V
IN
Figure 31. Single Supply Voltage-to-Frequency Converter
Typical AD824 bias currents of 2 pA allow megaohm-range
source impedances with negligible dc errors. Linearity errors on
the order of 0.01% full scale can be achieved with this circuit.
This performance is obtained with a 5 volt single supply, which
delivers less than 3 mA to the entire circuit.
Single Supply Programmable Gain Instrumentation Amplifier
The AD824 can be configured as a single supply instrumenta-
tion amplifier that is able to operate from single supplies down
to 3 V or dual supplies up to
15 V. AD824 FET inputs' 2 pA
bias currents minimize offset errors caused by high unbalanced
source impedances.
An array of precision thin-film resistors sets the in amp gain to
be either 10 or 100. These resistors are laser-trimmed to ratio
match to 0.01% and have a maximum differential TC of
5 ppm/
C.
Table I. AD824 In Amp Performance
Parameters
V
S
= 3 V, 0 V
V
S
= 5 V
CMRR
74 dB
80 dB
Common-Mode
Voltage Range
0.2 V to +2 V
5.2 V to +4 V
3 dB BW, G = 10
180 kHz
180 kHz
G = 100
18 kHz
18 kHz
t
SETTLING
2 V Step (V
S
= 0 V, 3 V)
2
s
5 V (V
S
=
5 V)
5
s
Noise @ f = 1 kHz, G = 10
270 nV/
Hz
270 nV/
Hz
G = 100
2.2
V/
Hz
2.2
V/
Hz
10
0%
100
90
1V
5s
Figure 32a. Pulse Response of In Amp to a 500 mV p-p
Input Signal; V
S
= +5 V, 0 V; Gain = 10
(G =10) V
OUT
= (V
IN1
V
IN2
) (1+ ) +V
REF
R6
R4 + R5
(G =100) V
OUT
= (V
IN1
V
IN2
) (1+ ) +V
REF
FOR R1 = R6, R2 = R5 AND R3 = R4
R5 + R6
R4
R1
R2
R3
R4
R5
R6
90k
9k
1k
1k
9k
90k
V
OUT
V
IN1
0.1
F
8
1/4
AD824
1/4
AD824
V
IN2
R
P
1k
1
2
3
6
5
11
7
OHMTEK
PART # 1043
V
REF
G =10
G =100
R
P
1k
G =100
G =10
+V
S
Figure 32b. A Single Supply Programmable
Instrumentation Amplifier
AD824
REV. A
13
3 Volt, Single Supply Stereo Headphone Driver
The AD824 exhibits good current drive and THD+N perfor-
mance, even at 3 V single supplies. At 1 kHz, total harmonic
distortion plus noise (THD+N) equals 62 dB (0.079%) for a
300 mV p-p output signal. This is comparable to other single
supply op amps that consume more power and cannot run on 3
V power supplies.
In Figure 33, each channel's input signal is coupled via a 1
F
Mylar capacitor. Resistor dividers set the dc voltage at the
noninverting inputs so that the output voltage is midway be-
tween the power supplies (+1.5 V). The gain is 1.5. Each half of
the AD824 can then be used to drive a headphone channel. A
5 Hz high-pass filter is realized by the 500
F capacitors and the
headphones, which can be modeled as 32 ohm load resistors to
ground. This ensures that all signals in the audio frequency
range (20 Hz20 kHz) are delivered to the headphones.
MYLAR
1F
1/4
AD824
L
R
HEADPHONES
32
IMPEDANCE
4.99k
MYLAR
1F
4.99k
1/4
AD824
10k
10k
47.5k
95.3k
47.5k
500F
500F
+3V
0.1F
0.1F
CHANNEL 1
CHANNEL 2
95.3k
Figure 33. 3 Volt Single Supply Stereo Headphone Driver
Low Dropout Bipolar Bridge Driver
The AD824 can be used for driving a 350 ohm Wheatstone
bridge. Figure 34 shows one half of the AD824 being used to
buffer the AD589--a 1.235 V low power reference. The output
350
350
350
350
V
REF
V
S
+V
S
AD620
R
G
R2
20
4.5V
10k
10k
10k
26.4k, 1%
R1
20
TO A/D CONVERTER
REFERENCE INPUT
AD589
49.9k
+1.235V
+5V
1F
GND
1%
1%
1%
1/4
AD824
1/4
AD824
V
S
+V
S
+V
S
V
S
0.1F
5V
1F
0.1F
7
6
5
4
3
2
Figure 34. Low Dropout Bipolar Bridge Driver
of +4.5 V can be used to drive an A/D converter front end. The
other half of the AD824 is configured as a unity-gain inverter
and generates the other bridge input of 4.5 V. Resistors R1 and
R2 provide a constant current for bridge excitation. The AD620
low power instrumentation amplifier is used to condition the
differential output voltage of the bridge. The gain of the AD620
is programmed using an external resistor R
G
and determined by:
G
=
49.4 k
R
G
+
1
A 3.3 Volt/5 Volt Precision Sample-and-Hold Amplifier
In battery-powered applications, low supply voltage operational
amplifiers are required for low power consumption. Also, low
supply voltage applications limit the signal range in precision
analog circuitry. Circuits like the sample-and-hold circuit
shown in Figure 35, illustrate techniques for designing precision
analog circuitry in low supply voltage applications. To maintain
high signal-to-noise ratios (SNRs) in a low supply voltage appli-
cation requires the use of rail-to-rail, input/output operational
amplifiers. This design highlights the ability of the AD824 to oper-
ate rail-to-rail from a single +3 V/+5 V supply, with the advantages
of high input impedance. The AD824, a quad JFET-input op
amp, is well suited to S/H circuits due to its low input bias cur-
rents (3 pA, typical) and high input impedances (3
10
13
,
typical). The AD824 also exhibits very low supply currents so
the total supply current in this circuit is less than 2.5 mA.
3.3/5V
3.3/5V
R1
50k
R2
50k
A1
3
2
4
1
11
0.1F
FALSE GROUND (FG)
A4
12
13
14
SAMPLE/
HOLD
A3
10
9
8
A2
5
6
7
15
14
16
10
9
11
AD824B
3.3/5V
ADG513
R5
2k
AD824C
+
V
OUT
CH
C
500pF
FG
4
5
8
6
7
2
3
1
AD824A
AD824D
R4
2k
FG
13
500pF
FG
Figure 35. 3.3 V/5.5 V Precision Sample and Hold
In many single supply applications, the use of a false ground
generator is required. In this circuit, R1 and R2 divide the sup-
ply voltage symmetrically, creating the false ground voltage at
one-half the supply. Amplifier A1 then buffers this voltage cre-
ating a low impedance output drive. The S/H circuit is config-
ured in an inverting topology centered around this false ground
level.
AD824
14
REV. A
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1
V/
s in this circuit. Higher values of C
H
will yield a lower
droop rate. For best performance, C
H
and C2 should be poly-
styrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Addi-
tionally, 1% metal film resistors were used throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output
is V
OUT
= V
IN
. The purpose of SW4, which operates in paral-
lel with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This cre-
ates a common-mode voltage across the inputs of A3 and is then
rejected by the CMR of A3; otherwise, the charge injection from
SW1 would create a differential voltage step error that would
appear at V
OUT
. The pedestal error for this circuit is less than 2
mV over the entire 0 V to 3.3 V/5 V signal range. Another
method of reducing pedestal error is to reduce the pulse ampli-
tude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the "ON" state and 0.8 V
for the "OFF" state. If possible, use an input control signal
whose amplitude ranges from 0.8 V to 2.4 V instead of a full
range 0 V to 3.3 V/5 V for minimum pedestal error.
Other circuit features include an acquisition time of less than
3
s to 1%; reducing C
H
and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normally-open and normally-closed pre-
cision CMOS switches on a dielectrically isolated process. SW2
is not required in this circuit; however, it was used in parallel
with SW3 to provide a lower R
ON
analog switch.
AD824
REV. A
15
FSY1
99
0
VP 1
FSY2
0
50
VN 1
DC1
25
99
DX
DC2
50
25
DX
*
* MODELS USED
*
.MODEL JX NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL
NPN NPN(BF=120 VAF=150 VAR=15 RB=2E3
+ RE=4 RC=550 IS=1E-16)
.MODEL PNP PNP(BF=120 VAF=150 VAR=15 RB=2E3 + RE=4
RC=750 IS=1E-16)
.MODEL DX D(IS=1E-15)
.MODEL DY D()
.MODEL DQ D(IS=1E-16)
.ENDS AD824
*
AD824 SPICE Macro-model 9/94, Rev. A *
ARG/ADI
*
* Copyright 1994 by Analog Devices, Inc.
*
* Refer to "README.DOC" file for License Statement.
Use of this model indicates your acceptance with
the terms and provisions in the License Statement. *
* Node assignments
*
noninverting input
*
| inverting input
*
| | positive supply
*
| | | negative supply
*
| | | | output
*
| | | | |
.SUBCKT AD824
1 2 99 50 25
*
* INPUT STAGE & POLE AT 3.1 MHz
*
R3
5
99
1.193E3
R4
6
99
1.193E3
CIN
1
2
4E-12
C2
5
6
19.229E-12
I1
4
50
108E-6
IOS
1
2
1E-12
EOS
7
1
POLY(1) (12,98) 100E-6 1
J1
4
2
5
JX
J2
4
7
6
JX
*
* GAIN STAGE & DOMINANT POLE
*
EREF
98
0
(30,0) 1
R5
9
98
2.205E6
C3
9
25
54E-12
G1
98
9
(6,5) 0.838E-3
V1
8
98
-1
V2
98
10
-1
D1
9
10
DX
D2
8
9
DX
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz *
R21
11
12
1E6
R22
12
98
100
C14
11
12
159E-12
E13
11
98
POLY(2) (2,98) (1,98) 0 0.5 0.5
*
* POLE AT 10 MHz
*
R23
18
98
1E6
C15
18
98
15.9E-15
G15
98
18
(9,98) 1E-6
*
* OUTPUT STAGE
*
ES
26
98
(18,98) 1
RS
26
22
500
IB1
98
21
2.404E-3
IB2
23
98
2.404E-3
D10
21
98
DY
D11
98
23
DY
C16
20
25
2E-12
C17
24
25
2E-12
DQ1
97
20
DQ
Q2
20
21
22 NPN
Q3
24
23
22 PNP
DQ2
24
51
DQ
Q5
25
20
97 PNP 20
Q6
25
24
51 NPN 20
VP
96
97
0
VN
51
52
0
EP
96
0
(99,0) 1
EN
52
0
(50,0) 1
R25
30
99
5E6
R26
30
50
5E6
AD824
16
REV. A
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Pin Plastic (N) Package
(N-14)
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.795 (20.19)
0.725 (18.42)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
PIN 1
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
7
8
14
1
14-Pin SOIC (R) Package
(R-14)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.2440 (6.20)
0.2284 (5.80)
1
14
8
7
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.3444 (8.75)
0.3367 (8.55)
0.0098 (0.25)
0.0040 (0.10)
16-Pin SOIC Package
(R-16)
16
9
8
1
0.4133 (10.50)
0.3977 (10.00)
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25) x 45
PRINTED IN U.S.A.
C1988a21/97
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