2 GHz Ultralow Distortion
Differential RF/IF Amplifier
AD8352
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
FUNCTIONAL BLOCK DIAGRAM
-3 dB bandwidth of 2.2 GHz (A
V
= 10 dB)
ENB
VCM
VOP
VON
GND
RGP
RDP
RDN
RGN
VIP
VIN
BIAS CELL
VCC
C
D
R
D
R
G
AD8352
+
0
57
28
-
00
1
Single resistor gain adjust 3 dB
A
V
21 dB
Single resistor and capacitor distortion adjust
Input resistance 3 k, independent of gain (A
V
)
Differential or single-ended input to differential output
Low noise input stage 2.7 nV/Hz RTI @ A
V
= 10 dB
Low broadband distortion
10 MHz: -86 dBc HD2, -82 dBc HD3
70 MHz: -84 dBc HD2, -82 dBc HD3
190 MHz: -81 dBc HD2, -87 dBc HD3
OIP3 of 41 dBm @ 150 MHz
Slew rate 8 V/ns
Fast settling and overdrive recovery of 2 ns
Figure 1.
Single-supply operation: 3 V to 5.0 V
Low power dissipation: 37 mA @ 5 V
60
100
20
220
FREQUENCY (MHz)
IP
3
(
d
B
m
)
HD
3
(
d
B
c
)
65
70
75
80
85
90
95
44
28
42
40
38
36
34
32
30
40
60
80
100
120
140
160
180
200
05
72
8-
00
2
Power down capability: 5 mA @ 5 V
Fabricated using the high speed XFCB3 SiGe process
APPLICATIONS
Differential ADC drivers
Single-ended to differential conversion
RF/IF gain blocks
SAW filter interfacing
Figure 2. IP3 and Third Harmonic Distortion vs. Frequency,
Measured Differentially
GENERAL DESCRIPTION
The AD8352 is a high performance differential amplifier
optimized for RF and IF applications. It achieves better than
80 dB SFDR performance at frequencies up to 200 MHz, and
65 dB beyond 500 MHz, making it an ideal driver for high
speed 12- to 16-bit analog-to-digital converters (ADCs).
The device is optimized for wide band, low distortion
performance at frequencies beyond 500 MHz. These attributes,
together with its wide gain adjust capability, make this device
the amplifier of choice for general-purpose IF and broadband
applications where low distortion, noise, and power are critical.
In particular, it is ideally suited for driving not only ADCs, but
also mixers, pin diode attenuators, SAW filters, and multielement
discrete devices. The device comes in a compact 3 mm 3 mm,
16-lead LFCSP package and operates over a temperature range of
-40C to +85C.
Unlike other wideband differential amplifiers, the AD8352 has
buffers that isolate the Gain Setting Resistor R
G
from the signal
inputs. As a result, the AD8352 maintains a constant 3 k input
resistance for gains of 3 dB to 24 dB, easing matching and input
drive requirements. The AD8352 has a nominal 100 differential
output resistance.
AD8352
Rev. 0| Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Noise Distortion Specifications .................................................. 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Applications..................................................................................... 11
Gain and Distortion Adjustment (Differential Input) .......... 11
Single-Ended Input Operation ................................................. 12
Narrow-Band, Third-Order Intermodulation Cancellation. 13
High Performance ADC Driving ............................................. 14
Layout and Transmission Line Effects..................................... 15
Evaluation Board ............................................................................ 16
Evaluation Board Loading Schemes ........................................ 17
Evaluation Board Schematics ................................................... 18
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
REVISION HISTORY
1/06--Revision 0: Initial Version
AD8352
Rev. 0| Page 3 of 20
SPECIFICATIONS
V
S
= 5 V, R
L
= 200 differential, R
G
= 118 (A
V
= 10 dB), f = 100 MHz, T = 25C; parameters specified differentially (in/out), unless
otherwise noted. C
D
and R
D
are selected for differential broadband operation (see Table 6 and Table 7).
Table 1.
Parameter Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
-3 dB Bandwidth
A
V
= 6 dB, V
OUT
1.0 V p-p
2500
MHz
A
V
= 10 dB, V
OUT
1.0 V p-p
2200
MHz
A
V
= 14 dB, V
OUT
1.0 V p-p
1800
MHz
Bandwidth for 0.1 dB Flatness
3 dB A
V
20 dB, V
OUT
1.0 V p-p
190
MHz
Bandwidth for 0.2 dB Flatness
3 dB A
V
20 dB, V
OUT
1.0 V p-p
300
MHz
Gain Accuracy
Using 1% resistor for R
G
, 0 dB A
V
20 dB
1
dB
Gain Supply Sensitivity
V
S
5%
.06
dB/V
Gain Temperature Sensitivity
-40C to +85C
4
mdB/C
Slew Rate
R
L
= 1 k, V
OUT
= 2 V step
9
V/ns
R
L
= 200 , V
OUT
= 2 V step
8
V/ns
Settling Time
2 V step to 1%
<2
ns
Overdrive Recovery Time
V
IN
= 4 V to 0 V step, V
OUT
10 mV
<3
ns
Reverse Isolation (S12)
-80
dB
INPUT/OUTPUT CHARACTERISTICS
Common-Mode Nominal
VCC/2
V
Voltage Adjustment Range
1.2 to 3.8
V
Maximum Output Voltage Swing
1 dB compressed
6
V p-p
Output Common-Mode Offset
Referenced to VCC/2
-100
+20
mV
Output Common-Mode Drift
-40C to +85C
.25
mV/C
Output Differential Offset Voltage
-20
+20
mV
CMRR
57
dB
Output Differential Offset Drift
-40C to +85C
.15
mV/C
Input Bias Current
5
A
Input Resistance
3
k
Input Capacitance (Single-Ended)
0.9
pF
Output Resistance
100
Output Capacitance
3
pF
POWER INTERFACE
Supply Voltage
3
5
5.5
V
ENB Threshold
1.5
V
ENB Input Bias Current
ENB at 3 V
75
nA
ENB at 0.6 V
-125
A
Quiescent Current
ENB at 3 V
35
37
39
mA
ENB at 0.6 V
5.3
mA
AD8352
Rev. 0| Page 4 of 20
NOISE DISTORTION SPECIFICATIONS
V
S
= 5 V, R
L
=200 differential, R
G
=118 (A
V
= 10 dB), V
OUT
= 2 V p-p composite, T = 25C; parameters specified differentially, unless
otherwise noted. C
D
and R
D
are selected for differential broadband operation (see Table 6 and Table 7).
Table 2.
Parameter Conditions
Min
Typ
Max
Unit
10 MHz
Second/Third Harmonic Distortion
1
R
L
= 1 k, V
OUT
= 2 V p-p
-88/-95
dBc
R
L
= 200 , V
OUT
= 2 V p-p
-86/-82
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 9.5 MHz, f
2
= 10.5 MHz
+38
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 9.5 MHz, f
2
= 10.5 MHz, V
OUT
= 2 V p-p composite
-86
dBc
R
L
= 200 , f
1
= 9.5 MHz, f
2
= 10.5 MHz, V
OUT
= 2 V p-p composite
-81
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+15.7
dBm
70 MHz
Second/Third HarmonicDistortion
1
R
L
= 1 k, R
G
= 178 , V
OUT
= 2 V p-p
-83/-84
dBc
R
L
= 200 , R
G
= 115 , V
OUT
= 2 V p-p
-84/-82
dBc
Output Third-Order Intercept
R
L
= 200 f
1
= 69.5 MHz, f
2
= 70.5 MHz
+40
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 69.5 MHz, f
2
= 70.5 MHz, V
OUT
= 2 V p-p composite
-91
dBc
R
L
= 200 , f
1
= 69.5 MHz, f
2
= 70.5 MHz, V
OUT
= 2 V p-p composite
-83
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+15.7
dBm
100 MHz
Second/Third Harmonic Distortion
R
L
= 1 k, V
OUT
= 2 V p-p
-83/-83
dBc
R
L
= 200 , V
OUT
= 2 V p-p
-84/-82
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 99.5 MHz, f
2
= 100.5 MHz
+40
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 99.5 MHz, f
2
= 100.5 MHz, V
OUT
= 2 V p-p composite
-91
dBc
R
L
= 200 , f
1
= 99.5 MHz, f
2
= 100.5 MHz, V
OUT
= 2 V p-p composite
-84
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+15.6
dBm
140 MHz
Second/Third Harmonic Distortion
2
R
L
= 1 k, V
OUT
= 2 V p-p
-83/-82
dBc
R
L
= 200 , V
OUT
= 2 V p-p
-82/-84
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 139.5 MHz, f
2
= 140.5 MHz
+41
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 139.5 MHz, f
2
= 140.5 MHz, V
OUT
= 2 V p-p composite
-89
dBc
R
L
= 200 , f
1
= 139.5 MHz, f
2
= 140.5 MHz, V
OUT
= 2 V p-p
composite
-85 dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+15.5
dBm
1
When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer such as Mini-Circuits ADT1-1WT to obtain the low
frequency balance required for differential HD2 cancellation.
2
C
D
and R
D
can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, C
D
and R
D
components are not required.
AD8352
Rev. 0| Page 5 of 20
V
S
= 5 V, R
L
= 200 differential, R
G
= 118 (A
V
= 10 dB), V
OUT
= 2 V p-p composite, T = 25C; parameters specified differentially, unless
otherwise noted. C
D
and R
D
are selected for differential broadband operation (see Table 6 and Table 7). See the Applications section for
single-ended to differential performance characteristics.
Table 3.
Parameter Conditions
Min
Typ
Max
Unit
190 MHz
Second/Third Harmonic Distortion
1
R
L
= 1 k, V
OUT
= 2 V p-p
-82/-85
dBc
R
L
= 200 , V
OUT
= 2 V p-p
-81/-87
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 180.5 MHz, f
2
= 190.5 MHz
+39
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 180.5 MHz, f
2
= 190.5 MHz, V
OUT
= 2 V p-p composite
-83
dBc
R
L
= 200 , f
1
= 180.5 MHz, f
2
= 190.5 MHz, V
OUT
= 2 V p-p composite
-81
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+15.4
dBm
240 MHz
Second/Third Harmonic Distortion
1
R
L
= 1 k, V
OUT
= 2 V p-p
-82/-76
dBc
R
L
= 200 , V
OUT
= 2 V p-p
-80/-73
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 239.5 MHz, f
2
= 240.5 MHz
+36
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 239.5 MHz, f
2
= 240.5 MHz, V
OUT
= 2 V p-p composite
-85
dBc
R
L
= 200 , f
1
= 239.5 MHz, f
2
= 240.5 MHz, V
OUT
= 2 V p-p composite
-77
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+15.3
dBm
380 MHz
Second/Third Harmonic Distortion
R
L
= 1 k, V
OUT
= 2 V p-p
-72/-68
dBc
R
L
= 200 , V
OUT
= 2 V p-p
-74/-69
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 379.5 MHz, f
2
= 380.5 MHz
+33
dBm
Third-Order IMD
R
L
= 1 k, f
1
= 379.5 MHz, f
2
= 380.5 MHz, V
OUT
= 2 V p-p composite
-74
dBc
R
L
= 200 , f
1
= 379.5 MHz, f
2
= 380.5 MHz, V
OUT
= 2 V p-p composite
-70
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+14.6
dBm
500 MHz
Second/Third Harmonic Distortion
2
R
L
= 200 , V
OUT
= 2 V p-p
-71/-64
dBc
Output Third-Order Intercept
R
L
= 200 , f
1
= 499.5 MHz, f
2
= 500.5 MHz
+28
dBm
Third-Order IMD
R
L
= 200 , f
1
= 499.5 MHz, f
2
= 500.5 MHz, V
OUT
= 2 V p-p composite
-61
dBc
Noise Spectral Density (RTI)
+2.7
nV/Hz
1 dB Compression Point (RTO)
+13.9
dBm
1
When using the evaluation board at frequencies below 50 MHz, replace the Output Balun T1 with a transformer such as Mini-Circuits ADT1-1WT to obtain the low
frequency balance required for differential HD2 cancellation.
2
C
D
and R
D
can be optimized for broadband operation below 180 MHz. For operation above 300 MHz, C
D
and R
D
components are not required.
AD8352
Rev. 0| Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage VCC
5.5 V
VIP, VIN
5 V
Internal Power Dissipation
210 mW
JA
91.4C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Maximum Junction Temperature
104C
Operating Temperature Range
-40C to +85C
Storage Temperature Range
-65C to +150C
Lead Temperature (Soldering 60 sec)
300C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8352
Rev. 0| Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
RDP
2
RGP
3
RGN
4
RDN
11 VOP
12 GND
10 VON
9 GND
5
V
I
N
6
G
N
D
7
G
N
D
8
V
C
C
1
5
E
N
B
1
6
V
I
P
1
4
V
C
M
1
3
V
C
C
TOP VIEW
(Not to Scale)
AD8352
05
72
8-
00
3
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RDP
Positive Distortion Adjust.
2
RGP
Positive Gain Adjust.
3
RGN
Negative Gain Adjust.
4
RDN
Negative Distortion Adjust.
5
VIN
Balanced Differential Input. Biased to VCM, typically ac-coupled.
6, 7, 9, 12
GND
Ground. Connect to low impedance GND.
8, 13
VCC
Positive Supply.
10
VON
Balanced Differential Output. Biased to VCM, typically ac-coupled.
11
VOP
Balanced Differential Output. Biased to VCM, typically ac-coupled.
14 VCM
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and output.
Typically decoupled to ground with a 0.1 F capacitor. With no reference applied, input and output common
mode floats to midsupply = VCC/2.
15
ENB
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device.
16
VIP
Balanced Differential Input. Biased to VCM, typically ac-coupled.
AD8352
Rev. 0| Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (MHz)
GA
IN
(
d
B
)
10
10k
25
5
100
1k
20
15
10
5
0
R
G
= 43
R
G
= 100
R
G
= 520
05
72
8-
03
6
FREQUENCY (MHz)
GA
IN
(
d
B
)
10
10k
30
5
100
1k
25
20
15
10
5
0
R
G
= 20
R
G
= 100
R
G
= 182
R
G
= 383
R
G
= 715
05
72
8-
03
9
Figure 4. Gain vs. Frequency for a 200 Differential Load with Baluns,
A
V
= 18 dB, 12 dB, and 6 dB
Figure 7. Gain vs. Frequency for a 1 k Differential Load Without Baluns,
R
D
/C
D
Open, A
V
= 25 dB, 14 dB, 10 dB, 6 dB, and 3 dB
FREQUENCY (MHz)
GA
IN
(
d
B
)
10
10k
25
5
100
1k
20
15
10
5
0
R
G
= 62
R
G
= 190
R
G
= 3k
05
72
8-
03
7
FREQUENCY (MHz)
GA
IN
(
d
B
)
GA
IN
(
d
B
)
10
10k
13.0
8.0
100
1k
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
11.0
6.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
40C
+85C
+25C
40C
+85C
+25C
05
72
8-
04
0
R
L
= 1k
R
G
= 182
T
C
= 0.002dB/C
R
L
= 200
R
G
= 118
T
C
= 0.004dBc
Figure 5. Gain vs. Frequency for a 1 k Differential Load with Baluns,
A
V
= 18 dB, 12 dB, and 6 dB
Figure 8. Gain vs. Frequency over Temperature (-40C, +25C, +85C)
Without Baluns, A
V
= 10 dB, R
L
= 200 and 1 k
50
10
0
500
FREQUENCY (MHz)
IP
3
(
d
B
m
)
45
40
35
30
25
20
15
50
100
150
200
250
300
350
400
450
A
V
= 6dB
A
V
= 10dB
A
V
= 15dB
05
72
8-
04
8
FREQUENCY (MHz)
GA
IN
(
d
B
)
10
10k
25
5
100
1k
20
15
10
5
0
R
G
= 19
R
G
= 64
R
G
= 118
R
G
= 232
R
G
= 392
05
72
8-
03
8
Figure 9. OIP3 vs. Frequency in dB, 2 V p-p Composite, R
L
= 200
A
V
= 15 dB, 10 dB, and 6 dB
Figure 6. Gain vs. Frequency for a 200 Differential Load Without Baluns,
R
D
/C
D
Open, A
V
= 22 dB, 14 dB, 10 dB, 6 dB, and 3 dB
AD8352
Rev. 0| Page 9 of 20
60
90
FREQUENCY (MHz)
H
ARM
O
N
I
C
DI
S
T
O
R
T
I
O
N
(
d
Bc)
65
70
75
80
85
220
260
300
340
380
420
460
500
> 300MHz NO C
D
OR R
D
USED
HD3
2V p-p
HD2
2V p-p
HD3
1V p-p
05
728
-
00
9
FREQUENCY (MHz)
GR
OU
P
D
E
L
A
Y
(
n
s
)
0
1000
0.6
0.5
0.4
0.3
0.2
0.1
0
0
20
40
60
80
100
120
100
200
300
400
500
600
700
800
900
P
H
AS
E
(
D
eg
r
ees)
05
72
8-
04
2
Figure 10. Third-Order Harmonic Distortion HD3 vs. Frequency,
A
V
= 10 dB, R
L
= 200
Figure 13. Phase and Group Delay vs. Frequency, A
V
= 10 dB, R
L
= 200
60
110
0
500
FREQUENCY (MHz)
H
ARM
O
N
I
C
DI
S
T
O
R
T
I
O
N
(
d
Bc)
65
70
75
80
85
90
95
100
105
50
100
150
200
250
300
350
400
450
HD3
HD2
05
72
8-
00
5
3500
0
10
1000
FREQUENCY (MHz)
I
N
PU
T
I
M
PED
A
N
C
E (
)
P
HAS
E
(
D
e
g
r
e
es)
100
3000
2500
2000
1500
1000
500
7
0
6
5
4
3
2
1
05
72
8-
04
4
Figure 11. Harmonic Distortion vs. Frequency for 2 V p-p into R
L
= 200 ,
A
V
= 10 dB, R
G
= 115 , R
D
= 4.3 k, C
D
= 0.2 pF
Figure 14. S11 Magnitude and Phase
50
110
0
400
FREQUENCY (MHz)
H
ARM
O
N
I
C
DI
S
T
O
R
T
I
O
N
(
d
Bc)
60
70
80
90
100
50
100
150
200
250
300
350
HD2
HD3
05
72
8-
00
7
120
100
10
1000
FREQUENCY (MHz)
O
UT
P
UT
I
M
P
E
D
ANCE
(
)
P
HAS
E
(
D
e
g
r
ees)
100
118
116
114
112
110
108
106
104
102
0
100
10
20
30
40
50
60
70
80
90
05
72
8-
04
5
Figure 12. Harmonic Distortion vs. Frequency for 2 V p-p into R
L
=1 k,
A
V
= 10 dB, 5 V Supply, R
G
= 180 , R
D
= 6.8 k, C
D
= 0.1 pF
Figure 15. S22 Magnitude and Phase
AD8352
Rev. 0| Page 10 of 20
1.5
1.5
TIME (nsec)
VO
L
T
A
G
E
(
V)
0
3.0
1.0
0.5
0
0.5
1.0
0.5
1.0
1.5
2.0
2.5
T
RISE
(10/90) = 215psec
T
FALL
(10/90) = 210psec
FREQUENCY (MHz)
S
P
E
C
T
RAL
NO
I
S
E
DE
NS
I
T
Y
RT
I
(
n
V
/
H
z
)
0
500
5.0
1.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
17.0
13.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
50
100
150
200
250
300
350
400
450
NO
I
S
E
F
I
G
UR
E
(
d
B)
05
72
8-
04
6
TIME (nsec)
SET
T
L
I
N
G
(%
)
Figure 16 Large Signal Output Transient Response, R
L
= 200 , A
V
= 10 dB
5
5
0
4.0
05
72
8-
04
1
FREQUENCY (MHz)
CM
R
R (
d
B)
Figure 18. Noise Figure and Noise Spectral Density RTI vs. Frequency,
A
V
= 10 dB, R
L
= 200 and 1 k
4
3
2
1
0
1
2
3
4
0.5
1.0
1.5
2.0
2.5
3.0
3.5
10
1000
80
10
70
60
50
40
30
20
R
L
= 200
R
L
= 1k
100
05
72
8-
04
3
05
72
8-
04
7
Figure 19. CMRR vs. Frequency, R
L
= 200 and 1 k,
Differential Source Resistance
Figure 17. 1% Settling Time for a 2 V p-p Step Response,
A
V
= 10 dB, R
L
= 200
AD8352
Rev. 0| Page 11 of 20
APPLICATIONS
Table 7. Broadband Selection of R
G
, C
D
, and R
D
: 1 k Load
GAIN AND DISTORTION ADJUSTMENT
(DIFFERENTIAL INPUT)
A
V
(dB)
R
G
()
C
D
(pF)
R
D
(k)
3
750
0 (DNP)
6.8
Table 6 and Table 7 show the required value of R
G
for the gains
specified at 200 and 1 k loads. Figure 20 and Figure 22 plot
R
G
vs. gain up to 18 dB for both load conditions. For other
output loads (R
L
), use Equation 1 to compute gain vs. R
G
.
(
)(
)
L
L
G
G
ial
VDifferent
R
R
R
R
A
+
+
+
+
=
430
53
5
500
(1)
where:
R
L
= single-ended load.
R
G
= gain setting resistor.
The third-order harmonic distortion can be reduced by using
external components R
D
and C
D
. Table 6 and Table 7 show the
required values for R
D
and C
D
vs. the specified gains to achieve
(single tone) third-order distortion reduction at 180 MHz.
Figure 21 and Figure 23 show C
D
vs. any gain (up to 18 dB) for
200 and 1 k loads, respectively. When these values are
selected, they result in minimum single tone, third-order
distortion at 180 MHz. This frequency point provides the best
overall broadband distortion for the specified frequencies below
and above this value. For applications above approximately
300 MHz, C
D
and R
D
are not required. See the Specifications
section and third-order harmonic plots in the Typical
Performance Characteristics section for more details.
C
D
can be further optimized for narrow-band tuning
requirements below 180 MHz that result in relatively lower
third-order (in-band) intermodulation distortion terms. See the
Narrow-Band, Third-Order Intermodulation Cancellation
section for more information. Though not shown, single tone,
third-order optimization can also be improved for narrow-band
frequency applications below 180 MHz with the proper
selection of C
D
, and 3 dB to 6 dB of relative third-order
improvement can be realized at frequencies below
approximately 140 MHz.
Using the information listed in Table 6 and Table 7, an
extrapolated value for R
D
can be determined for loads between
200 and 1 k. For loads above 1 k, use the 1 k R
D
values
listed in Table 7.
Table 6. Broadband Selection of R
G
, C
D
, and R
D
: 200 Load
A
V
(dB)
R
G
()
C
D
(pF)
R
D
(k)
3 390
0
(DNP)
6.8
6 220
0
(DNP)
4.3
9
140
0.1
4.3
10 115
0.2 4.3
12 86
0.3 4.3
15
56
0.6
4.3
18 35
1 4.3
6
360
0 (DNP)
6.8
9
210
0 (DNP)
6.8
10
180
0.05
6.8
12
130
0.1
6.8
15
82
0.3
6.8
18 54 0.5 6.8
20
0
0
400
R
G
()
GA
IN
(
d
B
)
18
16
14
12
10
8
6
4
2
100
200
300
50
150
250
350
05
72
8-
0
26
Figure 20. R
G
vs. Gain, R
L
= 200
20
0
0
C
D
(pF)
GA
IN
(
d
B
)
18
16
14
12
10
8
6
4
2
0.2
0.4
0.6
0.8
1.0
0.1
0.3
0.5
0.7
0.9
05
72
8-
0
27
Figure 21. C
D
vs. Gain, R
L
= 200
AD8352
Rev. 0| Page 12 of 20
20
0
0
800
R
G
()
GA
IN
(
d
B
)
18
16
14
12
10
8
6
4
2
100
200
300
400
500
600
700
05
72
8-
0
28
Figure 22. R
G
vs. Gain, R
L
= 1 k
20
0
0
0.5
C
D
(pF)
GA
IN
(
d
B
)
18
16
14
12
10
8
6
4
2
0.1
0.2
0.3
0.4
05
72
8-
0
29
Figure 23. C
D
vs. Gain, R
L
= 1 k
SINGLE-ENDED INPUT OPERATION
The AD8352 can be configured as a single-ended to differential
amplifier as shown in Figure 24. To balance the outputs when
driving only the VIP input, an external resistor (R
N
) of 200 is
added between VIP and RGN. See Equation 2 to determine the
single-ended input gain (A
VSingle-ended
) for a given R
G
or R
L
.
(
)(
)
30
430
53
5
500
+
+
+
+
+
+
=
-
L
L
L
L
G
G
ended
VSingle
R
R
R
R
R
R
A
(2)
where:
R
L
= single-ended load.
R
G
= gain setting resistor.
Figure 25 plots gain vs. R
G
for 200 and 1 k loads. Table 8
and Table 9 show the values of C
D
and R
D
required (for 180 MHz
broadband third-order, single tone optimization) for 200 and
1 k loads, respectively. This single-ended configuration
provides -3 dB bandwidths similar to input differential drive.
Figure 26 through Figure 28 show distortion levels at a gain of
12 dB for both 200 and 1 k loads. Gains from 3 dB to 18 dB,
using optimized C
D
and R
D
values, obtain similar distortion
levels.
R
D
R
G
25
65
50
0.1F
0.1F
0.1F
0.1F
RGP
RGN
AD8352
AC
C
D
VIP
R
N
200
05
72
8-
0
24
Figure 24. Single-Ended Schematic
40
0
1
10k
R
G
()
GA
IN
(
d
B
)
10
100
1k
35
30
25
20
15
10
5
GAIN, R
L
= 1k
GAIN, R
L
= 200
05
72
8-
0
20
Figure 25. Gain vs. R
G
60
110
FREQUENCY (MHz)
(d
B
c
)
10
70
140
190
240
70
80
90
100
2NDS, 2V p-p OUT
2NDS, 1V p-p OUT
05
72
8-
02
1
Figure 26. Single-Ended, Second-Order Harmonic Distortion,
200 Load
This broadband optimization was also performed at 180 MHz.
As with differential input drive, the resulting distortion levels
at lower frequencies are based on the C
D
and R
D
specified in
Table 8 and Table 9. As with differential input drive, relative
third-order reduction improvement at frequencies below
140 MHz are realized with proper selection of C
D
and R
D
.
AD8352
Rev. 0 | Page 13 of 20
Table 9. Distortion Cancellation Selection Components
(R
D
and C
D
) for Required Gain, 1 k Load
60
110
FREQUENCY (MHz)
(d
B
c
)
10
70
140
190
240
70
80
90
100
3RDS, 2V p-p OUT
3RDS, 1V p-p OUT
0
572
8-
0
22
A
V
(dB)
R
G
()
CD (pF)
R
D
(k)
6
3 k
0 (DNP)
4.3
9 470
0
(DNP)
4.3
12 210
0.2 4.3
15 120
0.3 4.3
18 68
0.5 4.3
NARROW-BAND, THIRD-ORDER
INTERMODULATION CANCELLATION
Broadband, single tone, third-order harmonic optimization
does not necessarily result in optimum (minimum) two tone,
third-order intermodulation levels. The specified values for C
D
and R
D
in
Figure 27. Single-Ended, Third-Order Harmonic Distortion, 200 Load
Table 6 and Table 7 were determined for minimizing
broadband single tone, third-order levels.
60
110
FREQUENCY (MHz)
(d
B
c
)
10
70
140
190
240
70
80
90
100
2NDS, 1V p-p OUT
2NDS, 2V p-p OUT
0
572
8-
0
23
Due to phase-related distortion coefficients, optimizing single
tone, third-order distortion does not result in optimum in band
(2f
1
- f
2
and 2f
2
- f
1
), third-order distortion levels. By proper
selection of C
D
(using a fixed 4.3 k R
D
), IP3s of better than
45 dBm are achieved. This results in degraded out-of-band,
third-order frequencies (f
2
+ 2f
1
, f
1
+ 2f
2
, 3f
1
and 3f
2
). Thus,
careful frequency planning is required to determine the
tradeoffs.
Figure 30 shows narrow band (2 MHz spacing) OIP3 levels
optimized at 32 MHz, 70 MHz, 100 MHz, and 180 MHz using
the C
D
values specified in Figure 31. These four data points (the
C
D
value and associated IP3 levels) are extrapolated to provide
close estimates of IP3 levels for any specific frequency between
30 MHz and 180 MHz. For frequencies below approximately
140 MHz, narrow-band tuning of IP3 results in relatively higher
IP3s (vs. the broadband results shown in
Figure 28. Single-Ended, Second-Order Harmonic Distortion, 1 k Load
60
110
FREQUENCY (MHz)
(d
B
c
)
10
70
140
190
240
70
80
90
100
3RDS, 1V p-p OUT
3RDS, 2V p-p OUT
0
572
8-
0
25
Table 2 specifications).
Though not shown, frequencies below 30 MHz also result in
improved IP3s when using proper values for C
D
.
48
38
0
200
FREQUENCY (MHz)
OIP
3
(
d
B
m
)
47
46
45
44
43
42
41
40
39
50
100
150
6db
10db
15db
18dB
A
V
=
05
72
8-
03
0
R
L
= 200
R
D
= 4.3k
C
D
= 0.3pF
Figure 29. Single-Ended, Third-Order Harmonic Distortion, 1 k Load
Table 8. Distortion Cancellation Selection Components
(R
D
and C
D
) for Required Gain, 200 Load
A
V
(dB)
R
G
()
C
D
(pF)
R
D
(k)
3
4.3 k
0 (DNP)
4.3
6 540
0
(DNP)
4.3
Figure 30.
Third-Order Intermodulation Distortion vs. Frequency for
Various Gain Settings
9 220
0.1
4.3
12 120
0.3 4.3
15 68
0.6 4.3
18 43
0.9 4.3
AD8352
Rev. 0| Page 14 of 20
6.0
0
30
190
FREQUENCY (MHz)
C
D
(pF
)
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
50
70
90
110
130
150
170
R
L
= 200
R
D
= 4.3k
6db
10db
15db
18dB
A
V
=
05
72
8-
03
1
These AD8352 simplified circuits provide the gain, isolation,
and distortion performance necessary for efficiently driving
high linearity converters such as the AD9445. This device also
provides balanced outputs whether driven differentially or
single-ended, thereby maintaining excellent second-order
distortion levels. Though at frequencies above approximately
100 MHz, due to phase related errors, single-ended, second-
order distortion is relatively higher. The output of the amplifier
is ac-coupled to allow for an optimum common-mode setting at
the ADC input. Input ac-coupling can be required if the source
also requires a common-mode voltage that is outside the
optimum range of the AD8352. A VCM common-mode pin is
provided on the AD8352 that equally shifts both input and
output common-mode levels. Increasing the gain of the
AD8352 increases the system noise and, thus, decreases the
SNR (3.5 dB at 100 MHz input for Av=10 dB) of the
AD9445
when no filtering is used. Note that amplifier gains from 3 dB to
18 dB, with proper selection of C
D
and R
D
, do not appreciably
affect distortion levels. These circuits, when configured
properly, can result in SFDR performance of better than 87 dBc
at 70 MHz and 82 dBc at 180 MHz input. Single-ended drive,
with appropriate C
D
and R
D
, give similar results for SFDR and
third-order intermodulation levels shown in these figures.
Figure 31. Narrow-Band C
D
vs. Frequency for Various Gain Settings
HIGH PERFORMANCE ADC DRIVING
The AD8352 provides the gain, isolation, and balanced low
distortion output levels for efficiently driving wideband ADCs
such as the
AD9445
.
Figure 32 and Figure 33 (single and differential input drive)
illustrate the typical front-end circuit interface for the AD8352
differentially driving the
AD9445
14-bit ADC at 105 MSPS. The
AD8352, when used in the single-ended configuration shows
little or no degradation in overall third-order harmonic
performance (vs. differential drive). See the
Placing antialiasing filters between the ADC and the amplifier
is a common approach for improving overall noise and broadband
distortion performance for both band-pass and low-pass appli-
cations. For high frequency filtering, matching to the filter is
required. The AD8352 maintains a 100 output impedance
well beyond most applications and is well-suited to drive most
filter configurations with little or no degradation in distortion.
Single-Ended Input
Operation section. The 100 MHz FFT plots shown in Figure 34
and Figure 35 display the results for the differential
configuration. Though not shown, the single-ended third-order
levels are similar.
AD9445
AD8352
IF/RF INPUT
ADT1-1WT
50
0
24
24
0
C
D
R
D
R
G
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
16
1
2
3
4
5
10
11
8, 11
14
05728-
012
V
CC
Figure 32
The 50 resistor shown in
provides a 50
differential input impedance to the source for matching
considerations. When the driver is less than one eighth of the
wavelength from the AD8352, impedance matching is not
required thereby negating the need for this termination resistor.
The output 24 resistors provide isolation from the analog-to-
digital input. Refer to the Layout and Transmission Line Effects
section for more information. The circuit in Figure 33
represents a single-ended input to differential output configura-
tion for driving the
AD9445.
In this case, the input 50 resistor
with R
N
(typically 200 ) provide the input impedance match
for a 50 system. Again, if input reflections are minimal, this
impedance match is not required. A fixed 200 resistor (R
N
) is
required to balance the output voltages that are required for
second-order distortion cancellation. R
G
is the gain-setting
resistor for the AD8352 with the R
D
and C
D
components
providing distortion cancellation. The
AD9445
presents
approximately 2 k in parallel with 5 pF/differential load to the
AD8352 and requires a 2.0 V p-p differential signal (V
REF
= 1 V)
between VIN+ and VIN- for a full-scale output operation.
Figure 32. Differential Input to the AD8352 Driving the AD9445
R
D
R
G
25
50
50
AD8352
C
D
33
33
0.1F
0.1F
0.1F
0.1F
AC
VIP
VIN
VOP
VON
R
N
200
AD9445
VIN+
VIN
05728-
033
Figure 33. Single-Ended Input to the AD8352 Driving the AD9445
AD8352
Rev. 0 | Page 15 of 20
0
150
0
52.50
FREQUENCY (MHz)
(dB
F
S)
10
20
30
40
50
60
70
80
90
100
110
120
130
140
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25
SNR = 67.26dBc
SFDR = 83.18dBc
NOISE FLOOR = 110.5dB
FUND = 1.074dBFS
SECOND = 83.14dBc
THIRD = 85.39dBc
05
72
8-
03
4
LAYOUT AND TRANSMISSION LINE EFFECTS
High Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies resulting
in excessive gain peaking or possible oscillation. If RF transmis-
sion lines connecting the input or output are used, they should
be designed such that stray capacitance at the I/O pins is
minimized. In many board designs, the signal trace widths
should be minimal where the driver/receiver is less than one-
eighth of the wavelength from the AD8352. This non-transmission
line configuration requires that underlying and adjacent ground
and low impedance planes be far removed from the signal lines.
In a similar fashion, stray capacitance should be minimized
near the R
G
, C
D
, and R
D
components and associated traces. This
also requires not placing low impedance planes near these
components. Refer to the evaluation board layout (
Figure 34. Single Tone Distortion AD8352 Driving
AD9445
, Encode Clock @
105 MHz with Fc @ 100 MHz (A
V
= 10 dB), See Figure 32
Figure 37
and
FREQUENCY (MHz)
(dB
F
S)
0
150
0
52.50
10
20
30
40
50
60
70
80
90
100
110
120
130
140
5.25 10.50 15.75 21.00 26.25 31.50 36.75 42.00 47.25
SNR = 61.98dBc
NOISE FLOOR = 111.2dB
FUND1 = 7.072
FUND2 = 7.043
IMD (2F2-F1) = 89dBc
IMD (2F1-F2) = 88dBc
05
72
8-
03
5
Figure 38) for more information. Excessive stray capacitance
at these nodes results in unwanted high frequency distortion.
The 0.1 F supply decoupling capacitors need to be close to the
amplifier. This includes Signal Capacitor C2 through Signal
Capacitor C5.
Parasitic suppressing resistors (R5, R6, R7, and R11) can be
used at the device I/O pins. Use 25 series resistors (Size 0402)
to adequately de-Q the input and output system from most
parasitics without a significant decrease in gain. In general,
if proper board layout techniques are used, the suppression
resistors may not be required. Output Parasitic Suppression
Resistor R7 and Output Parasitic Suppression Resistor R11 may
be required for driving some switch cap ADCs. These
suppressors, with Input C of the converter (and possibly added
External Shunt C), help provide charge kickback isolation and
improve overall distortion at high encode rates.
Figure 35. Two Tone Distortion AD8352 Driving
AD9445,
Encode Clock @ 105 MHz with Fc @ 100 MHz (A
V
= 10 dB),
Analog In = 98 MHz and 101 MHz, See Figure 32
AD8352
Rev. 0| Page 16 of 20
EVALUATION BOARD
An evaluation board is available for experimentation of various parameters such as gain, common-mode level, and distortion. The output
network can be configured for different loads via minor output component changes. The schematic and evaluation board artwork are
presented in Figure 36, Figure 37, and Figure 38. All discrete capacitors and resistors are Size 0402, except for C1 (3528-B).
Table 10. Evaluation Board Circuit Components and Functions
Component Name
Function
Additional
Information
Pin 8 and Pin 13
VCC
Supply VCC = +5 V.
Pin 6, Pin 7,
Pin 9, Pin 12
GND
Connect to Low Impedance GND.
Pin 14, C9
VCM, Capacitor
Common-Mode Offset Pin. Allows for monitoring or adjustment of the
output common-mode voltage. C9 is a bypass capacitor.
C9 = 0.1 F
R
D
/C
D
Distortion
Tuning
Components
Distortion Adjustment Components. Allows for third-order distortion
adjustment HD3.
Typically, both are open
above 300 MHz
C
D
= 0.2 pF, R
D
= 4.32 k
C
D
is Panasonic High Q
(microwave) Multilayer
Chip 402 capacitor
Pin 15, C8
ENB, Capacitor
Enable. Apply positive voltage (1.3 V < ENB < VCC) to activate device. Pull
down to disable. Can be bypassed and float high (1.8 V) for on state. C8 is
a bypass capacitor.
Floats to 1.8 V to
maintain device in
power-up mode
C8 = 0.1 F
R1, R2, R3, R4,
R5, R6, T2, C2,
C3
Resistors,
Transformer,
Capacitors
Input Interface. R1 and R4 ground one side of the differential drive
interface for single-ended applications. T2 is a 1-to-1 impedance ratio
balun to transform a single-ended input into a balanced differential
signal. R2 and R3 provide a differential 50 input termination. R5 and R6
can be increased to reduce gain peaking when driving from a high source
impedance. The 50 termination provides an insertion loss of 6 dB. C2
and C3 provide ac-coupling.
T2 = Macom
TM ETC1-1-13
R1 = open, R2 = 25 ,
R3 = 25 , R4 = 0 ,
R5 = 0 , R6 = 0 ,
C2 = 0.1 F, C3 = 0.1 F
R7, R8, R9, R11,
R12, R13, R14,
T1, C4, C5
Resistors,
Transformer,
Capacitors
Output Interface. R13 and R14 ground one side of the differential output
interface for single-ended applications. T1 is a 1-to-1 impedance ratio
balun to transform a balanced differential signal to a single-ended signal.
R8, R9, and R12 are provided for generic placement of matching
components. R7 and R11 allow additional output series resistance when
driving capacitive loads. The evaluation board is configured to provide a
150 to 50 impedance transformation with an insertion loss of 11.6 dB.
C4 and C5 provide ac-coupling. R7 and R11 provide additional series
resistance when driving capacitive loads.
T1= Macom ETC1-1-13
R7 = 0 , R8 = 86.6 ,
R9 = 57.6 ,
R11 = 0 , R12 = 86.6 ,
R13 = 0 , R14 = open
C4 = 0.1 F, C5 = 0.1 F
R
G
Resistor
Gain Setting Resistor. Resistor R
G
is used to set the gain of the device.
Refer to Table 6 and Table 7 when selecting the gain resistor.
R
G
= 115 (Size 0402)
for a gain of 10 dB
C1, C6, C7
Capacitors
Power Supply Decoupling. The supply decoupling consists of a 10 F
capacitor to ground. C6 and C7 are bypass capacitors.
C1 = 10 F
C6, C7 = 0.1 F
Pin 14
VCM
Common-Mode Offset Adjustment. Use Pin 14 to trim common-mode
input/output levels. By applying a voltage to Pin 14, the input and output,
common-mode voltage can be directly adjusted.
Typically decoupled to
ground using a 0.1 F
capacitor with
ac-coupled
input/output ports
AD8352
Rev. 0 | Page 17 of 20
EVALUATION BOARD LOADING SCHEMES
The AD8352 evaluation board is characterized with two load
configurations representing the most common ADC input
resistance. The loads chosen are 200 and 1000 using a
broadband resistive match. The loading can be changed via R8,
R9, and R12 giving the flexibility to characterize the AD8352
evaluation board for the load in any given application. These
loads are inherently lossy and thus must be accounted for in
overall gain/loss for the entire evaluation board. Measure the
gain of the AD8352 with an oscilloscope using the following
procedure to determine the actual gain:
1.
Measure the peak-to-peak voltage at the input node
(C2 or C3), and
2.
Measure the peak-to-peak voltage at the output node
(C4 or C5), then
3.
Compute gain using the formula
Gain = 20log V
OUT
/V
IN
Table 11. Values Used for 200 and 1000 Loads
Component
200 Load
1000 Load
R8 86.6
487
R9 57.6
51.1
R12 86.6
487
AD8352
Rev. 0| Page 18 of 20
EVALUATION BOARD SCHEMATICS
J2
J1
51
42
3
C12 0.
1
F
C11 0.
1
F
T3
51
42
3
T4
+
C7 0.
1
F
C1 10
F
C6 0.
1
F
VP
O
S
VP
O
S
RE
D
L
O
CAT
E
CAP
S
NE
AR
DUT
EN
B
VC
M
C8 0.
1F
C9 0.
1F
Z1
VPO
S
R1
9
0
R18 0
E
NBL
Y
EL
L
O
W
YEL
L
O
W
B
L
ACK
GN
D
S
W
I
T
CH_S
P
DT
VC
M
VC
M
EN
B
C10 0.
1
F
VP
O
S
R2
0
0
R1 OP
E
N
R4 0
R2 25
R5 0
R3 25
R6 0
VI
N
P
VI
N
N
T2
4
15
2
3
M
/
A_CO
M
ET
C
1
-1-1
3
C2
0.
1
F
C3
0.
1
F
C
D
0.
2p
F
R
D
4.
32k
R
G
11
5
1
2
3
4
12
11
10
9
RDP
VI
P
VI
N
RG
P
RG
N
RDN
GN
D
VO
P
VO
N
GN
D
VP
O
S
16
15
14
13
56
7
8
ENB
VCM
VCC
GND
GND
VCC
A
D
8352
R7 0
R8
86.
6
R12 86.
6
R1
1
0
R9
57.
6
C4
0
.
1F
C5
0
.
1F
T1
4
1
5
23
M
/
A_
CO
M
ET
C
1
-1
-
1
3
R1
4
OP
E
N
R1
3
0
VO
U
T
P
VO
U
T
N
50
T
RACE
S
50
T
RACE
S
HI
G
H I
M
P
E
D
ANCE
T
RACE
S
(
O
P
E
N
P
L
ANE
S
U
NDE
R
T
RACE
S
)
0
57
28
-
0
17
SW
1
CA
L
I
BR
AT
I
O
N
CI
R
CU
I
T
B
Y
P
AS
S
CI
R
CU
I
T
Figure 36. Preliminary Characterization Board v.A01212A
AD8352
Rev. 0 | Page 19 of 20
05
72
8-
0
18
Figure 37. Component Side Silk Screen
0
57
28
-
0
19
Figure 38. Far Side Showing Ground Plane Pull Back Around Critical Features
AD8352
Rev. 0| Page 20 of 20
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATOR
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12 MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW)
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8352ACPZ-WP
-40C to +85C
16-Lead LFCSP_VQ
CP-16-3
1
AD8352ACPZ-R7
-40C to +85C
16-Lead LFCSP_VQ, 7" Tape and Reel
CP-16-3
1
AD8352-EVAL
Evaluation
Board
1
Z = Pb-free part.
2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05728-0-1/06(0)
PDF 
ZIP