AD8556 Digitally Programmable Sensor Signal Amplifier with EMI Filters Data Sheet (REV. 0)
Digitally Programmable Sensor Signal
Amplifier with EMI Filters
AD8556
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
EMI filters at input pins
Specified from -40C to +140C
Low offset voltage: 10 V max
Low input offset voltage drift: 65 nV/C max
High CMRR: 94 dB min
Digitally programmable gain and output offset voltage
Programmable output clamp voltage
Open and short wire fault detection
Low-pass filtering
Single-wire serial interface
Stable with any capacitive load
SOIC_N and LFCSP_VQ packages
2.7 V to 5.5 V operation
APPLICATIONS
Automotive sensors
Pressure and position sensors
Precision current sensing
Strain gages
FUNCTIONAL BLOCK DIAGRAM
VDD
VSS
05448-053
VDD
VSS
1
2
3
+IN
IN
OUT
A3
VDD
VSS
1
2
3
+IN
IN
OUT
A4
VOUT
VDD
VSS
1
2
3
+IN
IN
OUT
A2
VDD
VSS
1
2
3
+IN
IN
OUT
A1
VSS
1
2
3
+IN
IN
OUT
A5
R7
P4
R5
VDD
DIGIN
VCLAMP
R3
P2
P1
R1
R2
R4
R6
P3
VNEG
VPOS
DAC
LOGIC
EMI
FILTER
EMI
FILTER
EMI
FILTER
RF
EMI
FILTER
FILT/DIGOUT
AD8556
VSS
EMI
FILTER
+IN
IN
Figure 1.
AD8556
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 16
Gain Values.................................................................................. 17
Open Wire Fault Detection....................................................... 18
Shorted Wire Fault Detection................................................... 18
Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 18
Device Programming................................................................. 18
EMI/RFI Performance ................................................................... 24
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
REVISION HISTORY
5/05--Revision 0: Initial Version
AD8556
Rev. 0 | Page 3 of 28
GENERAL DESCRIPTION
The AD8556 is a zero-drift, sensor signal amplifier with
digitally programmable gain and output offset. Designed to
easily and accurately convert variable pressure sensor and
strain bridge outputs to a well-defined output voltage range,
the AD8556 accurately amplifies many other differential or
single-ended sensor outputs. The AD8556 uses the ADI
patented low noise auto-zero and DigiTrim technologies to
create an incredibly accurate and flexible signal processing
solution in a very compact footprint.
Gain is digitally programmable in a wide range from 70 to
1,280 through a serial data interface. Gain adjustment can
be fully simulated in-circuit and then permanently pro-
grammed with reliable polyfuse technology. Output offset
voltage is also digitally programmable and is ratiometric to the
supply voltage. AD8556 also features internal EMI filters on the
VNEG, VPOS, FILT and VCLAMP pins.
In addition to extremely low input offset voltage, low input
offset voltage drift, and very high dc and ac CMRR, the
AD8556 also includes a pull-up current source at the input pins
and a pull-down current source at the VCLAMP pin. This
allows open wire and shorted wire fault detection. A low-pass
filter function is implemented via a single low cost external
capacitor. Output clamping set via an external reference voltage
allows the AD8556 to drive lower voltage ADCs safely and
accurately.
When used in conjunction with an ADC referenced to the same
supply, the system accuracy becomes immune to normal supply
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment
further ensures field reliability.
The AD8556 is fully specified from -40C to +140C.
Operating from single-supply voltages of 2.7 V to 5.5 V, the
AD8556 is offered in the 8-lead SOIC_N, and 4 mm 4 mm
16-lead LFCSP_VQ.
AD8556
Rev. 0 | Page 4 of 28
SPECIFICATIONS
VDD = 5.0 V, VSS = 0.0 V, V
CM
= 2.5 V, V
O
= 2.5 V, -40C T
A
+140C, unless otherwise specified.
Table 1. Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT STAGE
Input Offset Voltage
V
OS
-40C T
A
+125C
2
10
V
-40C T
A
+140C
3
12
V
Input Offset Voltage Drift
T
C
V
OS
25
65
nV/C
Input Bias Current
I
B
T
A
= 25C
38
49
54
nA
-40C T
A
+125C
58
nA
-40C T
A
+140C
60
nA
Input Offset Current
I
OS
T
A
= 25C
0.2
2.5
nA
-40C T
A
+125C
3.0
nA
-40C T
A
+140C
4.0
nA
Input Voltage Range
2.1
2.9
V
Common-Mode Rejection Ratio
CMRR
V
CM
= 2.1 V to 2.9 V, A
V
= 70
80
92
dB
V
CM
= 2.1 V to 2.9 V, A
V
= 1,280
94
112
dB
Linearity
V
O
= 0.2 V to 3.4 V
20
ppm
V
O
= 0.2 V to 4.8 V
1,000
ppm
Differential Gain Accuracy
Second stage gain = 17.5 to 100
0.35
1.6
%
Second stage gain = 140 to 200
0.5
2.5
%
Differential Gain Temperature
Coefficient
Second stage gain = 17.5 to 100
7
20
ppm/C
Second stage gain = 140 to 200
10
40
ppm/C
RF
14
18
22
k
RF Temperature Coefficient
600
ppm/C
DAC
Accuracy
A
V
= 70, offset codes = 8 to 248
0.2
0.6
%
Ratiometricity
A
V
= 70, offset codes = 8 to 248
50
ppm
Output Offset
A
V
= 70, offset codes = 8 to 248
5
35
mV
Temperature Coefficient
-40C T
A
+125C
3.3
15
ppm FS/C
-40C T
A
+140C
25
ppm FS/C
VCLAMP
Input Bias Current
T
A
= 25C, VCLAMP = 5 V
200
nA
-40C T
A
+125C, VCLAMP = 5 V
500
nA
-40C T
A
+140C, VCLAMP = 5 V
550
nA
Input Voltage Range
1.2
4.94
V
OUTPUT BUFFER STAGE
Buffer Offset
3
7
mV
Short-Circuit Current
I
SC
5
10
mA
Output Voltage, Low
V
OL
R
L
= 10 k to 5 V
20
mV
Output Voltage, High
V
OH
R
L
= 10 k to 0 V
4.94
V
POWER SUPPLY
Supply Current
I
SY
-40C T
A
+125C, V
O
= 2.5 V, VPOS = VNEG =
2.5 V, VDAC code = 128;
2.0
2.7
mA
-40C T
A
+140C, V
O
= 2.5 V, VPOS = VNEG =
2.5 V, VDAC Code = 128
2.78
mA
Power Supply Rejection Ratio
PSRR
A
V
= 70
109
125
dB
Supply Voltage Required During
Programming
10
C < T
PROG
< 40
C, supply capable of driving
250 mA
5.0 5.25 5.5 V
AD8556
Rev. 0 | Page 5 of 28
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBP
First gain stage, T
A
= 25C
2
MHz
Second gain stage, T
A
= 25C
8
MHz
Output buffer stage, T
A
= 25C
1.5
MHz
Output Buffer Slew Rate
SR
A
V
= 70, R
L
= 10 k, C
L
= 100 pF, T
A
= 25C
1.2
V/s
Settling Time
t
s
To 0.1%, A
V
= 70, 4 V output step, T
A
= 25C
8
s
NOISE PERFORMANCE
Input Referred Noise
T
A
= 25C, f = 1 kHz
32
nV/Hz
Low Frequency Noise
e
n
p-p
f = 0.1 Hz to 10 Hz, T
A
= 25C
0.5
V p-p
Total Harmonic Distortion
THD
V
IN
= 16.75 mV rms, f = 1 kHz, A
V
= 100, T
A
= 25C
-100
dB
DIGITAL INTERFACE
Input Current
2
A
DIGIN Pulse Width to Load 0
tw
0
T
A
= 25C
0.05
10
s
DIGIN Pulse Width to Load 1
tw
1
T
A
= 25C
50
s
Time Between Pulses at DIGIN
tw
s
T
A
= 25C
10
s
DIGIN Low
T
A
= 25C
1
V
DIGIN High
T
A
= 25C
4
V
DIGOUT Logic 0
T
A
= 25C
1
V
DIGOUT Logic 1
T
A
= 25C
4
V
AD8556
Rev. 0 | Page 6 of 28
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage
6 V
Input Voltage
VSS - 0.3 V to VDD + 0.3 V
Differential Input Voltage
1
5.0 V
Output Short-Circuit Duration to
VSS or VDD
Indefinite
Storage Temperature Range
-65C to +150C
Operating Temperature Range
-40C to +150C
Junction Temperature Range
-65C to +150C
Lead Temperature Range
300C
1
Differential input voltage is limited to 5.0 V or the supply voltage, which-
ever is less.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
JA
1
JC
Unit
8-Lead SOIC_N (R)
158
43
C/W
16-Lead LFCSP_VQ (CP)
44
31.5
C/W
1
JA
is specified for the worst-case conditions, that is,
JA
is specified for device
soldered in circuit board for LFCSP_VQ package.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8556
Rev. 0 | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
05448-002
VDD
1
FILT/DIGOUT
2
DIGIN
3
VNEG
4
VSS
8
VOUT
7
VCLAMP
6
VPOS
5
AD8556
TOP VIEW
(Not to Scale)
Figure 2. 8-Lead SOIC_N Pin Configuration
05448-003
12
11
10
9
NC
VCLAMP
NC
VOUT
1
NC
2
3
5
NC
VN
EG
NC
VPOS
6
7
8
4
DIGIN
NC
FILT/DIGOUT
16
15
14
13
AD8556
TOP VIEW
PIN 1
INDICATOR
AV
DD
DV
DD
A
VSS
D
VSS
NC = NO CONNECT
Figure 3.16-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
SOIC_N LFCSP_VQ
Mnemonic Description
1
VDD
Positive
Supply
Voltage.
2 2
FILT/DIGOUT
Unbuffered Amplifier Output in Series with a Resistor RF. Adding a capacitor between FILT and
VDD or VSS implements a low-pass filtering function. In read mode, this pin functions as a
digital output.
3 4
DIGIN Digital
Input.
4 6
VNEG Negative
Amplifier
Input (Inverting Input).
5 8
VPOS Positive
Amplifier
Input (Noninverting Input).
6
10
VCLAMP
Set Clamp Voltage at Output.
7 12
VOUT Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT pin. In read
mode, VOUT is a buffered digital output.
8
VSS
Negative Supply Voltage.
13, 14
DVSS, AVSS
Negative Supply Voltage.
15, 16
DVDD, AVDD
Positive Supply Voltage.
1, 3, 5, 7, 9, 11
NC
Do Not Connect.
AD8556
Rev. 0 | Page 8 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
05448-004
V
OS
5V (
V)
10
10
5
0
5
HITS
100
60
80
40
20
0
N: 363,
MEAN: 0.389938,
SD: 1.65684
Figure 4. Input Offset Voltage Distribution
05448-005
V
CM
(V)
3.5
1.5
2.0
2.5
3.0
V
OSi
(
V)
2.0
0.5
1.0
1.5
1.0
0.5
0
2.0
1.5
2.5
3.0
V
S
= 5V
T
A
= 25C
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
05448-006
TEMPERATURE (C)
150
50
25
0
25
50
75
100
125
IN
PU
T OFFSET VOLTA
GE (
V)
10
8
6
4
2
0
2
4
6
8
10
V
SY
= 5V
Figure 6. Input Offset Voltage vs. Temperature
05448-007
T
C
V
OS
(nV/C)
MORE
0
10
20
30
40
NUMBE
R OF AMP
L
IFIE
RS
25
15
20
10
5
0
V
SY
= 5V
Figure 7. T
C
V
OS
at V
SY
= 5 V
05448-009
TEMPERATURE (C)
150
50
25
0
25
50
75
100
125
BUFFER OFFSET VOLTAGE (mV)
1.9
1.5
1.7
1.1
1.3
0.9
0.7
0.5
V
OUT
= 0.3V
V
OUT
= 4.7V
V
SY
= 5V
Figure 8. Output Buffer Offset vs. Temperature
05448-010
TEMPERATURE (C)
150
50
25
0
25
50
75
100
125
INP
U
T BIAS
CURRE
NT (nA)
100
10
1
V
SY
= 5V
Figure 9. Input Bias Current at VPOS, VNEG vs. Temperature
AD8556
Rev. 0 | Page 9 of 28
05448-011
V
CM
(V)
6
0
1
2
3
4
5
I
B
(nA)
100
10
1
I
B
I
B
+
V
SY
= 5
T
A
= 25C
Figure 10. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage
05448-012
TEMPERATURE (C)
150
50
25
0
25
50
75
100
125
INP
U
T OFFS
E
T
CURRE
NT (nA)
0.8
0.6
0.5
0
0.2
0.2
0.3
0.3
0.5
0.6
0.8
V
SY
= 5V
Figure 11. Input Offset Current vs. Temperature
05448-013
DIGITAL INPUT VOLTAGE (V)
6
0
1
2
3
4
5
DIGITAL INP
U
T CURRE
NT (
A)
0
2.5
2.0
1.5
1.0
0.5
V
S
= 5.5V
Figure 12. Digital Input Current vs. Digital Input Voltage (Pin 4)
05448-014
VCLAMP VOLTAGE (V)
6
0
2
3
1
4
5
V
C
LAMP
CURRE
NT (nA)
10
1000
100
40C
+25C
+125C
V
S
= 5V
Figure 13. VCLAMP Current over Temperature at V
S
= 5 V vs. VCLAMP Voltage
05448-015
SUPPLY VOLTAGE (V)
6
0
1
2
3
5
4
S
U
P
P
L
Y
CURRE
NT (mA)
3.0
2.5
2.0
1.5
0.5
1.0
0
T
A
= 25C
Figure 14. Supply Current (I
SY
) vs. Supply Voltage
05448-016
TEMPERATURE (C)
150
50
25
0
25
50
75
100
125
S
U
P
P
L
Y
CURRE
NT (mA)
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
V
SY
= 5V
Figure 15. Supply Current (I
SY
) vs. Temperature
AD8556
Rev. 0 | Page 10 of 28
05448-017
FREQUENCY (Hz)
1M
100k
100
1k
10k
CMRR (dB)
40
80
120
0
V
S
= 2.5V
GAIN = 70
Figure 16. CMRR vs. Frequency
05448-018
FREQUENCY (Hz)
1M
100
1k
10k
100k
CMRR (dB)
120
80
40
0
V
S
= 2.5V
GAIN = 1280
Figure 17. CMRR vs. Frequency
05448-019
TEMPERATURE (C)
150
50
25
0
25
50
75
100
125
GAIN = 1280
GAIN = 800
GAIN = 400
GAIN = 200
GAIN = 100
GAIN = 70
CMRR (dB)
145
135
125
115
105
95
85
75
V
SY
= 5V
Figure 18. CMRR vs. Temperature at Different Gains
05448-020
FREQUENCY (kHz)
10
5
0
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/ H
z
)
60
50
40
30
20
10
V
S
= 2.5V
GAIN = 70
Figure 19. Input Voltage Noise Density vs. Frequency (0 Hz to 10 kHz)
05448-021
FREQUENCY (kHz)
500
250
0
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/ H
z
)
30
25
20
15
10
5
V
S
= 2.5V
GAIN = 70
35
Figure 20. Input Voltage Noise Density vs. Frequency (0 Hz to 500 kHz)
05448-022
TIME (1s/DIV)
N
OISE (
V)
0.6
0.4
0.2
0
0.2
0.4
0.6
V
S
= 2.5V
GAIN = 1000
Figure 21. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
AD8556
Rev. 0 | Page 11 of 28
Figure 22. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
05448-024
FREQUENCY (Hz)
1k
100k
10k
1M
GAIN = 1280
GAIN = 70
V
S
= 2.5V
C
L
= 40PF
CLOSED-
L
OOP GAIN (
d
B)
60
40
20
0
Figure 23. Closed-Loop Gain vs. Frequency Measured at Filter Pin
05448-025
FREQUENCY (Hz)
1k
100k
10k
1M
GAIN = 70
GAIN = 1280
V
S
= 2.5V
CLOSED-
L
OOP GAIN (
d
B)
60
40
20
0
Figure 24. Closed-Loop Gain vs. Frequency Measured at Output Pin
05448-026
FREQUENCY (Hz)
1k
100k
10k
1M
10M
V
S
= 2.5V
GAIN (
d
B)
4
8
0
4
8
Figure 25. Output Buffer Gain vs. Frequency
05448-027
LOAD CAPACITANCE (nF)
100
0.1
1
10
OVER
SH
OOT (
%
)
60
50
40
30
20
10
0
R
S
C
L
OUTPUT
BUFFER
V
S
= 2.5V
R
S
= 0
R
S
= 10
R
S
= 20
R
S
= 50
R
S
= 100
Figure 26. Output Buffer Positive Overshoot
05448-028
LOAD CAPACITANCE (nF)
100.0
0.1
1.0
10.0
OVER
SH
OOT (
%
)
60
50
40
30
20
10
0
R
S
C
L
V
S
= 2.5V
R
S
= 0
R
S
= 10
R
S
= 20
R
S
= 50
R
S
= 100
Figure 27. Output Buffer Negative Overshoot
AD8556
Rev. 0 | Page 12 of 28
05448-029
LOAD CURRENT (mA)
10.0
0.01
0.10
1.00
VDD
OUTPUT VOLTAGE (V)
0.001
1.000
0.100
0.010
V
S
= 2.5V
SINK
SOURCE
Figure 28. Output Voltage to Supply Rail vs. Load Current
05448-030
TEMPERATURE (C)
175
75
50
25
0
25
50
75
100
125
150
OUTP
UT S
H
ORT CIRCUIT (mA)
15
15
12
6
3
0
9
3
6
9
12
SINK 5V
SOURCE 5V
Figure 29. Output Short-Circuit vs. Temperature
TIME (100
s/DIV)
VOLTAGE
2
4
0
3
2
1
0
05448-031
SUPPLY VOLTAGE
V
OUT
Figure 30. Power-On Response at 25C
TIME (100
s/DIV)
VOLTA
G
E (
1
V/D
I
V)
5
6
4
3
2
1
0
05448-032
SUPPLY VOLTAGE
V
OUT
Figure 31. Power-On Response at 125C
TIME (100
s/DIV)
VOLTA
GE (
1
V/D
I
V)
5
6
4
3
2
1
0
05448-033
SUPPLY VOLTAGE
V
OUT
Figure 32. Power-On Response at
-40C
05448-034
TEMPERATURE (C)
150
75
50
25
0
25
50
75
100
125
P
S
RR (dB)
100
150
135
130
125
145
140
120
115
110
105
V
S
= 2.7V TO 5.5V
Figure 33. PSRR vs. Temperature
AD8556
Rev. 0 | Page 13 of 28
05448-035
FREQUENCY (kHz)
100
0.01
0.1
1
10
P
S
RR (dB)
140
120
100
80
60
40
20
0
V
S
= 2.7V TO 2.5V
Figure 34. PSRR vs. Frequency
05448-036
TIME (100
s/DIV)
VOU
T
(
50mV/D
I
V)
2
T
V
S
= 2.5V
GAIN = 70
C
L
= 0.1
F
F
IN
= 10kHz
Figure 35. Small Signal Response
05448-037
TIME (100
s/DIV)
VOU
T
(
50mV/D
I
V)
T
2
V
S
= 2.5V
GAIN = 70
C
L
= 100pF
F
IN
= 1kHz
Figure 36. Small Signal Response
05448-038
TIME (10
s/DIV)
VOU
T
(
1
V/D
I
V)
2
T
V
S
= 2.5V
GAIN = 70
C
L
= 100pF
Figure 37. Large Signal Response
05448-039
TIME (10
s/DIV)
VOU
T
(
1
V/D
I
V)
2
T
V
S
= 2.5V
GAIN = 70
C
L
= 0.05
F
Figure 38. Large Signal Response
05448-040
FREQUENCY (kHz)
0.1
10
1
100
1M
IMP
E
DANCE
(
)
1
10
100
1k
V
SY
= 2.5V
A
V
= 70
Figure 39. Output Impedance vs. Frequency
AD8556
Rev. 0 | Page 14 of 28
05448-041
0V
0V
V
IN
V
OUT
CH1 50.0mV
CH2
2.00V
M 1.00
s
A CH1
21.0mV
2
1
Figure 40. Negative Overload Recovery (Gain = 70)
05448-042
0V
0V
V
IN
V
OUT
CH1 50.0mV
CH2
2.00V
M 1.00
s
A CH1 57.0mV
2
1
Figure 41. Positive Overload Recovery (Gain = 70)
05448-043
0V
0V
V
IN
2.5V
CH1 10.0mV
CH2
2.00V
M 4.00
s A CH1
9.40mV
2
1
Figure 42. Negative Overload Recovery (Gain = 1280)
0V
0V
V
IN
V
OUT
CH1
10.0mV
CH2 2.00V
M 4.00
s
A CH1 8.40mV
1
2
05448-044
Figure 43. Positive Overload Recovery (Gain = 1280)
0.1
F
0.1
F
V
294
20.5
+V
4
1
6
7
8
5
10k
1k
10k
OUT
DUT
4V pp
GAIN = 70
OFFSET = 128
V
S
= 2.5V
CH1 2.00mV
CH2
2.00mV
M 1.00
s
A CH1 40.0mV
2
1
05448-045
Figure 44. Settling Time 0.1%
05448-046
0.1
F
0.1
F
V
294
20.5
+V
4
1
6
7
8
5
10k
1k
10k
OUT
DUT
4V pp
GAIN = 70
OFFSET = 128
V
S
= 2.5V
0V
0V
2
1
CH1 2.00mV
CH2
2.00mV
M 1.00
s
A CH1 40.0mV
Figure 45. Settling Time 0.01%
AD8556
Rev. 0 | Page 15 of 28
05448-047
FREQUENCY (Hz)
THD (%)
20
1k
2k
200
100
50
500
5k
10k
20k
0.10
1.00
0.20
0.50
0.02
0.05
0.01
V
S
= 2.5V
Figure 46. THD vs. Frequency
AD8556
Rev. 0 | Page 16 of 28
THEORY OF OPERATION
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiome-
ters, guaranteed to be monotonic. Programming P1 and P2
allows the first stage gain to be varied from 4.0 to 6.4 with 7-bit
resolution (see Table 5 and Equation 1), giving a fine gain
adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each
have a similar temperature coefficient, so the first stage gain
temperature coefficient is lower than 100 ppm/C.
127
4
6.4
4
Code
GAIN1
(1)
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of
the differential amplifier. A3 is also an auto-zeroed op amp that
minimizes input offset errors. P3 and P4 are digital potenti-
ometers, which allow the second stage gain to be varied from
17.5 to 200 in eight steps (see Table 6). R4, R5, R6, R7, P3, and
P4 each have a similar temperature coefficient, so the second
stage gain temperature coefficient is lower than 100 ppm/C.
RF together with an external capacitor, connected between
FILT/DIGOUT and VSS or VDD, form a low-pass filter. The
filtered signal is buffered by A4 to give a low impedance output
at VOUT. RF is nominally 18 k, allowing an 880 Hz low-pass
filter to be implemented by connecting a 10 nF external
capacitor between FILT/DIGOUT and VSS, or between
FILT/DIGOUT and VDD. If low-pass filtering is not needed,
the FILT/DIGOUT pin must be left floating.
A5 implements a voltage buffer, which provides the positive
supply to A4, the amplifier output buffer. Its function is to limit
VOUT to a maximum value, useful for driving analog-to-digital
converters (ADC) operating on supply voltages lower than
VDD. The input to A5, VCLAMP, has a very high input
resistance. It should be connected to a known voltage and not
left floating. However, the high input impedance allows the
clamp voltage to be set using a high impedance source, such as,
a potential divider. If the maximum value of VOUT does not
need to be limited, VCLAMP should be connected to VDD.
A4 implements a rail-to-rail input and output unity-gain
voltage buffer. The output stage of A4 is supplied from a
buffered version of VCLAMP instead of VDD, allowing the
positive swing to be limited. The maximum output current is
limited between 5 mA to 10 mA.
An 8-bit digital-to-analog converter (DAC) is used to generate
a variable offset for the amplifier output. This DAC is guaran-
teed to be monotonic. To preserve the ratiometric nature of the
input signal, the DAC references are driven from VSS and VDD,
and the DAC output can swing from VSS (Code 0) to VDD
(Code 255). The 8-bit resolution is equivalent to 0.39% of the
difference between VDD and VSS, for example, 19.5 mV with
a 5 V supply. The DAC output voltage (VDAC) is given
approximately by
(
)
VSS
VSS
VDD
Code
VDAC
+
-
+
256
5
.
0
(2)
Where the temperature coefficient of VDAC is lower than
200 ppm/C.
The amplifier output voltage (VOUT) is given by
(
)
VDAC
VNEG
VPOS
GAIN
VOUT
+
-
=
(3)
where GAIN is the product of the first and second stage gains.
A3
A2
A4
A5
VDD
VDD
DAC
VSS
VSS
VDD
VSS
VDD
VDD
VSS
VCLAMP
VPOS
VSS
FILT/
DIGOUT
VOUT
A1
VDD
VSS
VNEG
R1
R3
R2
R5
R7
P4
R4
R6
RF
P3
P2
P1
05448-001
Figure 47. Functional Schematic
AD8556
Rev. 0 | Page 17 of 28
GAIN VALUES
Table 5. First Stage Gain vs. First Stage Gain Code
First Stage
Gain Code
First Stage Gain
First Stage
Gain Code
First Stage Gain
First Stage
Gain Code
First Stage Gain
First Stage
Gain Code
First Stage Gain
0
4.000
32
4.503
64
5.069
96
5.706
1
4.015
33
4.520
65
5.088
97
5.727
2
4.030
34
4.536
66
5.107
98
5.749
3
4.045
35
4.553
67
5.126
99
5.770
4
4.060
36
4.570
68
5.145
100
5.791
5
4.075
37
4.587
69
5.164
101
5.813
6
4.090
38
4.604
70
5.183
102
5.834
7
4.105
39
4.621
71
5.202
103
5.856
8
4.120
40
4.638
72
5.221
104
5.878
9
4.135
41
4.655
73
5.241
105
5.900
10
4.151
42
4.673
74
5.260
106
5.921
11
4.166
43
4.690
75
5.280
107
5.943
12
4.182
44
4.707
76
5.299
108
5.965
13
4.197
45
4.725
77
5.319
109
5.988
14
4.213
46
4.742
78
5.339
110
6.010
15
4.228
47
4.760
79
5.358
111
6.032
16
4.244
48
4.778
80
5.378
112
6.054
17
4.260
49
4.795
81
5.398
113
6.077
18
4.276
50
4.813
82
5.418
114
6.099
19
4.291
51
4.831
83
5.438
115
6.122
20
4.307
52
4.849
84
5.458
116
6.145
21
4.323
53
4.867
85
5.479
117
6.167
22
4.339
54
4.885
86
5.499
118
6.190
23
4.355
55
4.903
87
5.519
119
6.213
24
4.372
56
4.921
88
5.540
120
6.236
25
4.388
57
4.939
89
5.560
121
6.259
26
4.404
58
4.958
90
5.581
122
6.283
27
4.420
59
4.976
91
5.602
123
6.306
28
4.437
60
4.995
92
5.622
124
6.329
29
4.453
61
5.013
93
5.643
125
6.353
30
4.470
62
5.032
94
5.664
126
6.376
31
4.486
63
5.050
95
5.685
127
6.400
Table 6. Second Stage Gain and Gain Ranges vs. Second Stage Gain Code
Second Stage Gain Code
Second Stage Gain
Minimum Combined Gain
Maximum Combined Gain
0 17.5
70
112
1 25
100
160
2 35
140
224
3 50
200
320
4 70
280
448
5 100
400
640
6 140
560
896
7 200
800
1280
AD8556
Rev. 0 | Page 18 of 28
OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a com-
parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD - 2.0 V. If (VNEG > VDD - 2.0 V) or
(VPOS > VDD - 2.0 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 49 nA
and matched to within 3 nA. If the inputs to A1 or A2 are
accidentally left floating, as with an open wire fault, IP1 and IP2
pull them to VDD which would cause VOUT to swing to VSS,
allowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.
SHORTED WIRE FAULT DETECTION
The AD8556 provides fault detection in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 48 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 7 lists the voltage levels shown in
Figure 48.
VPOS
VNEG
VSS
VINL
VINH
VDD
VSS
VCLL
VDD
VCLAMP
VSS
VINL
VINH
VDD
ERROR
ERROR
NORMAL
ERROR
NORMAL
ERROR
ERROR
NORMAL
05448-048
Figure 48. Voltage Regions at VPOS, VNEG, and VCLAMP
that Trigger a Fault Condition
Table 7. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage
Min (V)
Typ (V)
Max (V)
VOUT Condition
VINH 2.95 3.0 3.05 Short to VSS fault
detection
VINL 1.95 2.0 2.05 Short to VSS fault
detection
VCLL 1.05 1.1 1.15 Short to VSS fault
detection
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the previous section. In
this way, the VOUT pin is shorted to VSS when a floating input
is detected. Table 8 lists the currents used.
Table 8. Floating Fault Detection at VPOS, VNEG,
and VCLAMP
Pin
Typical Current
Goal of Current
VPOS
49 nA pull-up
Pull VPOS above VINH
VNEG
49 nA pull-up
Pull VNEG above VINH
VCLAMP
0.2 A pull-down
Pull VCLAMP below VCLL
DEVICE PROGRAMMING
Digital Interface
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of
inadvertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.
A short pulse at DIGIN from low to high and back to low again,
such as between 50 ns and 10 s long, loads a 0 into a shift
register. A long pulse at DIGIN, such as 50 s or longer, loads a
1 into the shift register. The time between pulses should be at
least 10 s. Assuming VSS = 0 V, voltages at DIGIN between
VSS and 0.2 VDD are recognized as a low, and voltages at
DIGIN between 0.8 VDD and VDD are recognized as a high.
A timing diagram example, Figure 49, shows the waveform for
entering code 010011 into the shift register.
AD8556
Rev. 0 | Page 19 of 28
CODE
0
1
0
0
1
1
WAVEFORM
t
W0
t
WS
t
W0
t
WS
t
WS
t
WS
t
W0
t
WS
t
W1
t
W1
t
W1
05448-049
Figure 49. Timing Diagram for Code 010011
Table 9. Timing Specifications
Timing Parameter
Description
Specification
t
w0
Pulse Width for Loading 0 into Shift Register
Between 50 ns and 10 s
t
w1
Pulse Width for Loading 1 into Shift Register
50 s
t
ws
Width Between Pulses
10 s
Table 10. 38-Bit Serial Word Format
Field No.
Bits
Description
0
0 to 11
12-Bit Start of Packet 1000 0000 0001
1
12 to 13
2-Bit Function
00: Change Sense Current
01: Simulate Parameter Value
10: Program Parameter Value
11: Read Parameter Value
2
14 to 15
2-Bit Parameter
00: Second Stage Gain Code
01: First Stage Gain Code
10: Output Offset Code
11: Other Functions
3
16 to 17
2-Bit Dummy 10
4
18 to 25
8-Bit Value
Parameter 00 (Second Stage Gain Code): 3 LSBs Used
Parameter 01 (First Stage Gain Code): 7 LSBs Used
Parameter 10 (Output Offset Code): All 8 Bits Used
Parameter 11 (Other Functions)
Bit 0 (LSB): Master Fuse
Bit 1: Fuse for Production Test at Analog Devices
Bit 2: Parity Fuse
5
26 to 37
12-Bit End of Packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 s, the 38-bit serial word transfers
in 2.3 ms. Table 10 summarizes the word format.
Field 0 and Field 5 are the start-of-packet field and end-of-
packet field, respectively. Matching the start-of-packet field with
1000 0000 0001 and the end-of-packet field with 0111 1111
1110 ensures that the serial word is valid and enables decoding
of the other fields.
Field 3 breaks up the data and ensures that no data combination
can inadvertently trigger the start-of-packet and end-of-packet
fields. Field 0 should be written first and Field 5 written last.
Within each field, the MSB must be written first and the LSB
written last. The shift register features power-on reset to mini-
mize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
AD8556
Rev. 0 | Page 20 of 28
Initial State
Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 11).
Table 11. Initial State Before Programming
Second Stage Gain Code = 0
Second Stage Gain = 17.5
First stage gain code = 0
First stage gain = 4.0
Output offset code = 0
Output offset = VSS
Master fuse = 0
Master fuse not blown
When power is applied to a device, parameter values are taken
either from internal registers, if the master fuse is not blown,
or from the polysilicon fuses, if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset, so the
unprogrammed devices enter a known state after power-up.
Power-on reset occurs when VDD is between 0.7 V and 2.2 V.
Simulation Mode
The simulation mode allows any parameter to be temporarily
changed. These changes are retained until the simulated value is
reprogrammed, the power is removed, or the master fuse is
blown. Parameters are simulated by setting Field 1 to 01,
selecting the desired parameter in Field 2, and the desired value
for the parameter in Field 4. Note that a value of 11 for Field 2 is
ignored during the simulation mode. Examples of temporary
settings follow:
Setting the second stage gain code (Parameter 00) to 011 and
the second stage gain to 50 produces:
1000 0000 0001 01 00 10 0000 0011 0111 1111 1110
Setting the first stage gain code (Parameter 01) to 000 1011
and the first stage gain to 4.166 produces:
1000 0000 0001 01 01 10 0000 1011 0111 1111 1110
A first stage gain of 4.166 with a second stage gain of 50 gives a
total gain of 208.3. This gain has a maximum tolerance of 2.5%.
Set the output offset code (Parameter 10) to 0100 0000 and
the output offset to 1.260 V when VDD = 5 V and VSS = 0 V.
This output offset has a maximum tolerance of 0.8%:
1000 0000 0001 01 10 10 0100 0000 0111 1111 1110
Programming Mode
Intact fuses give a bit value of 0. Bits with a desired value of 1
need to have the associated fuse blown. Since a relatively large
current is needed to blow a fuse, only one fuse can be reliably
blown at a time. Thus, a given parameter value may need
several 38-bit words to allow reliable programming. A 5.25 V
(0.25 V) supply is required when blowing fuses to minimize
the on resistance of the internal MOS switches that blow the
fuse. The power supply voltage must not exceed the absolute
maximum rating and must be able to deliver 250 mA of current.
At least 10 F (tantalum type) of decoupling capacitance is
needed across the power pins of the device during program-
ming. The capacitance can be on the programming apparatus as
long as it is within 2 inches of the device being programmed.
An additional 0.1 F (ceramic type) in parallel with the 10 F is
recommended within inch of the device being programmed.
A minimum period of 1 ms should be allowed for each fuse to
blow. There is no need to measure the supply current during
programming.
The best way to verify correct programming is to use the read
mode to read back the programmed values. Then, remeasure
the gain and offset to verify these values. Programmed fuses
have no effect on the gain and output offset until the master
fuse is blown. After blowing the master fuse, the gain and
output offset are determined solely by the blown fuses, and the
simulation mode is permanently deactivated.
Parameters are programmed by setting Field 1 to 10, selecting
the desired parameter in Field 2, and selecting a single bit with
the value 1 in Field 4.
As an example, suppose the user wants to permanently set the
second stage gain to 50. Parameter 00 needs to have the value
0000 0011 assigned. Two bits have the value 1, so two fuses need
to be blown. Since only one fuse can be blown at a time, this
code can be used to blow one fuse:
1000 0000 0001 10 00 10 0000 0010 0111 1111 1110
The MOS switch that blows the fuse closes when the complete
packet is recognized, and opens when the start-of-packet,
dummy, or end-of-packet fields are no longer valid. After 1 ms,
this second code is entered to blow the second fuse:
1000 0000 0001 10 00 10 0000 0001 0111 1111 1110
To permanently set the first stage gain to a nominal value of
4.151, Parameter 01 needs to have the value 000 1011 assigned.
Three fuses need to be blown, and the following codes are used,
with a 1 ms delay after each code:
1000 0000 0001 10 01 10 0000 1000 0111 1111 1110
1000 0000 0001 10 01 10 0000 0010 0111 1111 1110
1000 0000 0001 10 01 10 0000 0001 0111 1111 1110
To permanently set the output offset to a nominal value of
1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to
have the value 0100 0000 assigned. If one fuse needs to be
blown, use the following code:
1000 0000 0001 10 10 10 0100 0000 0111 1111 1110
Finally, to blow the master fuse to deactivate the simulation
mode and prevent further programming, use code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110
There are a total of 20 programmable fuses. Since each fuse
requires 1 ms to blow, and each serial word can be loaded in
AD8556
Rev. 0 | Page 21 of 28
2.3 ms, the maximum time needed to program the fuses can be
as low as 66 ms.
Parity Error Detection
A parity check is used to determine whether the programmed
data of an AD8556 is valid, or whether data corruption has
occurred in the nonvolatile memory. Figure 50 shows the
schematic implemented in the AD8556.
VA0 to VA2 is the 3-bit control signal for the second stage gain,
VB0 to VB6 is the 7-bit control signal for the first stage gain,
and VC0 to VC7 is the 8-bit control signal for the output offset.
PFUSE is the signal from the parity fuse, and MFUSE is the
signal from the master fuse.
The function of the 2-input AND gate (Cell AND2) is to ignore
the output of the parity circuit (PAR_SUM signal) when the
master fuse has not been blown. PARITY_ERROR is set to 0
when MFUSE = 0. In the simulation mode, for example, parity
check is disabled. After the master fuse has been blown, that is,
after the AD8556 has been programmed, the output from the
parity circuit (PAR_SUM signal) is fed to PARITY_ERROR.
When PARITY_ERROR is 0, the AD8556 behaves as a
programmed amplifier. When PARITY_ERROR is 1, a parity
error has been detected, and VOUT is connected to VSS.
The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to
VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). The
output of Cell EOR18 is the DAT_SUM signal. DAT_SUM = 0 if
there is an even number of 1s in the 18-bit word; DAT_SUM =
1 if there is an odd number of 1s in the 18-bit word. Refer to
Table 12 for examples.
After the second stage gain, first stage gain, and output offset
have been programmed, compute DAT_SUM and set the parity
bit equal to DAT_SUM. If DAT_SUM is 0, the parity fuse should
not
be blown in order for the PFUSE signal to be 0. If
DAT_SUM is 1, the parity fuse should be blown to set the
PFUSE signal to 1. The code to blow the parity fuse is:
1000 0000 0001 10 11 10 0000 0100 01111111 1110.
After setting the parity bit, the master fuse can be blown to
prevent further programming, using the code:
1000 0000 0001 10 11 10 0000 0001 0111 1111 1110.
IN01
IN02
IN03
IN04
IN05
IN06
IN07
IN08
IN09
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
VA0
VA1
VA2
VB0
VB1
VB2
VB3
VB4
VB5
VB6
VC0
VC1
VC2
VC3
VC4
VC5
VC6
VC7
EOR18
OUT
I0
DAT_SUM
PAR_SUM
PFUSE
MFUSE
IN1
IN2
EOR2
AND2
IN1
IN2
PARITY_ERROR
I1
OUT
I2
OUT
05448-050
Figure 50. Functional Circuit of AD8556 Parity Check
Table 12. Examples of DAT_SUM
Second Stage Gain Code
First Stage Gain Code
Output Offset Code
Number of Bits with 1
DAT_SUM
000
000 0000
0000 0000
0
0
000
000 0000
1000 0000
1
1
000
000 0000
1000 0001
2
0
000
000 0001
0000 0000
1
1
000
100 0001
0000 0000
2
0
001
000 0000
0000 0000
1
1
001
000 0001
1000 0000
3
1
111
111 1111
1111 1111
18
0
AD8556
Rev. 0 | Page 22 of 28
Signal PAR_SUM is the output of the 2-input exclusive-OR
gate (Cell EOR2). After the master fuse is blown, set
PARITY_ERROR to PAR_SUM. As mentioned earlier, the
AD8556 behaves as a programmed amplifier when
PARITY_ERROR = 0 (no parity error). On the other hand,
VOUT is connected to VSS when a parity error has been
detected, that is, when PARITY_ERROR = 1.
Read Mode
The values stored by the polysilicon fuses can be sent to the
FILT/DIGOUT pin to verify correct programming. Normally,
the FILT/DIGOUT pin is only connected to the second gain
stage output via RF. During read mode, however, the
FILT/DIGOUT pin is also connected to the output of a shift
register to allow the polysilicon fuse contents to be read. Since
VOUT is a buffered version of FILT/DIGOUT, VOUT also
outputs a digital signal during read mode.
Read mode is entered by setting Field 1 to 11 and selecting the
desired parameter in Field 2. Field 4 is ignored. The parameter
value, stored in the polysilicon fuses, is loaded into an internal
shift register, and the MSB of the shift register is connected to
the FILT/DIGOUT pin. Pulses at DIGIN shift out the shift
register contents to the FILT/DIGOUT pin, allowing the 8bit
parameter value to be read after seven additional pulses; shift-
ing occurs on the falling edge of DIGIN. An eighth pulse at
DIGIN disconnects FILT/DIGOUT from the shift register and
terminates the read mode. If a parameter value is less than eight
bits long, the MSBs of the shift register are padded with 0s.
For example, to read the second stage gain, this code is used:
1000 0000 0001 11 00 10 0000 0000 0111 1111 1110
Since the second stage gain parameter value is only three bits
long, the FILT/DIGOUT pin has a value of 0 when this code is
entered, and remains 0 during four additional pulses at DIGIN.
The fifth, sixth, and seventh pulses at DIGIN return the 3-bit
value at FILT/DIGOUT, the seventh pulse returns the LSB. An
eighth pulse at DIGIN terminates the read mode.
Sense Current
A sense current is sent across each polysilicon fuse to determine
whether it has been blown. When the voltage across the fuse is
less than approximately 1.5 V, the fuse is considered not blown,
and Logic 0 is output from the OTP cell. When the voltage
across the fuse is greater than approximately 1.5 V, the fuse is
considered blown, and Logic 1 is output.
When the AD8556 is manufactured, all fuses have a low
resistance. When a sense current is sent through the fuse, a
voltage less than 0.1 V is developed across the fuse. This is
much lower than 1.5 V, so Logic 0 is output from the OTP cell.
When a fuse is electrically blown, it should have a very high
resistance. When the sense current is applied to the blown fuse,
the voltage across the fuse should be larger than 1.5 V, so
Logic 1 is output from the OTP cell.
It is theoretically possible, though very unlikely, for a fuse to be
incompletely blown during programming, assuming the
required conditions are met. In this situation, the fuse could
have a medium resistance, neither low nor high, and a voltage of
approximately 1.5 V could be developed across the fuse. Thus,
the OTP cell could output Logic 0 or a Logic 1, depending on
temperature, supply voltage, and other variables.
To detect this undesirable situation, the sense current can be
lowered by a factor of 4 using a specific code. The voltage
developed across the fuse would then change from 1.5 V to
0.38 V, and the output of the OTP would be a Logic 0 instead of
the expected Logic 1 from a blown fuse. Correctly blown fuses
would still output a Logic 1. In this way, incorrectly blown fuses
can be detected. Another specific code would return the sense
current to the normal (larger) value. The sense current cannot
be permanently programmed to the low value. When the
AD8556 is powered up, the sense current defaults to the high
value.
The low sense current code is:
1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110
The normal (high) sense current code is:
1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110
Programming Procedure
For reliable fuse programming, it is imperative to follow the
programming procedure requirements, especially the proper
supply voltage during programming.
1. When programming the AD8556, the temperature of the
device must be between 10C to 40C.
2. Set VDD and VSS to the desired values in the application.
Use simulation mode to test and determine the desired
codes for the second stage gain, first stage gain, and output
offset. The nominal values for these parameters are shown in
Table 5, Table 6, Equation 2, and Equation 3; use the codes
corresponding to these values as a starting point. However,
since actual parameter values for given codes vary from
device to device, some fine tuning is necessary for the best
possible accuracy.
One way to choose these values is to set the output offset
to an approximate value, such as Code 128 for midsupply, to
allow the required gain to be determined. Then set the
second stage gain so the minimum first stage gain (Code 0)
gives a lower gain than required, and the maximum first
stage gain (Code 127) gives a higher gain than required.
After choosing the second stage gain, the first stage gain can
be chosen to fine tune the total gain. Finally, the output
offset can be adjusted to give the desired value. After
determining the desired codes for second stage gain, first
stage gain, and output offset, the device is ready for
permanent programming.
AD8556
Rev. 0 | Page 23 of 28
Important:
Once a programming attempt has been made for
any fuse, there should be no further attempt to blow that
fuse. If a fuse does not program to the expected state, discard
the unit. The expected incidence rate of attempted but
unblown fuses is very small when following the proper
programming procedure and conditions.
3. Set VSS to 0 V and VDD to 5.25 V (0.25 V). Power supplies
should be capable of supplying 250 mA at the required
voltage and properly bypassed as described in the
Programming Mode section. Use program mode to
permanently enter the desired codes for the first stage gain,
second stage gain, and output offset. Blow the parity bit fuse
if necessary (see Parity Error Detection section). Blow the
master fuse to allow the AD8556 to read data from the fuses
and to prevent further programming.
4. Set VDD and VSS to the desired values in the application.
Use read mode with low sense current followed by high
sense current to verify programmed codes.
5. Measure gain and offset to verify correct functionality.
Determining Optimal Gain and Offset Codes
First, determine the desired gain:
1. Determine the desired gain, G
A
(using the measurements
obtained from the simulation).
2. Use Table 6 to determine G
2
, the second stage gain, such that
(4.00 1.04) < (G
A
/G
2
) < (6.4/1.04). This ensures the first and
last codes for the first stage gain are not used, thereby
allowing enough first stage gain codes within each second
stage gain range to adjust for the 3% accuracy.
Next, set the second stage gain:
1. Use the simulation mode to set the second stage gain to G
2
.
2. Set the output offset to allow the AD8556 gain to be
measured, for example, use Code 128 to set it to midsupply.
3. Use Table 5 or Equation 1 to set the first stage gain code
C
G1
, so the first stage gain is nominally G
A
/G
2
.
4. Measure the resulting gain (G
B
). G
B
should be within
3% of G
A
.
5. Calculate the first stage gain error (in relative terms)
E
G1
= G
B
/G
A
- 1.
6. Calculate the error (in the number of the first stage gain
codes) C
EG1
= E
G1
/0.00370.
7. Set the first stage gain code to C
G1
- C
EG1
.
8. Measure the gain (G
C
). G
C
should be closer to G
A
than to G
B
.
9. Calculate the error (in relative terms) E
G2
= G
C
/G
A
- 1.
10. Calculate the error (in the number of the first stage gain
codes) C
EG2
= E
G2
/0.00370.
11. Set the first stage gain code to C
G1
- C
EG1
- C
EG2
. The
resulting gain should be within one code of G
A
.
Finally, determine the desired output offset:
1. Determine the desired output offset O
A
(using the
measurements obtained from the simulation).
2. Use Equation 2 to set the output offset code C
O1
such that
the output offset is nominally O
A
.
3. Measure the output offset (O
B
). O
B
should be within
3% of O
A
.
4. Calculate the error (in relative terms) E
O1
= O
B
/O
A
- 1.
5. Calculate the error (in the number of the output offset
codes) C
EO1
= E
O1
/0.00392.
6. Set the output offset code to C
O1
- C
EO1
.
7. Measure the output offset (O
C
). O
C
should be closer to O
A
than to O
B
.
8. Calculate the error (in relative terms) E
O2
= O
C
/O
A
- 1.
9. Calculate the error (in the number of the output offset
codes) C
EO2
= E
O2
/0.00392.
10. Set the output offset code to C
O1
- C
EO1
- C
EO2
. The
resulting offset should be within one code of O
A
.
AD8556
Rev. 0 | Page 24 of 28
EMI/RFI PERFORMANCE
Real world applications must work with ever increasing
radio/magnetic frequency interference (RFI and EMI). In
situations where signal strength is low and transmission lines
are long, instrumentation amplifiers such as AD8556 are
needed to extract weak, small differential signals riding on
common-mode noise and interference. Additionally, wires and
PCB traces act as antennas and pick up high frequency EMI
signals. The longer the wire, the larger the voltage it picks up.
The amount of voltages picked up is dependent on the
impedances at the wires, as well as the EMI frequency. These
high frequency voltages are then passed into the in-amp
through its pins. All instrumentation amplifiers can rectify high
frequency out-of-band signals. Unfortunately, the EMI/RFI
rectification occurs because amplifiers do not have any
significant common-mode rejection above 100 kHz. Once these
high frequency signals are rectified, they appear as dc offset
errors at the output.
AD8556 features internal EMI filters on the VNEG, VPOS,
FILT and VCLAMP pins. These built-in filters on the pins limit
the interference bandwidth, and provide good RFI suppression
without reducing performance within the pass-band of the
in-amp. A functional diagram of AD8556 along with its
EMI/RFI filters is shown in Figure 51.
AD8556 has built-in filters on its inputs, VCLAMP, and filter
pins. The first-order low-pass filters inside the AD8556 are
useful to reject high frequency EMI signals picked up by wires
and PCB traces outside the AD8556. The most sensitive pin of
any amplifier to RFI/EMI signal is the non-inverting pin. Signals
present at this pin appear as common-mode signals and create
problems.
The filters built at the input of the AD8556 have two different
bandwidths: common and differential mode. The common-
mode bandwidth defines what a common-mode RF signal sees
between the two inputs tied together and ground. The EMI
filters placed on the input pins of the AD8556 reject EMI/RFI
suppressions that appear as common-mode signals.
VDD
VSS
05448-053
VDD
VSS
1
2
3
+IN
IN
OUT
A3
VDD
VSS
1
2
3
+IN
IN
OUT
A4
VOUT
VDD
VSS
1
2
3
+IN
IN
OUT
A2
VDD
VSS
1
2
3
+IN
IN
OUT
A1
VSS
1
2
3
+IN
IN
OUT
A5
R7
P4
R5
VDD
DIGIN
VCLAMP
R3
P2
P1
R1
R2
R4
R6
P3
VNEG
VPOS
DAC
LOGIC
EMI
FILTER
EMI
FILTER
EMI
FILTER
RF
EMI
FILTER
FILT/DIGOUT
AD8556
VSS
EMI
FILTER
+IN
IN
Figure 51. Block Diagram Showing EMI/RFI Built-In Filters
AD8556
Rev. 0 | Page 25 of 28
In order to show the benefits that the AD8556 brings to new
applications where EMI/RFI signals are present, a part was
programmed with a gain of 70, dc offset = 2.5 V, to produce
V
OUT
= 0 V. A test circuit like that shown in Figure 52 was used.
Figure 52 simulates the presence of a noisy common-mode
signal, and Figure 53 shows the response dc values at V
OUT
.
AD8556
VDD
VSS
FILT/DIGOUT
DIGIN
VNEG
VPOS
VCLAMP
VOUT
+2.5V
2.5V
U3
VARIABLE
V3
1
2
3
4
0
5
6
7
8
2.5V
VOUT
05448-051
Figure 52. Test Circuit to Show AD8556 Performance
Exposed to Common-Mode RFI/EMI Signals
05448-054
20
0
20
40
60
80
100
0
200
400
600
800
1000
FREQUENCY (MHz)
DE
V
I
ATION FROM DC OUTP
UT (mV
)
NON-EMI PROTECTED SOLUTION
AD8556
Figure 53. DC Offset Values at V
OUT
Caused by Frequency Seep of Input
The differential bandwidth defines the frequency response of
the filters with a differential signal applied between the two
inputs, VPOS (that is, +IN ) and VNEG (that is, IN). Figure 54
shows the circuit used to test for AD8556 EMI/RFI
susceptibility. The part is programmed as stated previously
during the common-mode testing.
AD8556
+2.5V
2.5V
U2
200mV p-p
V2
1
2
3
4
0
5
6
7
8
2.5V
V
OUT
05448-052
0
VDD
VSS
FILT/DIGOUT
DIGIN
VNEG
VPOS
VCLAMP
VOUT
Figure 54. Test Circuit to Show AD8556 Performance Exposed to Differential
Mode RFI/EMI Signals
The response of AD8556 to EMI/RFI differential signals is
shown in Figure 55.
05448-055
1400
1200
1000
800
600
400
200
0
200
400
600
0
200
400
600
800
1000
FREQUENCY (MHz)
D
C
OFFSET (
m
V)
NON-EMI PROTECTED SOLUTION
AD8556
Figure 55. Response of AD8556 to EMI/RFI Differential Signals
To make a board robust against EMI, the leads at VPOS and
VNEG should be as similar as possible. In this way, any EMI
received by the VPOS and VNEG pins will be similar (that is, a
common-mode input), and rejected by the AD8556.
Furthermore, additional filtering at the VPOS and VNEG pins
should give a better reduction of unwanted behavior compared
with filtering at the other pins.
AD8556
Rev. 0 | Page 26 of 28
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 56. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
16
5
13
8
9
12
1
4
1.95 BSC
PIN 1
INDICATOR
TOP
VIEW
4.00
BSC SQ
3.75
BSC SQ
COPLANARITY
0.08
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
12 MAX
1.00
0.85
0.80
SEATING
PLANE
0.30
0.23
0.18
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.20 REF
0.65 BSC
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
0.75
0.60
0.50
0.25 MIN
2.25
2.10 SQ
1.95
Figure 57. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8556ARZ
1
-40C to +140C
8-Lead SOIC_N
R-8
AD8556ARZ-REEL
1
-40C to +140C
8-Lead SOIC_N
R-8
AD8556ARZ-REEL7
1
-40C to +140C
8-Lead SOIC_N
R-8
AD8556ACPZ-R2
1
-40C to +140C
16-Lead LFCSP_VQ
CP-16-4
AD8556ACPZ-REEL
1
-40C to +140C
16-Lead LFCSP_VQ
CP-16-4
AD8556ACPZ-REEL7
1
-40C to +140C
16-Lead LFCSP_VQ
CP-16-4
AD8556ARZ-EVAL
1
Evaluation
Board
1
Z = Pb-free part.
AD8556
Rev. 0 | Page 27 of 28
NOTES
AD8556
Rev. 0 | Page 28 of 28
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0544805/05(0)
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