AD8591/92/94 Data Sheet

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD8591/AD8592/AD8594

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

CMOS Single Supply

Rail-to-Rail Input/Output

Operational Amplifiers with Shutdown

PIN CONFIGURATIONS

6-Lead SOT

(RT Suffix)

OUT A

IN A

AD8591

10-Lead SOIC

(RM Suffix)

SDA

SDB

+IN B

OUT A

IN A

+IN A

V+

OUT B

IN B

AD8592

(Not to Scale)

16-Lead Narrow SOIC

(R Suffix)

TOP VIEW

(Not to Scale)

NC = NO CONNECT

OUT A

IN A

IN B

OUT B

OUT D

IN D

IN C

OUT C

AD8594

16-Lead TSSOP

(RU Suffix)

OUT A

IN A
IN A

IN D
IN D

OUT D

IN B
IN B

OUT B

IN C

OUT C

+IN C

AD8594

NC = NO CONNECT

FEATURES
Single Supply Operation: +2.5 V to +6 V
High Output Current: 250 mA
Extremely Low Shutdown Supply Current: 100 nA
Low Supply Current: 750 A/Amp
Wide Bandwidth: 3 MHz
Slew Rate: 5 V/ s
No Phase Reversal
Very Low Input Bias Current
High Impedance Outputs When in Shutdown Mode
Unity Gain Stable

APPLICATIONS
Mobile Communication Handset Audio
PC Audio
PCMCIA/Modem Line Driving
Battery Powered Instrumentation
Data Acquisition
ASIC Input or Output Amplifier
LCD Display Reference Level Driver

GENERAL DESCRIPTION

The AD8591, AD8592 and AD8594 are single, dual and quad
rail-to-rail input and output single supply amplifiers featuring
250 mA output drive current and a power saving shutdown
mode. The AD8592 includes an independent shutdown func-
tion for each amplifier. When both amplifiers are in shutdown
mode the total supply current is reduced to less than 1

A. The

AD8591 and AD8594 include a single master shutdown func-
tion that reduces total supply current to less than 1

A. All

amplifier outputs are in a high impedance state when in shut-
down mode.

These amplifiers have very low input bias currents, making them
suitable for integrators and diode amplification. Outputs are
stable with virtually any capacitive load. Supply current is less
than 750

A per amplifier in active mode.

Applications for these amplifiers include audio amplification for
portable computers, portable phone headsets, sound ports, sound
cards and set-top boxes. The AD859x family is capable of driving
heavy capacitive loads such as LCD panel reference levels.

The ability to swing rail-to-rail at both the input and output
enables designers to buffer CMOS DACs, ASICs and other
wide output swing devices in single supply systems.

The AD8591, AD8592 and AD8594 are specified over the indus-
trial (40

C to +85

C) temperature range. The AD8591, single,

is available in the tiny 6-lead SOT package. The AD8592, dual, is
available in the 10-lead

SOIC surface mount package. The

AD8594, quad, is available in 16-lead narrow SOIC and 16-lead
TSSOP packages.

REV. A

AD8591/AD8592/AD8594SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

C < T

< +85

Input Bias Current

C < T

< +85

Input Offset Current

C < T

< +85

Input Voltage Range

+2.7

Common-Mode Rejection Ratio

CMRR

= 0 V to +2.7 V

Large Signal Voltage Gain

= 2 k

, V

= +0.3 V to +2.4 V

V/mV

Offset Voltage Drift

Bias Current Drift

fA/

Offset Current Drift

fA/

OUTPUT CHARACTERISTICS

Output Voltage High

= 10 mA

+2.55

+2.61

C to +85

+2.5

Output Voltage Low

= 10 mA

100

C to +85

125

Output Current

OUT

250

Open-Loop Impedance

OUT

f = 1 MHz, A

= 1

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

= +2.5 V to +6 V

Supply Current/Amplifier

= 0 V

C < T

< +85

1.25

Supply Current Shutdown Mode

All Amplifiers Shut Down

0.1

C < T

< +85

SD1

Amplifier 1 Shut Down (AD8592)

1.4

SD2

Amplifier 2 Shut Down (AD8592)

1.4

SHUTDOWN INPUTS

Logic High Voltage

INH

C < T

< +85

+1.6

Logic Low Voltage

INL

C < T

< +85

+0.5

Logic Input Current

C < T

< +85

DYNAMIC PERFORMANCE

Slew Rate

= 2 k

3.5

Settling Time

To 0.01%

1.4

Gain Bandwidth Product

GBP

2.2

MHz

Phase Margin

Degrees

Channel Separation

f = 1 kHz, R

= 2 k

NOISE PERFORMANCE

Voltage Noise Density

f = 1 kHz

nV/

f = 10 kHz

nV/

Current Noise Density

f = 1 kHz

0.05

pA/

Specifications subject to change without notice.

= +2.7 V, V

= +1.35 V, T

= +25 C unless otherwise noted)

REV. A

AD8591/AD8592/AD8594

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

INPUT CHARACTERISTICS

Offset Voltage

C < T

< +85

Input Bias Current

C < T

< +85

Input Offset Current

C < T

< +85

Input Voltage Range

Common-Mode Rejection Ratio

CMRR

= 0 V to +5 V

Large Signal Voltage Gain

= 2 k

, V

= +0.5 V to +4.5 V

V/mV

Offset Voltage Drift

C < T

< +85

Bias Current Drift

fA/

Offset Current Drift

fA/

OUTPUT CHARACTERISTICS

Output Voltage High

= 10 mA

+4.9

+4.94

C to +85

+4.85

Output Voltage Low

= 10 mA

100

C to +85

125

Output Current

OUT

250

Open-Loop Impedance

OUT

f = 1 MHz, A

= 1

POWER SUPPLY

Power Supply Rejection Ratio

PSRR

= +2.5 V to +6 V

Supply Current/Amplifier

= 0 V

1.25

C < T

< +85

1.75

Supply Current-Shutdown Mode

All Amplifiers Shut Down

0.1

C < T

< +85

SD1

Amplifier 1 Shut Down (AD8592)

1.6

SD2

Amplifier 2 Shut Down (AD8592)

1.6

SHUTDOWN INPUTS

Logic High Voltage

INH

C < T

< +85

+2.4

Logic Low Voltage

INL

C < T

< +85

+0.8

Logic Input Current

C < T

< +85

DYNAMIC PERFORMANCE

Slew Rate

= 2 k

Full-Power Bandwidth

1% Distortion

325

kHz

Settling Time

To 0.01%

1.6

Gain Bandwidth Product

GBP

MHz

Phase Margin

Degrees

Channel Separation

f = 1 kHz, R

= 10 k

NOISE PERFORMANCE

Voltage Noise Density

f = 1 kHz

nV/

f = 10 kHz

nV/

Current Noise Density

f = 1 kHz

0.05

pA/

Specifications subject to change without notice.

= +5.0 V, V

= +2.5 V, T

= +25 C unless otherwise noted)

AD8591/AD8592/AD8594

REV. A

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8591/AD8592/AD8594 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .

6 V

Output Short Circuit

Duration to GND

. . . . . . . . . . . . Observe Derating Curves

Storage Temperature Range

R, RT, RM, RU Packages . . . . . . . . . . . . 65

C to +150

Operating Temperature Range

AD8591/AD8592/AD8594 . . . . . . . . . . . . 40

C to +85

Junction Temperature Range

R, RT, RM, RU Packages . . . . . . . . . . . . 65

C to +150

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

For supplies less than

5 V the differential input voltage is limited to the supplies.

Package Type

Units

6-Lead SOT-23 (RT)

230

C/W

10-Lead

SOIC (RM)

200

C/W

16-Lead SOIC (R)

120

C/W

16-Lead TSSOP (RU)

180

C/W

NOTE

is specified for worst case conditions, i.e.,

is specified for device in socket

for surface mount packages.

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD8591ART

C to +85

6-Lead SOT-23

RT-6

AD8592ARM 40

C to +85

10-Lead

SOIC

RM-10

AD8594AR

C to +85

16-Lead SOIC

R-16A

AD8594ARU 40

C to +85

16-Lead TSSOP

RU-16

WARNING!

ESD SENSITIVE DEVICE

LOAD CURRENT mA

0.1

0.01

OUTPUT VOLTAGE mV

0.1

100

SOURCE

SINK

= +2.7V

= +25 C

100

Figure 1. Output Voltage to Supply
Rail vs. Load Current

LOAD CURRENT mA

0.1

0.01

OUTPUT VOLTAGE mV

0.1

100

10k

SOURCE

SINK

= +5V

= +25 C

100

Figure 2. Output Voltage to Supply
Rail vs. Load Current

TEMPERATURE C

100

SUPPLY CURRENT/AMPLIFIER mA

0.90

0.50

0.85

0.70

0.65

0.60

0.55

0.80

0.75

= +5V

= +2.7V

Figure 3. Supply Current per
Amplifier vs. Temperature

Typical Performance Characteristics

REV. A

AD8591/AD8592/AD8594

SUPPLY VOLTAGE Volts

SUPPLY CURRENT/AMPLIFIER mA

0.8

0.7

0.75

1.25

1.75

2.25

2.75

0.4

0.3

0.2

0.1

0.6

0.5

= +25 C

Figure 4. Supply Current per
Amplifier vs. Supply Voltage

TEMPERATURE C

INPUT OFFSET VOLTAGE mV

= +5V

= +2.5V

Figure 5. Input Offset Voltage vs.
Temperature

TEMPERATURE C

INPUT BIAS CURRENT pA

= +2.7V, +5V

= V

Figure 6. Input Bias Current vs.
Temperature

TEMPERATURE C

INPUT OFFSET CURRENT pA

= +2.7V, +5V

= V

/ 2

Figure 7. Input Offset Current vs.
Temperature

COMMON-MODE VOLTAGE Volts

INPUT BIAS CURRENT pA

= +5V

= +25 C

Figure 8. Input Bias Current vs.
Common-Mode Voltage

FREQUENCY Hz

GAIN dB

10k

100M

100k

10M

135

180

PHASE SHIFT Degrees

= +2.7V

= NO LOAD

= +25 C

Figure 9. Open-Loop Gain and Phase
vs. Frequency

FREQUENCY Hz

GAIN dB

10k

100M

100k

10M

135

180

PHASE SHIFT De

rees

= +5V

= NO LOAD

= +25 C

Figure 10. Open-Loop Gain and
Phase vs. Frequency

FREQUENCY Hz

OUTPUT SWING V p-p

10k

10M

100k

= +2.7V

= 2k

= +25 C

= 2.5V p-p

Figure 11. Closed-Loop Output
Voltage Swing vs. Frequency

FREQUENCY Hz

OUTPUT SWING V p-p

10k

10M

100k

= +5V

= 2k

= +25 C

= 4.9V p-p

Figure 12. Closed-Loop Output
Voltage Swing vs. Frequency

AD8591/AD8592/AD8594

REV. A

FREQUENCY Hz

IMPEDANCE 

10k

100M

100k

10M

= +5V

= +25 C

100

120

140

160

180

200

= 10

= 1

Figure 13. Closed-Loop Output
Impedance vs. Frequency

FREQUENCY Hz

CMRR dB

110

10k

10M

100k

= +5V

= +25 C

100

Figure 14. Common-Mode Rejection
Ratio vs. Frequency

FREQUENCY Hz

PSRR dB

10k

100k

10M

= +2.5V

= +25 C

100

120

140

+PSRR

PSRR

Figure 15. Power Supply Rejection
Ratio vs. Frequency

FREQUENCY Hz

PSRR dB

10k

100k

10M

= +5V

= +25 C

100

120

140

+PSRR

PSRR

Figure 16. Power Supply Rejection
Ratio vs. Frequency

CAPACITANCE pF

SMALL SIGNAL OVERSHOOT %

100

10k

= +2.5V

= 2k

= +25 C

+OS

Figure 17. Small Signal Overshoot
vs. Load Capacitance

CAPACITANCE pF

SMALL SIGNAL OVERSHOOT %

100

10k

= +5V

= 2k

= +25 C

+OS

Figure 18. Small Signal Overshoot
vs. Load Capacitance

500 ns/DIV

20mV/DIV

= 1.35V

= 50mV

= 1

= 2k

= 300pF

= +25 C

Figure 19. Small Signal Transient
Response

500 ns/DIV

20mV/DIV

= 2.5V

= 50mV

= 1

= 2k

= 300pF

= +25 C

Figure 20. Small Signal Transient
Response

500ns

500mV

100

= 1.35V

= 1

= 2k

= +25 C

Figure 21. Large Signal Transient
Response

AD8591/AD8592/AD8594

REV. A

500ns

500mV

100

= 2.5V

= 1

= 2k

= +25 C

Figure 22. Large Signal Transient
Response

10 s

100

= 2.5V

= 1

= +25 C

Figure 23. No Phase Reversal

FREQUENCY Hz

CURRENT NOISE DENSITY pA/

0.1

0.01

100

100k

10k

= +5V

= +25 C

Figure 24. Current Noise Density vs.
Frequency

100

= +5V

= 1000

= +25 C

FREQUENCY = 1kHz

100

V/DIV

MARKER 41 V/

Figure 25. Voltage Noise Density vs.
Frequency

100

= +5V

= 1000

= +25 C

FREQUENCY = 10kHz

MARKER 25.9 V/

200

V/DIV

Figure 26. Voltage Noise Density vs.
Frequency

INPUT OFFSET VOLTAGE mV

QUANTITY Amplifiers

300

500

400

200

100

12 10 8

= +2.7V

= +1.35V

= +25 C

Figure 27. Input Offset Voltage
Distribution

INPUT OFFSET VOLTAGE mV

QUANTITY Amplifiers

300

12 10 8

500

400

200

100

= +5V

= +2.5V

= +25 C

Figure 28. Input Offset Voltage
Distribution

AD8591/AD8592/AD8594

REV. A

AD8591/AD8592/AD8594 APPLICATION SECTION
Theory of Operation

The AD859x family of amplifiers are all CMOS, high output drive,
rail-to-rail input and output single supply amplifiers designed for
low cost and high output current drive. The parts include a power
saving shutdown function making the AD8591/AD8592/AD8594
op amps ideal for portable multimedia and telecom applications.

Figure 29 shows the simplified schematic for an AD8591/AD8592/
AD8594 amplifier. Two input differential pairs, consisting of an
n-channel pair (M1-M2) and a p-channel pair (M3-M4), provide
a rail-to-rail input common-mode range. The outputs of the input
differential pairs are combined in a compound folded-cascode
stage, which drives the input to a second differential pair gain
stage. The outputs of the second gain stage provide the gate volt-
age drive to the rail-to-rail output stage.

The rail-to-rail output stage consists of M15 and M16, which are
configured in a complementary common-source configuration.
As with any rail-to-rail output amplifier, the gain of the output
stage, and thus the open-loop gain of the amplifier, is dependent
on the load resistance. Also, the maximum output voltage swing
is directly proportional to the load current. The difference be-
tween the maximum output voltage to the supply rails, known as
the dropout voltage, is determined by the AD8591/AD8592/
AD8594 output transistors' on-channel resistance. The output
dropout voltage is given in Figure 1 and Figure 2.

50 A

100 A

20 A

M12

M15

M16

M11

OUT

IN

IN+

M10

20 A

M13

50 A

V+

M14

M337

INV

M340

*NOTE: ALL CURRENT SOURCES GO
TO 0 A IN SHUTDOWN MODE

INV

M31

M30

Figure 29. AD8591/AD8592/AD8594 Simplified Schematic

Input Voltage Protection
Although not shown on the simplified schematic, ESD protec-
tion diodes are connected from each input to each power supply
rail. These diodes are normally reverse biased, but will turn on
if either input voltage exceeds either supply rail by more than
+0.6 V. Should this condition occur, the input current should
be limited to less than

5 mA. This can be done by placing a

resistor in series with the input(s). The minimum resistor value
should be:

IN MAX

(1)

Output Phase Reversal

The AD8591/AD8592/AD8594 are immune to output voltage
phase reversal with an input voltage within the supply voltages
of the device. However, if either of the device's inputs exceeds
+0.6 V outside of the supply rails, the output could exhibit
phase reversal. This is due to the ESD protection diodes be-
coming forward biased, thus causing the polarity of the input
terminals of the device to switch.

The technique recommended in the Input Overvoltage Protection
section should be applied in applications where the possibility of
input voltages exceeding the supply voltages exists.

Output Short Circuit Protection

To achieve high output current drive and rail-to-rail performance,
the outputs of the AD859x family do not have internal short cir-
cuit protection circuitry. Although these amplifiers are designed to
sink or source as much as 250 mA of output current, shorting the
output directly to the positive supply could damage or destroy the
device. To protect the output stage, the maximum output current
should be limited to

250 mA.

By placing a resistor in series with the output of the amplifier as
shown in Figure 30, the output current can be limited. The
minimum value for R

can be found from Equation 2.

250

(2)

For a +5 V single supply application, R

should be at least 20

Because R

is inside the feedback loop, V

OUT

is not affected. The

tradeoff in using R

is a slight reduction in output voltage swing

under heavy output current loads. R

will also increase the effec-

tive output impedance of the amplifier to R

+ R

, where R

the output impedance of the device.

+5V

OUT

AD8592

Figure 30. Output Short Circuit Protection

Power Dissipation

Although the AD859x family of amplifiers are able to provide
load currents of up to 250 mA, proper attention should be
given to not exceeding the maximum junction temperature for
the device. The equation for finding the junction temperature is
given as:

DISS

(3)

Where

= AD859x junction temperature

DISS

= AD859x power dissipation

= AD859x junction-to-ambient thermal resistance

of the package; and
T

= The ambient temperature of the circuit

AD8591/AD8592/AD8594

REV. A

In any application, the absolute maximum junction temperature
must be limited to +150

C. If this junction temperature is ex-

ceeded, the device could suffer premature failure. If the output
voltage and output current are in phase, for example, with a
purely resistive load, the power dissipated by the AD859x can
be found as:

ISS

OUT

LOAD

(

)

(4)

Where

LOAD

= AD859x output load current

= AD859x supply voltage; and

OUT

= The output voltage

By calculating the power dissipation of the device and using the
thermal resistance value for a given package type, the maximum
allowable ambient temperature for an application can be found
using Equation 3.

Capacitive Loading

The AD859x exhibits excellent capacitive load driving capabilities
and can drive up to 10 nF directly. Although the device is stable
with large capacitive loads, there is a decrease in amplifier band-
width as the capacitive load increases. Figure 31 shows a graph of
the AD8592 unity gain bandwidth under various capacitive loads.

CAPACITIVE LOAD nF

3.5

0.01

100

0.1

BANDWIDTH MHz

1.5

0.5

2.5

= 2.5V

= 1k

= +25 C

Figure 31. Unity Gain Bandwidth vs. Capacitive Load

When driving heavy capacitive loads directly from the AD859x
output, a snubber network can be used to improve transient
response. This network consists of a series R-C connected from
the amplifier's output to ground, placing it in parallel with the
capacitive load. The configuration is shown in Figure 32. Al-
though this network will not increase the bandwidth of the am-
plifier, it will significantly reduce the amount of overshoot, as
shown in Figure 33.

+5V

OUT

100mV p-p

AD8592

47nF

1 F

Figure 32. Configuration for Snubber Network to
Compensate for Capacitive Loads

10 s

50mV

100

50mV

47nF LOAD

ONLY

SNUBBER

IN CIRCUIT

Figure 33. Snubber Network Reduces Overshoot and
Ringing Caused from Driving Heavy Capacitive Loads

The optimum values for the snubber network should be determined
empirically based on the size of the capacitive load. Table I shows a
few sample snubber network values for a given load capacitance.

Table I. Snubber Networks for Large Capacitive Loads

Load Capacitance

Snubber Network

)

, C

)

0.47 nF

300

, 0.1

4.7 nF

, 1

47 nF

, 1

A PC-98 Compliant Headphone/Speaker Amplifier

Because of its high output current performance and shutdown
feature, the AD8592 makes an excellent amplifier for driving an
audio output jack in a computer application. Figure 34 shows
how the AD8592 can be interfaced with an AC97 codec to drive
headphones or speakers.

U1-A

100 F

+5V

LEFT

OUT

AD1881

(AC97)

RIGHT

OUT

+5V

100k

100 F

NOTE: ADDITIONAL PINS
OMITTED FOR CLARITY

U1-B

U1 = AD8592

Figure 34. A PC-98 Compliant Headphone/Line Out Amplifier

When headphones are plugged into the jack, the normalizing con-
tacts disconnect from the audio contacts. This allows the voltage to
the AD8592 shutdown pins to be pulled up to +5 V, activating the
amplifiers. With no plug in the output jack, the shutdown voltage is
pulled to 100 mV through the R1 and R3 + R5 voltage divider.
This powers the AD8592 down when it is not needed, saving
current from the power supply or battery.

AD8591/AD8592/AD8594

REV. A

If gain is required from the output amplifier, four additional
resistors should be added as shown in Figure 35. The gain of
the AD8592 can be set as:

(5)

U1-A

100 F

+5V

LEFT

OUT

AD1881

(AC97)

RIGHT

OUT

+5V

100k

100 F

NOTE: ADDITIONAL PINS
OMITTED FOR CLARITY

U1-B

U1 = AD8592

20k

REF

10k

= +6dB WITH VALUES SHOWN

Figure 35. A PC-98 Compliant Headphone/Line Out
Amplifier With Gain

Input coupling capacitors are not required for either circuit as
the reference voltage is supplied from the AD1881.

R4 and R5 help protect the AD8592 output in case the output
jack or headphone wires accidentally get shorted to ground.
The output coupling capacitors C1 and C2 block dc current
from the headphones and create a high-pass filter with a corner
frequency of:

(

)

(6)

Where R

is the resistance of the headphones.

A Combined Microphone and Speaker Amplifier for
Cellphone and Portable Headsets

The dual amplifiers in the AD8592 make an efficient design for
interfacing with a headset containing a microphone and speaker.
Figure 36 demonstrates a simple method for constructing an
interface to a codec.

U1-A

+5V

10 F

U1 = AD8592

10k

U1-B

10k

(OPTIONAL)

10k

FROM CODEC
MONO OUT
(OR LEFT OUT)

TO
CODEC

100k

REF

FROM CODEC

MIC + SPEAKER

JACK

2.2k

+5V

10k

100k

+5V

0.1 F

(RIGHT OUT)

Figure 36. A Speaker/Mic Headset Amplifier Circuit

U1-A is used as a microphone preamplifier, where the gain of
the preamplifier is set as R3/R2. R1 is used to bias an electret
microphone and C1 blocks any dc voltages from the amplifier.
U1-B is the speaker amplifier, and its gain is set at R5/R4. To
sum a stereo output, R6 should be added, equal in value to R4.

Using the same principle as described in the previous section,
the normalizing contact on the microphone/speaker jack can be
used to put the AD8592 into shutdown when the headset is not
plugged in. The AD8592 shutdown inputs can also be con-
trolled with TTL or CMOS compatible logic, allowing micro-
phone or speaker muting if desired.

An Inexpensive Sample-and-Hold Circuit

The independent shutdown control of each amplifier in the
AD8592 allows a degree of flexibility in circuit design. One par-
ticular application for which this feature is useful is in designing a
sample-and-hold circuit for data acquisition. Figure 37 shows a
schematic of a simple, yet extremely effective sample-and-hold
circuit using a single AD8592 and one capacitor.

U1-A

C1
1nF

U1-B

SAMPLE
AND HOLD
OUTPUT

+5V

SAMPLE

CLOCK

U1 = AD8592

+5V

Figure 37. An Efficient Sample-and-Hold Circuit

AD8591/AD8592/AD8594

REV. A

The U1-A amplifier is configured as a unity gain buffer driving a
1 nF capacitor. The input signal is connected to the noninverting
input, while the sample clock controls the shutdown for that
amplifier. When the sample clock is high, the U1-A amplifier is
active and the output follows V

. Once the sample clock goes

low, U1-A shuts down with the output of the amplifier going to
a high impedance state, holding the voltage on the C1 capacitor.

The U1-B amplifier is used as a unity gain buffer to prevent load-
ing on C1. Because of the low input bias current of the U1-B
CMOS input stage and the high impedance state of the U1-A
output in shutdown, there is very little voltage droop from C1
during the Hold period. This circuit can be used with sample
frequencies as high as 500 kHz and as low as below 1 Hz. Even
lower voltage droop can be achieved for very low sample rates
by increasing the value of C1.

Direct Access Arrangement for PCMCIA Modems
(Telephone Line Interface)

Figure 38 illustrates a +5 V transmit/receive telephone line
interface for 600

systems. It allows full duplex transmission of

signals on a transformer-coupled 600

line in a differential

manner. Amplifier A1 provides gain that can be adjusted to
meet the modem output drive requirements. Both A1 and A2
are configured to apply the largest possible signal on a single
supply to the transformer. Because of the AD8594's high output
current drive and low dropout voltages, the largest signal avail-
able on a single +5 V supply is approximately 4.5 V p-p into a
600

transmission system. Amplifier A3 is configured as a

difference amplifier for two reasons: (1) It prevents the transmit
signal from interfering with the receive signal and (2) it extracts
the receive signal from the transmission line for amplification by
A4. Amplifier A4's gain can be adjusted in the same manner as
A1's to meet the modem's input signal requirements. Standard
resistor values permit the use of SIP (Single In-line Package)
format resistor arrays. Couple this with the AD8594 16-lead
TSSOP or SOIC footprint, and this circuit offers a compact,
cost effective solution.

R7
10k

R8
10k

+5V

6.2V

TRANSMIT

TxA

RECEIVE

RxA

0.1 F

10k

9.09k

Tx GAIN
ADJUST

A1, A2 = 1/2 AD8592
A3, A4 = 1/2 AD8592

360

1:1

TO TELEPHONE

LINE

10 F

10k

R14

14.3k

R10

10k

R11

10k

R12

10k

R13

10k

0.1 F

Rx GAIN
ADJUST

600

MIDCOM
671-8005

SHUTDOWN

Figure 38. A Single Supply Direct Access Arrangement for
PCMCIA Modems

Single Supply Differential Line Driver

Figure 39 shows a single supply differential line driver circuit that
can drive a 600

load with less than 0.7% distortion from 20 Hz

to 15 kHz with an input signal of 4 V p-p and a single +5 V supply.
The design uses an AD8594 to mimic the performance of a fully
balanced transformer based solution. However, this design occu-
pies much less board space while maintaining low distortion and
can operate down to dc. Like the transformer based design, either
output can be shorted to ground for unbalanced line driver applica-
tions without changing the circuit gain of 1.

600

22 F

+5V

10k

R11
10k

R7
10k

+5V

R8
100k

100k

1 F

R12

10k

R14

10k

R13

10k

47 F

A1, A2 = 1/2 AD8592

GAIN = R3

SET: R7, R10, R11 = R2

SET: R6, R12, R13 = R3

R10

10k

Figure 39. A Low Noise, Single Supply Differential
Line Driver

R8 and R9 set up the common-mode output voltage equal to
half of the supply voltage. C1 is used to couple the input signal
and can be omitted if the input's dc voltage is equal to half of
the supply voltage.

The circuit can also be configured to provide additional gain if
desired. The gain of the circuit is:

OUT

(7)

Where:

OUT

= V

R2 = R7 = R10 = R11 and,
R3 = R6 = R12 = R13

AD8591/AD8592/AD8594

REV. A

SPICE Model for the AD8591/AD8592/AD8594 Amplifier

The SPICE model for the AD8591/AD8592/AD8594 amplifier is
one of the more realistic computer simulation macro-models
available, providing a high degree of realism with respect to char-
acteristics of the actual amplifier. This model, shown in Listing 1,
is based on typical values for the device and can be downloaded
from Analog Devices' Internet site at www.analog.com.

The model uses a common source output stage to provide rail-
to-rail performance. This allows realistic simulation of open-
loop gain dependency on load resistance as well as maximum
output voltage versus output current. Two differential pairs are
used in the input stage of the model, simulating the rail-to-rail
input stage of the AD8591/AD8592/AD8594 amplifier.

The EOS voltage source establishes the input offset voltage and
is also used to simulate the common-mode rejection power
supply rejection, and input voltage noise characteristics for the
model. In addition, G2, R2 and CF are used to help set the
open-loop gain and gain-bandwidth product of the model.

A number of secondary characteristics are also accurately por-
trayed in the SPICE model. Flicker noise is accurately modeled
with the 1/f corner frequency set through the KF and AF terms
in the input stage transistors. C1 and C2 are used in the input
section to create secondary poles to achieve an accurate phase
margin characteristic for the model.

The AD8591/AD8592/AD8594 shutdown circuitry is included
in the model. Switches S1 through S7 deactivate the op amp
circuitry in shutdown mode. The logic threshold for the shut-
down circuitry is accurately modeled through the VSWITCH
model parameters near the end of the listing. The active supply
current versus supply voltage is also modeled through the volt-
age-controlled current source GSY.

Characteristics of this model are based on typical values for the
AD8591/AD8592/AD8594 amplifier at +27

C. The model's

characteristics are optimized specifically at +27

C, and may lose

accuracy at different simulation temperatures.

AD8591/AD8592/AD8594

REV. A

Listing 1: AD859x SPICE Macro-Model

* AD8592 SPICE Macro-Model Typical Values
* 9/98, Ver. 1
* TAM / ADSC
*
* Copyright 1998 by Analog Devices
*
* Refer to "README.DOC" file for License
* Statement. Use of this
* model indicates your acceptance of the
* terms and provisions in
* the License Statement.
*
* Node Assignments
*

noninverting input

inverting input

positive supply

negative supply

output

shutdown

.SUBCKT AD8592

*
* INPUT STAGE
*
M1 4 1 3 3 PIX L=0.8E-6 W=125E-6
M2 6 7 3 3 PIX L=0.8E-6 W=125E-6
RC1 4 50 4E3
RC2 6 50 4E3
C1 4 6 2E-12
I1 99 8 100E-6

M3 10 1 12 12 NIX L=0.8E-6 W=125E-6
M4 11 7 12 12 NIX L=0.8E-6 W=125E-6
RC3 10 99 4E3
RC4 11 99 4E3
C2 10 11 2E-12
I2 13 50 100E-6

EOS 7 2 POLY(3) (21,98) (73,98) (61,0)
+1E-3 1 1 1
IOS 1 2 2.5E-12
V1 99 9 0.9
D1 3 9 DX
V2 14 50 0.9
D2 14 12 DX
S1 3 8 (82,98) SOPEN
S2 99 8 (98,82) SCLOSE
S3 12 13 (82,98) SOPEN
S4 13 50 (98,82) SCLOSE
*
* CMRR=64dB, ZERO AT 20kHz
*
ECM1 20 98 POLY(2) (1,98) (2,98) 0 .5 .5
RCM1 20 21 79.6E3
CCM1 20 21 100E-12
RCM2 21 98 50
*
* PSRR=80dB, ZERO AT 200Hz
*
RPS1 70 0 1E6
RPS2 71 0 1E6
CPS1 99 70 1E-5

AD8591/AD8592/AD8594

REV. A

CPS2 50 71 1E-5
EPSY 98 72 POLY(2) (70,0) (0,71) 0 1 1
RPS3 72 73 1.59E6
CPS3 72 73 500E-12
RPS4 73 98 80
*
* INTERNAL VOLTAGE REFERENCE
*
EREF 98 0 POLY(2) (99,0) (50,0) 0 .5 .5
GSY 99 50 POLY(1) (99,50) 20E-6 10E-7
*
* SHUTDOWN SECTION
*
E1 81 98 (80,50) 1
R1 81 82 1E3
C3 82 98 1E-9
*
* VOLTAGE NOISE REFERENCE OF 30nV/rt(Hz)
*
VN1 60 0 0
RN1 60 0 16.45E-3
HN 61 0 VN1 30
RN2 61 0 1
*
* GAIN STAGE
*
G2 98 30 POLY(2) (4,6) (10,11) 0 2.19E-5 +2.19E-5
R2 30 98 13E6
CF 45 30 5E-12
S5 30 98 (98,82) SCLOSE
D3 30 31 DX
D4 32 30 DX
V3 99 31 0.6
V4 32 50 0.6
*
* OUTPUT STAGE
*
M5 45 46 99 99 POX L=0.8E-6 W=16E-3
M6 45 47 50 50 NOX L=0.8E-6 W=16E-3
EG1 99 48 POLY(1) (98,30) 1.06 1
EG2 49 50 POLY(1) (30,98) 1.05 1
RG1 48 46 10E3
RG2 49 47 10E3
S6 46 99 (98,82) SCLOSE
S7 47 50 (98,82) SCLOSE
*
* MODELS
*
.MODEL PIX PMOS (LEVEL=2,KP=20E-6,VTO=-0.7, LAMBDA=0.01,AF=1,KF=1E-31)
.MODEL NIX NMOS (LEVEL=2,KP=20E-6,VTO=0.7, LAMBDA=0.01,AF=1,KF=1E-31)
.MODEL POX PMOS (LEVEL=2,KP=8E-6,VTO=-1, LAMBDA=0.067)
.MODEL NOX NMOS (LEVEL=2,KP=13.4E-6,VTO=1, LAMBDA=0.067)
.MODEL SOPEN VSWITCH(VON=2.4,VOFF=0.8, RON=10,ROFF=1E9)
.MODEL SCLOSE VSWITCH(VON=-0.8,VOFF=-2.4, RON=10,ROFF=1E9)
.MODEL DX D(IS=1E-14)
.ENDS AD8592

AD8591/AD8592/AD8594

REV. A

0.199 (5.05)
0.187 (4.75)

PIN 1

0.0197 (0.50) BSC

0.124 (3.15)
0.112 (2.84)

0.122 (3.10)
0.110 (2.79)

SEATING
PLANE

0.006 (0.15)
0.002 (0.05)

0.016 (0.41)
0.006 (0.15)

0.038 (0.97)
0.030 (0.76)

0.043 (1.09)
0.037 (0.94)

0.011 (0.28)
0.003 (0.08)

0.022 (0.56)
0.021 (0.53)

0.120 (3.05)
0.112 (2.84)

6
0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

6-Lead SOT

(RT-6)

0.122 (3.10)
0.106 (2.70)

PIN 1

0.118 (3.00)
0.098 (2.50)

0.075 (1.90)

BSC

0.037 (0.95) BSC

0.071 (1.80)
0.059 (1.50)

0.009 (0.23)
0.003 (0.08)

0.022 (0.55)
0.014 (0.35)

0.020 (0.50)
0.010 (0.25)

0.059 (0.15)
0.000 (0.00)

0.051 (1.30)
0.035 (0.90)

SEATING
PLANE

0.057 (1.45)
0.035 (0.90)

16-Lead Thin Shrink Small Outline

(RU-16)

0.177 (4.50)

0.169 (4.30)

0.201 (5.10)
0.193 (4.90)

0.256 (6.50)

0.246 (6.25)

PIN 1

SEATING

PLANE

0.006 (0.15)
0.002 (0.05)

0.0118 (0.30)
0.0075 (0.19)

0.0256

(0.65)

BSC

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)
0.020 (0.50)

8
0

10-Lead SOIC

(RM-10)

16-Lead Narrow Body SO

(R-16A)

0.3937 (10.00)

0.3859 (9.80)

0.2440 (6.20)

0.2284 (5.80)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0688 (1.75)

0.0532 (1.35)

0.0500

(1.27)

BSC

0.0099 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

C3456a02/99

PRINTED IN U.S.A.

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