Low Noise,
Precision CMOS Amplifier
AD8655
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low noise: 2.7 nV/
Hz @ f = 10 kHz
Low offset voltage: 250 V max over V
B
CM
B
Offset voltage drift: 0.4 V/C typ and 2.3 V/C max
Bandwidth: 28 MHz
Rail-to-rail input/output
Unity gain stable
2.7 V to 5.5 V operation
-40C to +125C operation
APPLICATIONS
ADC and DAC buffers
Audio
Industrial controls
Precision filters
Digital scales
Strain gauges
PLL filters
PIN CONFIGURATIONS
NC
1
IN
2
+IN
3
V
4
NC
8
V+
7
OUT
6
NC
5
AD8655
TOP VIEW
(Not to Scale)
05304-048
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM-8)
NC
1
IN
2
+IN
3
V
4
NC
8
V+
7
OUT
6
NC
5
NC = NO CONNECT
AD8655
TOP VIEW
(Not to Scale)
05304-049
Figure 2. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The AD8655 is the industry's lowest noise, precision CMOS
amplifier. It leverages the Analog Devices DigiTrim technology
to achieve high dc accuracy.
The AD8655 provides low noise (2.7 nV/Hz @ 10 kHz), low
THD + N (0.0007%), and high precision performance (250 V
max over V
B
CM
B
) to low voltage applications. The ability to swing
rail-to-rail at the input and output enables designers to buffer
ADCs and other wide dynamic range devices in single-supply
systems.
The AD8655 high precision performance improves the
resolution and dynamic range in low voltage applications.
Audio applications, such as microphone pre-amps and audio
mixing consoles, benefit from the low noise, low distortion, and
high output current capability of the AD8655 to reduce system
level noise performance and maintain audio fidelity. The
AD8655's high precision and rail-to-rail input and output
benefit data acquisition, process controls, and PLL filter
applications.
The AD8655 is fully specified over the -40C to +125C
temperature range. The AD8655 is available in 8-lead MSOP
and SOIC packages.
AD8655
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
5.0 V Electrical Specifications......................................................... 3
2.7 V Electrical Specifications......................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 14
Applications..................................................................................... 15
Input Overvoltage Protection ................................................... 15
Input Capacitance ...................................................................... 15
Driving Capacitive Loads.......................................................... 15
Layout, Grounding, and Bypassing Considerations .................. 17
Power Supply Bypassing ............................................................ 17
Grounding ................................................................................... 17
Leakage Currents........................................................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
4/05--Revision 0: Initial Version
AD8655
Rev. 0 | Page 3 of 20
5.0 V ELECTRICAL SPECIFICATIONS
V
B
S
B
= 5.0 V, V
B
CM
B
= V
B
S
B
/2, T
B
A
B
= 25C, unless otherwise specified.
Table 1.
Parameter Symbol
Conditions Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
B
OS
B
V
B
CM
B
= 0 V to 5 V
50
250
V
-40C T
B
A
B
+125C
550
V
Offset Voltage Drift
V
B
OS
B
/
T
-40C T
B
A
B
+125C
0.4
2.3
V/C
Input Bias Current
I
B
B
B
1
10
pA
-40C T
B
A
B
+125C
300
pA
Input Offset Current
I
B
OS
B
10
pA
-40C T
B
A
B
+125C
300
pA
Input Voltage Range
0
5
V
Common-Mode Rejection Ratio
CMRR
V
B
CM
B
= 0 V to 5 V
85
100
dB
Large Signal Voltage Gain
A
B
VO
B
V
B
O
B
= 0.2 V to 4.8 V, R
B
L
B
= 10 k, V
B
CM
B
= 0 V
100
110
dB
-40C T
B
A
B
+125C
95
dB
OUTPUT CHARACTERISTICS
Output Voltage High
V
B
OH
B
I
B
L
B
= 1 mA; -40C T
B
A
B
+125C
4.97
4.991
V
Output Voltage Low
V
B
OL
B
I
B
L
B
= 1 mA; -40C T
B
A
B
+125C
8
30
mV
Output Current
I
B
OUT
B
V
B
OUT
B
= 0.5 V
220
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
B
S
B
= 2.7 V to 5.0 V
88
105
dB
Supply Current/Amplifier
I
B
SY
B
V
B
O
B
= 0 V
3.7
4.5
mA
-40C T
B
A
B
+125C
5.3
mA
INPUT CAPACITANCE
C
B
IN
B
Differential
9.3
pF
Common-Mode
16.7
pF
NOISE PERFORMANCE
Input Voltage Noise Density
e
B
n
B
f = 1 kHz
4
nV/
Hz
f = 10 kHz
2.7
nV/
Hz
Total Harmonic Distortion + Noise
THD + N
G = 1, R
B
L
B
= 1 k, f = 1 kHz, V
B
IN
B
= 2 V p-p
0.0007
%
FREQUENCY RESPONSE
Gain Bandwidth Product
GBP
28
MHz
Slew Rate
SR
R
B
L
B
= 10 k
11
V/s
Settling Time
ts
To 0.1%, V
B
IN
B
= 0 V to 2 V step, G = +1
370
ns
Phase Margin
C
B
L
B
= 0 pF
69
degrees
AD8655
Rev. 0 | Page 4 of 20
2.7 V ELECTRICAL SPECIFICATIONS
V
B
S
B
= 2.7 V, V
B
CM
B
= V
B
S
B
/2, T
B
A
B
= 25C, unless otherwise specified.
Table 2.
Parameter Symbol
Conditions Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
B
OS
B
V
B
CM
B
= 0 V to 2.7 V
44
250
V
-40C T
B
A
B
+125C
550
V
Offset Voltage Drift
V
B
OS
B
/
T
-40C T
B
A
B
+125C
0.4
2.0
V/C
Input Bias Current
I
B
B
B
1
10
pA
-40C T
B
A
B
+125C
300
pA
Input Offset Current
I
B
OS
B
10
pA
-40C T
B
A
B
+125C
300
pA
Input Voltage Range
0
2.7
V
Common-Mode Rejection Ratio
CMRR
V
B
CM
B
= 0 V to 2.7 V
80
98
dB
Large Signal Voltage Gain
A
B
VO
B
V
B
O
B
= 0.2 V to 2.5 V, R
B
L
B
= 10 k, V
B
CM
B
= 0 V
98
dB
-40C T
B
A
B
+125C
90
dB
OUTPUT CHARACTERISTICS
Output Voltage High
V
B
OH
B
I
B
L
B
= 1 mA; -40C T
B
A
B
+125C
2.67
2.688
V
Output Voltage Low
V
B
OL
B
I
B
L
B
= 1 mA; -40C T
B
A
B
+125C
10
30
mV
Output Current
I
B
OUT
B
V
B
OUT
B
= 0.5 V
75
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
B
S
B
= 2.7 V to 5.0 V
88
105
dB
Supply Current/Amplifier
I
B
SY
B
V
B
O
B
= 0 V
3.7
4.5
mA
-40C T
B
A
B
+125C
5.3
mA
INPUT CAPACITANCE
C
B
IN
B
Differential
9.3
pF
Common-Mode
16.7
pF
NOISE PERFORMANCE
Input Voltage Noise Density
e
B
n
B
f = 1 kHz
4.0
nV/
Hz
f = 10 kHz
2.7
nV/
Hz
Total Harmonic Distortion + Noise
THD + N
G = 1, R
B
L
B
= 1k, f = 1 kHz, V
B
IN
B
= 2 V p-p
0.0007
%
FREQUENCY RESPONSE
Gain Bandwidth Product
GBP
27
MHz
Slew Rate
SR
R
B
L
B
= 10 k
8.5
V/s
Settling Time
ts
To 0.1%, V
B
IN
B
= 0 to 1 V step, G = +1
370
ns
Phase Margin
C
B
L
B
= 0 pF
54
degrees
AD8655
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage
6 V
Input Voltage
VSS - 0.3 V to VDD + 0.3 V
Differential Input Voltage
6 V
Output Short-Circuit Duration
to GND
Indefinite
Electrostatic Discharge (HBM)
3.0 kV
Storage Temperature Range
R, RM Packages
-65C to +150C
Junction Temperature Range
R, RM Packages
-65C to +150C
Lead Temperature
(Soldering, 10 sec)
260C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Package Type
JA
1
JC
Unit
8-Lead MSOP (RM)
210
45
C/W
8-Lead SOIC (R)
158
43
C/W
1
JA
is specified for worst-case conditions, that is,
JA
is specified for a device
soldered in the circuit board for surface-mount packages.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8655
Rev. 0 | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
60
50
40
30
20
10
0
150
100
50
0
50
100
150
V
OS
(
V)
NUMBE
R OF AMP
L
IFIE
RS
05304-001
V
S
= 2.5V
Figure 3. Input Offset Voltage Distribution
150.0
100.0
50.0
0.0
50.0
100.0
150.0
50
0
50
TEMPERATURE (C)
100
150
V
OS
(
V)
05304-002
V
S
= 2.5V
Figure 4. Input Offset Voltage vs. Temperature
60
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
|TCV
OS
| (
V/C)
1.4
1.6
NUMBE
R OF AMP
L
IFIE
RS
05304-003
V
S
= 2.5V
Figure 5. |TCV
B
OS
B
| Distribution
20
10
0
10
20
30
0
1
2
3
4
COMMON-MODE VOLTAGE (V)
5
6
V
OS
(
V)
05304-004
V
S
= 2.5V
Figure 6. Input Offset Voltage vs. Common-Mode Voltage
250
200
150
100
50
0
0
20
40
60
80
100
120
140
TEMPERATURE (C)
IB (
p
A)
V
S
= 2.5V
05304-005
Figure 7. Input Bias Current vs. Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
S
U
P
P
L
Y
CURRE
NT (mA)
05304-006
V
S
= 2.5V
Figure 8. Supply Current vs. Supply Voltage
AD8655
Rev. 0 | Page 7 of 20
4.5
4.0
3.5
3.0
2.5
2.0
50
0
50
TEMPERATURE (C)
100
150
S
U
P
P
L
Y
CURRE
NT (mA)
V
S
= 2.5V
05304-007
Figure 9. Supply Current vs. Temperature
V
OH
V
OL
2500
2000
1500
1000
500
0
0
50
100
150
200
CURRENT LOAD (mA)
250
D
E
LTA
SW
IN
G FR
OM
SU
PPLY (
m
V)
05304-008
V
S
= 2.5V
Figure 10. Output Voltage to Supply Rail vs. Current Load
4.996
4.990
4.988
4.986
4.984
4.982
50
0
50
TEMPERATURE (C)
100
150
V
OH
(V
)
05304-009
4.992
4.994
V
S
= 2.5V
LOAD CURRENT = 1mA
Figure 11. Output Voltage Swing High vs. Temperature
12
10
8
6
4
2
50
0
50
TEMPERATURE (C)
100
150
V
OL
(mV
)
05304-010
LOAD CURRENT = 1mA
V
S
= 2.5V
Figure 12. Output Voltage Swing Low vs. Temperature
100
80
60
40
20
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
CMRR (dB)
V
S
= 2.5V
V
IN
= 28mV p-p
05304-011
Figure 13. Small Signal CMRR vs. Frequency
110.00
107.00
104.00
101.00
98.00
95.00
92.00
50
0
50
TEMPERATURE (C)
100
150
CMRR (dB)
05304-012
V
S
= 2.5V
V
CM
= 0V
Figure 14. Large Signal CMRR vs. Temperature
AD8655
Rev. 0 | Page 8 of 20
100
80
60
40
20
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
P
S
RR (dB)
V
S
= 2.5V
V
IN
= 50mV
R
L
= 1M
C
L
= 47pF
05304-013
+PSRR
PSRR
Figure 15. Small Signal PSSR vs. Frequency
110.00
108.00
106.00
104.00
102.00
100.00
50
0
50
TEMPERATURE (C)
100
150
PSR
R
(
d
B
)
05304-014
V
S
= 2.5V
Figure 16. Large Signal PSSR vs. Temperature
100
10
1
1
10
100
1k
FREQUENCY (Hz)
10k
100k
VOLTA
GE N
O
ISE D
E
N
S
ITY (
n
V/
H
z
1/2)
05304-019
V
S
= 2.5V
Figure 17. Voltage Noise Density vs. Frequency
1
V
S
= 2.5V
Vn (p-p) = 1.23
V
05304-020
500nV/D
I
V
1s/DIV
Figure 18. Low Frequency Noise (0.1 Hz to 10 Hz
).
T
2
V
S
= 2.5V
C
L
= 50pF
GAIN = +1
05304-021
1V/D
IV
20
s/DIV
V
IN
V
OUT
Figure 19. No Phase Reversal
120
100
80
60
40
20
0
20
40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
GAIN (
d
B)
05304-015
90
135
180
225
PH
A
SE SH
IFT (
D
egrees)
45
V
S
= 2.5V
C
LOAD
= 11.5pF
PHASE MARGIN = 69
Figure 20. Open-Loop Gain and Phase vs. Frequency
AD8655
Rev. 0 | Page 9 of 20
140.00
130.00
120.00
110.00
90.00
50
0
50
TEMPERATURE (C)
100
150
A
VO
(dB)
05304-016
V
S
= 2.5V
R
L
= 10k
100.00
Figure 21. Large Signal Open-Loop Gain vs. Temperature
40
50
30
20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
CLOSED-LOOP GAIN (dB)
05304-017
V
S
= 2.5V
R
L
= 1M
C
L
= 47pF
10
0
10
20
Figure 22. Closed-Loop Gain vs. Frequency
6
5
4
3
2
1
0
10k
100k
1M
FREQUENCY (Hz)
10M
OUTPUT (V)
05304-018
V
S
= 2.5V
V
IN
= 5V
G = +1
Figure 23. Maximum Output Swing vs. Frequency
T
2
V
S
= 2.5V
C
L
= 100pF
GAIN = +1
V
IN
= 4V
05304-022
TIME (10
s/DIV)
V
OUT
(
1
V/D
I
V)
Figure 24. Large Signal Response
2
T
V
S
= 2.5V
C
L
= 100pF
G = +1
05304-023
TIME (1
s/DIV)
V
OUT
(
100mV/D
I
V)
Figure 25. Small Signal Response
30
25
20
15
10
5
0
0
50
100
150
200
250
300
350
CAPACITANCE (pF)
OVER
SH
OOT %
V
S
= 2.5V
V
IN
= 200mV
OS
+OS
05304-024
Figure 26. Small Signal Overshoot vs. Load Capacitance
AD8655
Rev. 0 | Page 10 of 20
T
2
1
V
S
= 2.5V
V
IN
= 300mV
GAIN = 10
RECOVERY TIME = 240ns
05304-025
300mV
0V
0V
2.5V
V
IN
V
OUT
400ns/DIV
Figure 27. Negative Overload Recovery Time
1
2
05304-026
400ns/DIV
V
S
= 2.5V
V
IN
= 300mV
GAIN = 10
RECOVERY TIME = 240ns
T
V
IN
V
OUT
0V
0V
300mV
2.5V
Figure 28. Positive Overload Recovery Time
100
10
1
0.1
FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
100M
OUTP
UT IMP
E
DANCE
(
)
05304-027
V
S
= 2.5V
G = +100
G = +10
G = +1
Figure 29. Output Impedance vs. Frequency
80
70
60
50
40
30
20
10
0
150 125 100 75 50 25
0
V
OS
(
V)
25
50
75 100 125 150
NUMBE
R OF AMP
L
IFIE
RS
05304-028
V
S
= 1.35V
Figure 30. Input Offset Voltage Distribution
60
40
20
0
20
40
50
0
50
100
150
TEMPERATURE (C)
V
OS
(
V)
05304-029
V
S
= 1.35V
Figure 31. Input Offset Voltage vs. Temperature
80
70
60
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
|TCV
OS
| (
V/
C)
1.0
1.2
1.4
1.6
NUMBE
R OF AMP
L
IFIE
RS
05304-030
V
S
= 1.35V
Figure 32. |TCV
B
OS
B
| Distribution
AD8655
Rev. 0 | Page 11 of 20
4.5
4.0
3.5
3.0
2.5
2.0
50
0
50
100
150
TEMPERATURE (C)
S
U
P
P
L
Y
CURRE
NT (mA)
05304-031
V
S
= 1.35V
Figure 33. Supply Current vs. Temperature
1400
1200
1000
800
600
400
200
0
0
20
40
60
80
LOAD CURRENT (mA)
100
120
(V
SY
-V
OUT
) (mV
)
V
S
= 1.35V
V
OH
V
OL
05304-050
Figure 34. Output Voltage to Supply Rail vs. Load Current
2.698
2.694
2.690
2.686
2.682
2.678
2.674
50
0
50
100
150
TEMPERATURE (C)
V
OH
(V
)
05304-032
V
S
= 1.35V
LOAD CURRENT = 1mA
Figure 35. Output Voltage Swing High vs. Temperature
14
12
10
8
6
4
2
50
0
50
100
150
TEMPERATURE (C)
V
OL
(mV
)
05304-033
V
S
= 1.35V
LOAD CURRENT = 1mA
Figure 36. Output Voltage Swing Low vs. Temperature
T
2
V
S
= 1.35V
G = +1
C
L
= 50pF
05304-047
1V/DIV
V
IN
V
OUT
20
s/DIV
Figure 37. No Phase Reversal
T
2
V
S
= 1.35V
C
L
= 50pF
GAIN = +1
05304-042
TIME (10
s/DIV)
V
OUT
(
500mV/D
I
V)
Figure 38. Large Signal Response
AD8655
Rev. 0 | Page 12 of 20
2
T
V
S
= 1.35V
C
L
= 100pF
GAIN = +1
05304-043
TIME (1
s/DIV)
V
OUT
(
100mV/D
I
V)
Figure 39. Small Signal Response
35
30
25
20
15
10
5
0
0
50
100
150
200
250
300
350
CAPACITANCE (pF)
OVER
SH
OOT %
V
S
= 1.35V
V
IN
= 200mV
OS
+OS
05304-044
Figure 40. Small Signal Overshoot vs. Load Capacitance
400ns/DIV
T
1
2
V
S
= 1.35V
V
IN
= 200mV
GAIN = 10
RECOVERY TIME = 180ns
05304-045
200mV
0V
0V
1.35V
V
IN
V
OUT
Figure 41. Negative Overload Recovery Time
T
1
2
V
S
= 1.35V
V
IN
= 200mV
GAIN = 10
RECOVERY TIME = 200ns
05304-046
0V
200mV
1.35V
0V
400ns/DIV
V
IN
V
OUT
Figure 42. Positive Overload Recovery Time
100
80
60
40
20
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
CMRR (dB)
V
S
= 1.35V
V
IN
= 28mV p-p
R
L
= 1M
C
L
= 47pF
05304-034
Figure 43. Small Signal CMRR vs. Frequency
102.00
98.00
94.00
90.00
86.00
50
0
50
TEMPERATURE (C)
100
150
CMRR (dB)
05304-035
V
S
= 1.35V
Figure 44. Large Signal CMRR vs. Temperature
AD8655
Rev. 0 | Page 13 of 20
100
80
60
40
20
0
100
1k
10k
100k
FREQUENCY (Hz)
1M
100M
10M
P
S
RR (dB)
V
S
= 1.35V
V
IN
= 50mV
R
L
= 1M
C
L
= 47pF
05304-040
+PSRR
PSRR
Figure 45. Small Signal PSSR vs. Frequency
120
100
80
60
40
20
20
40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
GAIN (
d
B)
05304-036
90
135
180
225
PH
A
SE SH
IFT (
D
egrees)
45
V
S
= 1.35V
C
LOAD
= 11.5pF
PHASE MARGIN = 54
0
Figure 46. Open-Loop Gain and Phase vs. Frequency
130.00
120.00
110.00
100.00
90.00
80.00
50
0
50
TEMPERATURE (C)
100
150
A
VO
(dB)
05304-037
V
S
= 1.35V
R
L
= 10k
Figure 47. Large Signal Open-Loop Gain vs. Temperature
50
40
30
20
10
0
10
20
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
CLOSED-LOOP GAIN (dB)
V
S
= 1.35V
R
L
= 1M
C
L
= 47pF
05304-038
Figure 48. Closed-Loop Gain vs. Frequency
3.0
2.5
2.0
1.5
1.0
0.5
0
10k
100k
1M
FREQUENCY (Hz)
10M
OUTPUT (V)
05304-039
V
S
= 1.35V
V
IN
= 2.7V
G = +1
NO LOAD
Figure 49. Maximum Output Swing vs. Frequency
1000
100
10
1
0.1
FREQUENCY (Hz)
100
1k
10k
100k
1M
100M
10M
OUTP
UT IMP
E
DANCE
(
)
05304-041
V
S
= 1.35V
G = +1
G = +100
G = +10
Figure 50. Output Impedance vs. Frequency
AD8655
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
The AD8655 amplifier is a voltage feedback, rail-to-rail input
and output precision CMOS amplifier, which operates from
2.7 V to 5.0 V of power supply voltage. This amplifier uses the
Analog Devices DigiTrim technology to achieve a higher degree
of precision than is available from most CMOS amplifiers.
DigiTrim technology, used in a number of ADI amplifiers, is a
method of trimming the offset voltage of the amplifier after it is
packaged. The advantage of post-package trimming is that it
corrects any offset voltages caused by the mechanical stresses of
assembly.
The AD8655 is available in a standard op amp pinout, making
DigiTrim completely transparent to the user. The input stage of
the amplifier is a true rail-to-rail architecture, allowing the
input common-mode voltage range of the amplifier to extend
to both positive and negative supply rails. The open-loop gain
of the AD8655 with a load of 10 k is typically 110 dB.
The AD8655 can be used in any precision op amp application.
The amplifier does not exhibit phase reversal for common-mode
voltages within the power supply. The AD8655 is a great choice
for high resolution data acquisition systems with voltage noise of
2.7 nV/Hz and THD + Noise of 103 dB for a 2 V p-p signal at
10 kHz. Its low noise, sub-pA input bias current, precision offset,
and high speed make it a superb preamp for fast filter applica-
tions. The speed and output drive capability of the AD8655 also
make it useful in video applications.
AD8655
Rev. 0 | Page 15 of 20
APPLICATIONS
INPUT OVERVOLTAGE PROTECTION
The internal protective circuitry of the AD8655 allows voltages
exceeding the supply to be applied at the input. It is recom-
mended, however, not to apply voltages that exceed the supplies
by more than 0.3 V at either input of the amplifier. If a higher
input voltage is applied, series resistors should be used to limit
the current flowing into the inputs. The input current should be
limited to less than 5 mA.
The extremely low input bias current allows the use of larger
resistors, which allows the user to apply higher voltages at the
inputs. The use of these resistors adds thermal noise, which
contributes to the overall output voltage noise of the amplifier.
For example, a 10 k resistor has less than 12.6 nV/Hz of
thermal noise and less than 10 nV of error voltage at room
temperature.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground.
For circuits with resistive feedback network, the total capacitance,
whether it is the source capacitance, stray capacitance on the
input pin, or the input capacitance of the amplifier causes a
breakpoint in the noise gain of the circuit. As a result, a
capacitor must be added in parallel with the gain resistor to
obtain stability. The noise gain is a function of frequency and
peaks at the higher frequencies, assuming the feedback capaci-
tor is selected to make the second-order system critically
damped. A few picofarads of capacitance at the input reduce
the input impedance at high frequencies, which increases the
amplifier's gain, causing peaking in the frequency response or
oscillations. With the AD8655, additional input damping is
required for stability with capacitive loads greater than 200 pF
with direct input to output feedback. See the next section on
Driving Capacitive Loads.
DRIVING CAPACITIVE LOADS
Although the AD8655 can drive capacitive loads up to 500 pF
without oscillating, a large amount of ringing is present when
operating the part with input frequencies above 100 kHz. This
is especially true when the amplifier is configured in positive
unity gain (worst case). When such large capacitive loads are
required, the use of external compensation is highly recom-
mended. This reduces the overshoot and minimizes ringing,
which in turn, improves the stability of the AD8655 when
driving large capacitive loads.
One simple technique for compensation is a snubber that
consists of a simple RC network. With this circuit in place,
output swing is maintained, and the amplifier is stable at all
gains. Figure 52 shows the implementation of a snubber, which
reduces overshoot by more than 30% and eliminates ringing.
Using a snubber does not recover the loss of bandwidth
incurred from a heavy capacitive load.
TIME (2
s/DIV)
V
S
= 2.5V
A
V
= 1
C
L
= 500pF
05304-051
VOLTA
GE (
100mV/D
I
V)
Figure 51. Driving Heavy Capacitive Loads Without Compensation
V+
200
500pF
500pF
V
V
CC
V
EE
200mV
+
05304-052
+
Figure 52. Snubber Network
V
S
= 2.5V
A
V
= 1
R
S
= 200
C
S
= 500pF
C
L
= 500pF
TIME (10
s/DIV)
05304-053
VOLTA
GE (
100mV/D
I
V)
Figure 53. Driving Heavy Capacitive Loads Using a Snubber Network
AD8655
Rev. 0 | Page 16 of 20
THD Readings vs. Common-Mode Voltage
Total harmonic distortion of the AD8655 is well below 0.0007%
with a load of 1 k. The distortion is a function of the circuit
configuration, the voltage applied, and the layout, in addition
to other factors.
+
V
IN
R
L
V
OUT
+2.5V
2.5V
AD8655
05304-054
Figure 54. THD + N Test Circuit
1.0
0.1
0.01
0.001
0.0001
%
20
100
1k
10k
80k
50
500
5k
50k
200
2k
20k
Hz
0.5
0.05
0.005
0.0005
0.2
0.02
0.002
0.0002
SWEEP 1:
V
IN
= 2V p-p
R
L
= 10k
SWEEP 2:
V
IN
= 2V p-p
R
L
= 1k
SWEEP 1
SWEEP 2
05304-055
Figure 55. THD + Noise vs. Frequency
AD8655
Rev. 0 | Page 17 of 20
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
Power supply pins can act as inputs for noise, so care must be
taken to apply a noise-free, stable dc voltage. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering most
of the noise. Bypassing schemes are designed to minimize the
supply impedance at all frequencies with a parallel combination
of capacitors with values of 0.1 F and 4.7 F. Chip capacitors of
0.1 F (X7R or NPO) are critical and should be as close as
possible to the amplifier package. The 4.7 F tantalum capacitor
is less critical for high frequency bypassing, and, in most cases,
only one is needed per board at the supply inputs.
GROUNDING
A ground plane layer is important for densely packed PC
boards to minimize parasitic inductances. This minimizes
voltage drops with changes in current. However, an under-
standing of where the current flows in a circuit is critical to
implementing effective high speed circuit design. The length
of the current path is directly proportional to the magnitude
of parasitic inductances, and, therefore, the high frequency
impedance of the path. Large changes in currents in an
inductive ground return create unwanted voltage noise.
The length of the high frequency bypass capacitor leads is
critical, and, therefore, surface-mount capacitors are
recommended. A parasitic inductance in the bypass ground
trace works against the low impedance created by the bypass
capacitor. Because load currents flow from the supplies, the
ground for the load impedance should be at the same physical
location as the bypass capacitor grounds. For larger value
capacitors intended to be effective at lower frequencies, the
current return path distance is less critical.
LEAKAGE CURRENTS
Poor PC board layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the AD8655. Any voltage differential
between the inputs and nearby traces sets up leakage currents
through the PC board insulator, for example, 1 V/100 G =
10 pA. Similarly, any contaminants on the board can create
significant leakage (skin oils are a common problem).
To significantly reduce leakage, put a guard ring (shield) around
the inputs and input leads that are driven to the same voltage
potential as the inputs. This ensures that there is no voltage
potential between the inputs and the surrounding area to set up
any leakage currents. To be effective, the guard ring must be
driven by a relatively low impedance source and should
completely surround the input leads on all sides, above and
below, by using a multilayer board.
The charge absorption of the insulator material itself can also
cause leakage currents. Minimizing the amount of material
between the input leads and the guard ring helps to reduce the
absorption. Also, low absorption materials, such as Teflon or
ceramic, may be necessary in some instances.
AD8655
Rev. 0 | Page 18 of 20
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8
5
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
0.80
0.60
0.40
8
0
4
8
1
5
4.90
BSC
PIN 1
0.65 BSC
3.00
BSC
SEATING
PLANE
0.15
0.00
0.38
0.22
1.10 MAX
3.00
BSC
COPLANARITY
0.10
0.23
0.08
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 56. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Figure 57. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description Package
Option
Branding
AD8655ARZ
T
P
1
P
T
-40C to +125C
8-Lead Standard Small Outline Package (SOIC)
R-8
AD8655ARZ-REEL
1
-40C to +125C
8-Lead Standard Small Outline Package (SOIC)
R-8
AD8655ARZ-REEL7
1
-40C to +125C
8-Lead Standard Small Outline Package (SOIC)
R-8
AD8655ARMZ-REEL
1
-40C to +125C
8-Lead Mini Small Outline Package (MSOP)
RM-8
A0D
AD8655ARMZ-R2
1
-40C to +125C
8-Lead Mini Small Outline Package (MSOP)
RM-8
A0D
T
P
1
P
T
Z = Pb-free part.
AD8655
Rev. 0 | Page 19 of 20
NOTES
AD8655
Rev. 0 | Page 20 of 20
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0530404/05(0)
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