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Audio Codec for Recordable DVD

ADAV801

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

Stereo analog-to-digital converter (ADC)

Supports 48/96 kHz sample rates
102 dB dynamic range
Single-ended input
Automatic level control

Stereo digital-to-analog converter (DAC)

Supports 32/44.1/48/96/192 kHz sample rates
101 dB dynamic range
Single-ended output

Asynchronous operation of ADC and DAC
Stereo sample rate converter (SRC)

Input/output range: 8 kHz to 192 kHz
140 dB dynamic range

Digital interfaces

Record
Playback
Auxiliary record
Auxiliary playback

S/PDIF (IEC60958) input and output

Digital interface receiver (DIR)
Digital interface transmitter (DIT)

PLL-based audio MCLK generators
Generates required DVDR system MCLKs
Device control via SPI®-compatible serial port
64-lead LQFP package

FUNCTIONAL BLOCK DIAGRAM

ANALOG-TO-DIGITAL

CONVERTER

REFERENCE

SRC

DIGITAL-TO-ANALOG

CONVERTER

ADAV801

DIT

AUX DATA

OUTPUT

RECORD

DATA

OUTPUT

CONTROL

REGISTERS

PLL

DIGITAL

INPUT/OUTPUT

SWITCHING MATRIX

(DATAPATH)

PLAYBACK

DATA INPUT

AUX DATA

INPUT

DIR

VINL

VINR

VREF

FILTD

IAUXL

RCL

IAUXBCL

IAUXSDAT

DIRIN

OLRCLK

OBCLK
OSDATA

OAUXLRCLK
OAUXBCLK
OAUXSDATA

DITOUT

CIN

CCL

SYSCL

ZEROL/INT
ZEROR

MCL

XOUT

XIN

MCL

VOUTL

VOUTR

04577-0-001

RCL

IBCL

ISDAT

Figure 1.

APPLICATIONS

DVD-recordable
All formats
CD-R/W

PRODUCT OVERVIEW

The ADAV801 is a stereo audio codec intended for applications
such as DVD or CD recorders that require high performance
and flexible, cost-effective playback and record functionality.
The ADAV801 features Analog Devices' proprietary, high
performance converter cores to provide record (ADC), playback
(DAC), and format conversion (SRC) on a single chip. The
ADAV801 record channel features variable input gain to allow
for adjustment of recorded input levels and automatic level
control, followed by a high performance stereo ADC whose
digital output is sent to the record interface. The record channel
also features level detectors that can be used in feedback loops
to adjust input levels for optimum recording. The playback
channel features a high performance stereo DAC with
independent digital volume control.

The sample rate converter (SRC) provides high performance
sample rate conversion to allow inputs and outputs that require
different sample rates to be matched. The SRC input can be
selected from playback, auxiliary, DIR, or ADC (record). The
SRC output can be applied to the playback DAC, both main and
auxiliary record channels, and a DIT.

Operation of the ADAV801 is controlled via an SPI-compatible
serial interface, which allows the programming of individual
control register settings. The ADAV801 operates from a single
analog 3.3 V power supply and a digital power supply of 3.3 V
with optional digital interface range of 3.0 V to 3.6 V.

The part is housed in a 64-lead LQFP package and is character-
ized for operation over the commercial temperature range of
-40°C to +85°C.

ADAV801

Rev. 0 | Page 2 of 56

TABLE OF CONTENTS

Specifications..................................................................................... 3

Test Conditions............................................................................. 3

ADAV801 Specifications ............................................................. 3

Timing Specifications .................................................................. 6

Temperature Range ...................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Typical Performance Characteristics ........................................... 11

Functional Description .................................................................. 15

ADC Section ............................................................................... 15

DAC Section................................................................................ 18

Sample Rate Converter (SRC) Functional Overview ............ 19

PLL Section ................................................................................. 22

SPDIF Transmitter and Receiver.............................................. 23

Serial Data Ports ......................................................................... 27

Interface Control ............................................................................ 30

SPI Interface ................................................................................ 30

Block Reads and Writes ............................................................. 30

Layout Considerations................................................................... 54

ADC ............................................................................................. 54

DAC.............................................................................................. 54

PLL ............................................................................................... 54

Reset and Power-Down Considerations ................................. 54

Outline Dimensions ....................................................................... 55

Ordering Guide .......................................................................... 55

REVISION HISTORY

7/04--Revision 0: Initial Version

ADAV801

Rev. 0 | Page 3 of 56

SPECIFICATIONS

TEST CONDITIONS

Test conditions, unless otherwise noted.

Table 1.

Test Parameter

Condition

Supply Voltage

Analog 3.3

Digital 3.3

Ambient Temperature

25°C

Master Clock (XIN)

12.288 MHz

Measurement Bandwidth

20 Hz to 20 kHz

Word Width (All Converters)

24 bits

Load Capacitance on Digital Outputs

100 pF

ADC Input Frequency

1007.8125 Hz at -1 dBFS

DAC Output Frequency

960.9673 Hz at 0 dBFS

Digital Input

Slave Mode, I

S Justified Format

Digital Output

Slave Mode, I

S Justified Format

ADAV801 SPECIFICATIONS

Table 2.

Parameter Min

Typ

Max

Unit

Comments

PGA SECTION

Input Impedance

Minimum Gain

Maximum Gain

Gain Step

0.5

REFERENCE SECTION

Absolute Voltage, V

REF

1.5

REF

Temperature Coefficient

ppm/°C

ADC SECTION

Number of Channels

Resolution

Bits

Dynamic Range

-60 dB input

Unweighted

= 48 kHz

= 96 kHz

A-Weighted 98

102

= 48 kHz

101

= 96 kHz

Total Harmonic Distortion plus Noise

Input = -1.0 dBFS

-88

= 48 kHz

-87

= 96 kHz

Analog Input

Input Range (± Full Scale)

1.0

V rms

DC Accuracy

Gain Error

-1.5

-0.8

Interchannel Gain Mismatch

0.05

Gain Drift

mdB/°C

Offset

-10

Crosstalk (EIAJ Method)

-110

Volume Control Step Size (256 Steps)

0.39

% per
step

ADAV801

Rev. 0 | Page 4 of 56

Parameter Min

Typ

Max

Unit

Comments

Maximum Volume Attenuation

-48

Mute Attenuation

ADC outputs all zero codes

Group Delay

= 48 kHz

910

µs

= 96 kHz

460

µs

ADC LOW-PASS DIGITAL DECIMATION FILTER CHARACTERISTICS

Pass-Band Frequency

kHz

Sample rate: 48 kHz

kHz

Sample rate: 96 kHz

Stop-Band Frequency

kHz

Sample rate: 48 kHz

kHz

Sample rate: 96 kHz

Stop-Band Attenuation

120

Sample rate: 48 kHz

120

Sample rate: 96 kHz

Pass-Band Ripple

±0.01

Sample rate: 48 kHz

±0.01

Sample rate: 96 kHz

ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS

Cutoff Frequency

0.9

= 48 kHz

SRC SECTION

Resolution

Bits

Sample Rate

192

kHz

XIN = 27 MHz

SRC MCLK

138 × f

S-MAX

MHz

S-MAX

is the greater of the input

or output sample rate

Maximum Sample Rate Ratios

Upsampling

1:8

Downsampling

7.75:1

Dynamic Range

140

20 Hz to f

/2, 1 kHz,

-60 dBFS input, f

= 44.1 kHz,

OUT

= 48 kHz

Total Harmonic Distortion plus Noise

120

20 Hz to f

/2, 1 kHz,

0 dBFS input, f

= 44.1 kHz,

OUT

= 48 kHz

DAC SECTION

Number of Channels

Resolution

Bits

Dynamic Range

20 Hz to 20 kHz, -60 dB input

Unweighted

dB f

= 48 kHz

dB f

= 96 kHz

A-Weighted 97

101

dB f

= 48 kHz

100

dB f

= 96 kHz

Total Harmonic Distorton plus Noise

Referenced to 1 V rms

-91

dB f

= 48 kHz

-90

dB f

= 96 kHz

Analog Outputs

Output Range (± Full Scale)

1.0

V rms

Output Resistance

Common-Mode Output Voltage

1.5

DC Accuracy

Gain Error

-2

-0.8

Interchannel Gain Mismatch

0.05

Gain Drift

mdB/°C

DC Offset

-30

+30

Crosstalk (EIAJ Method)

-110

Phase Deviation

0.05

Degrees

Mute Attenuation

-95.625

ADAV801

Rev. 0 | Page 5 of 56

Parameter Min

Typ

Max

Unit

Comments

Volume Control Step Size (256 Steps)

0.375

Group Delay

48 kHz

630

µs

96 kHz

155

µs

192 kHz

µs

DAC LOW-PASS DIGITAL INTERPOLATION FILTER CHARACTERISTICS

Pass-Band Frequency

kHz

Sample rate: 44.1 kHz

kHz

Sample rate: 48 kHz

kHz

Sample rate: 96 kHz

Stop-Band Frequency

kHz

Sample rate: 44.1 kHz

kHz

Sample rate: 48 kHz

kHz

Sample rate: 96 kHz

Stop-Band Attenuation

Sample rate: 44.1 kHz

Sample rate: 48 kHz

Sample rate: 96 kHz

Pass-Band Ripple

±0.002

Sample rate: 44.1 kHz

±0.002

Sample rate: 48 kHz

±0.005

Sample rate: 96 kHz

PLL SECTION

Master Clock Input Frequency

27/54

MHz

Generated System Clocks

MCLKO

27/54

MHz

SYSCLK1 256

768

256/384/512/768 × 32/44.1/
48 kHz

SYSCLK2 256

768

256/384/512/768 × 32/44.1/
48 kHz

SYSCLK3 256

512

256/512 × 32/44.1/48 kHz

Jitter

SYSCLK1

rms

SYSCLK2

rms

SYSCLK3

rms

DIR SECTION

Input Sample Frequency

27.2

200

kHz

Differential Input Voltage

200

DIT SECTION

Output Sample Frequency

27.2

200 kHz

DIGITAL I/O

Input Voltage High, V

2.0

DVDD V

Input Voltage Low, V

0.8 V

Input Leakage, I

@ V

= 3.3 V

10 µA

Input Leakage, I

@ V

= 0 V

10 µA

Output Voltage High, V

@ I

= 0.4 mA

2.4

Output Voltage Low, V

@ I

= -2 mA

0.4 V

Input Capacitance

15 pF

POWER

Supplies

Voltage, AVDD

3.0

3.3

3.6

Voltage, DVDD

3.0

3.3

3.6

Voltage, ODVDD

3.0

3.3

3.6

ADAV801

Rev. 0 | Page 6 of 56

Parameter Min

Typ

Max

Unit

Comments

Operating Current

All supplies at 3.3 V

Analog Current

Digital Current

Digital Interface Current

DIRIN/DIROUT Current

PLL Current

Power-Down Current

RESET low, no MCLK

Analog Current

Digital Current

2.5

Digital Interface Current

700

µA

DIRIN/DIROUT Current

3.5

PLL Current

900

µA

Power Supply Rejection

Signal at Analog Supply Pins

-70

1 kHz, 300 mV p-p

-70

20 kHz, 300 mV p-p

Guaranteed by design.

TIMING SPECIFICATIONS

Timing specifications are guaranteed over the full temperature and supply range.

Table 3.

Parameter

Min

Typ

Max

Unit

Comments

MASTER CLOCK AND RESET

MCLK

MCLKI Frequency

12.288

MHz

XIN

XIN Frequency

27.0

MHz

RESET

RESET Low

SPI PORT

CCH

CCLK High

CCL

CCLK Low

CIS

CIN Setup

To CCLK rising edge

CIH

CIN Hold

From CCLK rising edge

CLS

CLATCH Setup

To CCLK rising edge

CLH

CLATCH Hold

From CCLK rising edge

COE

COUT Enable

From CLATCH falling edge

COD

COUT Delay

From CCLK falling edge

COTS

COUT Three-State

From CLATCH rising edge

SERIAL PORTS

Slave Mode

SBH

xBCLK High

SBL

xBCLK Low

SBF

xBCLK Frequency

64 × f

SLS

xLRCLK Setup

To xBCLK rising edge

SLH

xLRCLK Hold

From xBCLK rising edge

SDS

xSDATA Setup

To xBCLK rising edge

SDH

xSDATA Hold

From xBCLK rising edge

SDD

xSDATA Delay

From xBCLK falling edge

ADAV801

Rev. 0 | Page 8 of 56

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

DVDD to DGND and ODVDD to

DGND

0 V to 4.6 V

AVDD to AGND

0 V to 4.6 V

Digital Inputs

DGND - 0.3 V to DVDD + 0.3 V

Analog Inputs

AGND - 0.3 V to AVDD + 0.3 V

AGND to DGND

-0.3 V to +0.3 V

Reference Voltage

Indefinite short circuit to ground

Soldering (10 s)

300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

ADAV801

Rev. 0 | Page 9 of 56

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOU

OAUX

DATA

IAUX

LRCLK

IAUX

BCLK

IAUX

DATA

ZEROL/INT

ZEROR

DVDD

DGND

ADVDD
ADGND
PLL_LF2
PLL_LF1
PLL_GND
PLL_VDD
DGND
SYSCLK1
SYSCLK2
SYSCLK3
XIN
XOUT

MCLKO
MCLKI
DVDD
DGND

17 18 19 20 21 22 23 24

ILRCLK

IBCLK

DATA

OLRCLK

OBCLK

DATA

DIRIN

ODVDD

ODGND

DITOUT

OAUX

LRCLK

OAUX

BCLK

64 63 62 61 60 59 58

CAP

AGND

CAP

AGND

FILTD

AGND

VINR

VINL

AGND

AVDD

DIR_LF

DIR_GND

DIR_VDD

RESET

CLATCH

CIN

CCLK

COUT

25 26 27

57 56 55 54 53 52 51 50 49

ADAV801

TOP VIEW

(Not to Scale)

04577-0-002

PIN 1

INDICATOR

NC = NO CONNECT

Figure 2. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

I/O

Description

VINR

Analog Audio Input, Right Channel.

VINL

Analog Audio Input, Left Channel.

3 AGND

Analog

Ground.

4 AVDD

Analog

Voltage

Supply.

DIR_LF

DIR Phase-Locked Loop (PLL) Filter Pin.

DIR_GND

Supply Ground for DIR Analog Section. This pin should be connected to AGND.

DIR_VDD

Supply for DIR Analog Section. This pin should be connected to AVDD.

RESET

Asychronous Reset Input (Active Low).

CLATCH

Chip Select (Control Latch) Pin of SPI-Compatible Control Interface.

CIN

Data Input of SPI-Compatible Control Interface.

CCLK

Clock Input of SPI-Compatible Control Interface.

COUT

Data Output of SPI-Compatible Control Interface.

13 ZEROL/INT

Left Channel (Output) Zero Flag or Interrupt (Output) Flag. The function of this pin is determined
by the INTRPT pin in DAC Control Register 4.

ZEROR

Right Channel (Output) Zero Flag.

DVDD

Digital Voltage Supply.

16 DGND

Digital

Ground.

17 ILRCLK

I/O

Sampling

Clock

(LRCLK) of Playback Digital Input Port.

IBCLK

I/O

Serial Clock (BCLK) of Playback Digital Input Port.

ISDATA

Data Input of Playback Digital Input Port.

20 OLRCLK

I/O

Sampling

Clock

(LRCLK) of Record Digital Output Port.

OBCLK

I/O

Serial Clock (BCLK) of Record Digital Output Port.

OSDATA

Data Output of Record Digital Output Port.

DIRIN

Input to Digital Input Receiver (S/PDIF).

ODVDD

Interface Digital Voltage Supply.

ODGND

Interface Digital Ground.

DITOUT

S/PDIF Output from DIT.

27 OAUXLRCLK

I/O

Sampling

Clock

(LRCLK) of Auxiliary Digital Output Port.

ADAV801

Rev. 0 | Page 10 of 56

Pin No.

Mnemonic

I/O

Description

OAUXBCLK

I/O

Serial Clock (BCLK) of Auxiliary Digital Output Port.

OAUXSDATA

Data Output of Auxiliary Digital Output Port.

IAUXLRCLK

I/O

Sampling Clock (LRCLK) of Auxiliary Digital Input Port.

IAUXBCLK

I/O

Serial (BCLK) of Auxiliary Digital Input Port.

IAUXSDATA

Data Input of Auxiliary Digital Input Port.

33 DGND

Digital

Ground.

DVDD

Digital Supply Voltage.

MCLKI

External MCLK Input.

36 MCLKO

Oscillator

Output.

37 XOUT

I Crystal

Input.

XIN

Crystal or External MCLK Input.

SYSCLK3

System Clock 3 (from PLL2).

SYSCLK2

System Clock 2 (from PLL2).

SYSCLK1

System Clock 1 (from PLL1).

42 DGND

Digital

Ground.

PLL_VDD

Supply for PLL Analog Section. This pin should be connected to AVDD.

PLL_GND

Ground for PLL Analog Section. This pin should be connected to AGND.

PLL_LF1

Loop Filter for PLL1.

PLL_LF2

Loop Filter for PLL2.

ADGND

Analog Ground (Mixed Signal). This pin should be connected to AGND.

ADVDD

Analog Voltage Supply (Mixed Signal). This pin should be connected to AVDD.

VOUTR

Right Channel Analog Output.

50 NC No

Connect.

VOUTL

Left Channel Analog Output.

52 NC No

Connect.

53 AVDD

Analog

Voltage

Supply.

54 AGND

Analog

Ground.

FILTD

Output DAC Reference Decoupling.

56 AGND

Analog

Ground.

VREF

Voltage Reference Voltage.

58 AGND

Analog

Ground.

59 AVDD

Analog

Voltage

Supply.

CAPRN

ADC Modulator Input Filter Capacitor (Right Channel, Negative).

CAPRP

ADC Modulator Input Filter Capacitor (Right Channel, Positive).

62 AGND

Analog

Ground.

CAPLP

ADC Modulator Input Filter Capacitor (Left Channel, Positive).

CAPLN

ADC Modulator Input Filter Capacitor (Left Channel, Negative).

ADAV801

Rev. 0 | Page 13 of 56

FREQUENCY (kHz)

MAGNITUDE

(dB)

20

40

80

100

60

120

140

160

04577-0-049

DNR = 102dB
(A-Weighted)

Fig

ure 15. DAC Dynamic Range, f

= 48 k

FREQUENCY (kHz)

MAGNITUDE

(dB)

20

40

80

100

60

120

140

160

04577-0-050

THD+N = 96dB

Figure 16. DAC THD + N, f

= 48 kHz

FREQUENCY (kHz)

MAGNITUDE

(dB)

20

40

80

100

60

120

140

160

45 48

04577-0-051

DNR = 102dB
(A-Weighted)

Figure 17. DAC Dynamic Range, f

= 96 kHz

FREQUENCY (kHz)

MAGNITUDE

(dB)

20

40

80

100

60

120

140

160

45 48

04577-0-052

THD+N = 95dB

Figure 18. DAC THD + N, f

= 96 kHz

FREQUENCY (kHz)

MAGNITUDE

(dB)

20

40

80

100

60

120

140

160

04577-0-053

DNR = 102dB
(A-Weighted)

Figure 19. ADC Dynam c Range, f

= 48 kHz

FREQUENCY (kHz)

MAGNITUDE

(dB)

20

40

80

100

60

120

140

160

04577-0-054

THD+N = 92dB

= 3dB)

Figure 20. DAC THD + N, f

= 48 kHz

ADAV801

Rev. 0 | Page 15 of 56

TION

and by a factor of 8 at

ther the

FUNCTIONAL DESCRIP

ADC SECTION

The ADAV801's ADC section is implemented using a second-
order multibit (5 bits) - modulator. The modulator is
sampled at either half of the ADC MCLK rate (modulator clo
= 128 × f

) or one-quarter of the ADC MCLK rate (modulator

clock = 64 × f

). The digital decimator consists of a Sinc^5 filter

followed by a cascade of three half-band FIR filters. The Sin
decimates by a factor of 16 at 48 kHz
96 kHz. Each of the half-band filters decimates by a factor of 2.

Figure 23 shows the details of the ADC section. The ADC can
be clocked by a number of different clock sources to control t
sample rate. MCLK selection for the ADC is set by Internal
Clocking Control Register 1 (Address 0x76). The ADC provide
an output word of up to 24 bits in resolution in twos comple-
ment format. The output word can be routed to ei
output ports, the sample rate converter, or the SPDIF digital
transmitter.

LL2

INTE

RNAL

LL1

INTE

RNAL

MCLKI

XIN

REG 0x76
BITS 42

DIR P

LL (2

× f

)

REG 0x6F
BITS 10

04577-0-003

DIR P

LL (5

× f

)

ADC MCLK

DIVIDER

ADC

MCLK

ADC

Figure 23. Clock Path Control on the ADC

Programmable Gain Amplifier (PGA)

The input of the record channel features a PGA that converts
the single-ended signal to a differential signal, which is applied
to the analog - modulator of the ADC. The PGA can be
programmed to amplify a signal by up to 24 dB in 0.5 dB
increments. Figure 24 shows the structure of the PGA circuit.

TO 64k

125

CAPxN

EXTERNAL

CAPACITOR

(1nF NPO)

VREF

MODULATOR

EXTERNAL

CAPACITOR

(1nF NPO)

CAPxP

EXTERNAL

CAPACITOR

(1nF NPO)

04577-0-004

125

Figure 24. PGA Block Diagram

Analog - Modulator

The ADC features a second-order, multibit, - modulator. The
input features two integrators in cascade followed by a flash
converter. This multibit output is directed to a scrambler,
followed by a DAC for loop feedback. The flash ADC outp
also converted from thermometer coding to binary codin
input as a 5-bit word to the decimator. F

ut is

g for

igure 25 shows the

ADC block diagram.

The ADC also features independent digital volume control for
the left and right channels. The volume control consists of
256 linear steps, with each step reducing the digital output
codes by 0.39%. Each channel also has a peak detector that
records the peak level of the input signal. The peak detector
register is cleared by reading it.

ADC MCLK

AMC

(REG 0X63

BIT-7)

MULTIBIT

MODULATOR

DECIMATOR

HPF

PEAK

DETECT

VOLUME

ONTROL

04577-0-005

SINC^5

HALF-BAND

FILTER

MODULATOR

CLOCK

(6.144MHz MAX)

384kHz

768kHz

SINC

COMPENSATION

192kHz

384kHz

HALF-BAND

FILTER

96kHz

192kHz

48kHz

96kHz

Diagram

Figure 25. A

DC Block

ADAV801

Rev. 0 | Page 16 of 56

ALC)

aximum front end gain.

olume

ADC is still present at the output of the ADC, but scaled by a
value determined by the volume control register.

The ALC block has two functions, attack mode and recover
mode. Recovery mode consists of three settings: no recovery,
normal recovery, and limited recovery. These modes are
discussed in the following sections. Figure 26 is a flow diagram
of the ALC block. When the ALC has been enabled, any changes
made to the PGA or ALC settings are ignored. To change the
functionality of the ALC, it must first be disabled. The settings
can then be changed and the ALC re-enabled.

Attack Mode

When the absolute value of the ADC output exceeds the level
set by the attack threshold bits in ALC Control Register 2, attack
mode is initiated. The PGA gain for both channels is reduced by
one step (0.5 dB). The ALC then waits for a time determined by
the attack timer bits before sampling the ADC output value
again. If the ADC output is still above the threshold, the PGA
gain is reduced by a further step. This procedure continues until
the ADC output is below the limit set by the attack threshold
bits. The initial gains of the PGAs are defined by the ADC left
PGA gain register and the ADC right PGA gain register, and
they can have different values. The ALC subtracts a common
gain offset to these values. The ALC preserves any gain differ-
ence in dB as defined by these registers. At no time do the PGA
gains exceed their initial values. The initial gain setting,
therefore, also serves as a maximum value.

The limit detection mode bit in ALC Control Register 1 deter-
mines how the ALC responds to an ADC output that exceeds
the set limits. If this bit is a 1, then both channels must exceed
the threshold before the gain is reduced. This mode can be used
to prevent unnecessary gain reduction due to spurious noise on
a single channel. If the limit detection mode bit is a 0, the gain is
reduced when either channel exceeds the threshold.

is not recovered until the ALC has been reset, either

r by

in reduction unnecessarily.

ormal Recovery Mode

Normal recovery mode allows for the PGA gain to be recovered,
provided that the input signal meets certain criteria. First, the
ALC must not be in attack mode, that is, the PGA gain has been

sufficiently such that the input signal is below the level

set by the attack threshold bits. Second, the output result from
the ADC must be below the level set by the recovery threshold
bits in the ALC control register. If both of these criteria are met,
the gain is recovered by one step (0.5 dB). The gain is incremen-
tally restored to its original value, assuming that the ADC
output level is below the recovery threshold at intervals
determined by the recovery time bits.

If the ADC output level exceeds the recovery threshold while
the PGA gain is being restored, the PGA gain value is held and
does not continue restoration until the ADC output level is
again below the recovery threshold. Once the PGA gain is
restored to its original value, it is not changed again unless the
ADC output value exceeds the attack threshold and the ALC
then enters attack mode. Care should be taken when using this
mode to choose values for the attack and recovery thresholds
that prevent excessive volume modulation caused by continuous
gain adjustments.

Limited Recovery Mode

Limited recovery mode offers a compromise between no recov-
ery and normal recovery modes. If the output level of the ADC
exceeds the attack threshold, then attack mode is initiated.
When attack mode has reduced the PGA gain to suitable levels,
the ALC attempts to recover the gain to its original level. If the
ADC output level exceeds the level set by the recovery threshold
bits, a counter is incremented (GAINCNTR). This counter is
incremented at intervals equal to the recovery time selection, if
the ADC has any excursion above the recovery threshold. If the
counter reaches its maximum value, determined by the
GAINCNTR bits in ALC Control Register 1, the PGA gain is
deemed suitable and no further gain recovery is attempted.
Whenever the ADC output level exceeds the attack threshold,
attack mode is reinitiated and the counter is reset.

Automatic Level Control (

The ADC record channel features a programmable automatic
level control block. This block monitors the level of the ADC
output signal and automatically reduces the gain, if the signal
the input pins causes the ADC output to exceed a preset limit.
This function can be useful to maximize the signal dynamic
range when the input level is not well defined. The PGA can b
used to amplify the unknown signal, and the ALC reduces the
gain until the ADC output is within the preset limits. This
results in m

Because the ALC block monitors the output of the ADC, the
volume control function should not be used. The ADC v
control scales the results from the ADC, and any distortion
caused by the input signal exceeding the input range of the

No Recovery Mode

By default, there is no gain recovery. Once the gain has bee
reduced, it

reduced

by toggling the ALCEN bit in ALC Control Register 1 o
writing any value to ALC Control Register 3. The latter option
more efficient, because it requires only one write operation to
reset the ALC function. No recovery mode prevents volume
modulation of the signal caused by adjusting the gain, which
can create undesirable artifacts in the signal. The gain can be
reduced but not recovered. Therefore, care should be taken that
spurious signals do not interfere with the input signal, because
these might trigger a ga

ADAV801

Rev. 0 | Page 17 of 56

le Rate

ecause

ital

ut reduces the oversampling ratio,

cted

o generate a separate 12.288 MHz

eat

Selecting a Samp

The output sample rate of the ADC is always ADC MCLK/256,
as shown in Figure 23. By default, the ADC modulator runs at
ADC MCLK/2. When the ADC MCLK exceeds 12.288 MHz,
the ADC modulator should be set to run at ADC MCLK/4. This
is achieved by setting the AMC (ADC Modulator Clock) bit in
the ADC Control Register 1. To compensate for the reduced
modulator clock speed, a different set of filters are used in the
decimator section ensuring that the sample rate remains
the same.

The AMC bit can also be used to boost the THD + N perform
ance of the ADC at the expense of dynamic range. The
improvement is typically 0.5 dB to 1.0 dB and works, b
selecting the lower modulator rate reduces the amount of dig

noise, improving THD + N, b
therefore reducing the dynamic range by a corresponding
amount.

For best performance of the ADC, avoid using similar
frequency clocks from separate sources in the ADAV801. For
example, running the ADC from a 12.288 MHz clock conne
to MCLKI and using the PLL t
clock for the DAC can reduce the performance of the ADC.
This is due to the interaction of the clocks, which generate b
frequencies that can affect the charge on the switch capacitors
of the analog inputs.

WAIT FOR SAMPLE

DECREASE GAIN BY 0.5dB

AND WAIT ATTACK TIME

IS SAMPLE

GREATER THAN ATTACK

THRESHOLD?

ABO

THRESHOLD?

IS A RECOVERY

MODE ENABLED?

SAMPLE

VE ATTACK

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

HAS GAIN BEEN

FULLY RESTORED?

YES

NORMAL RECOVERY

INCREASE GAIN BY 0.5dB

WAIT RECOVERY TIME

LIMITED RECOVERY

ATTACK MODE

04577-

006

IS SAMPLE

ABOVE ATTACK

THRESHOLD?

ARE ALL

SAMPLES BELOW

RECOVERY

THRESHOLD?

HAS GAIN BEEN

FULLY RESTORED?

IS GAINCNTR

AT MAXIMUM?

YES

INCREASE GAIN BY 0.5dB

INCREMENT

GAINCNTR

HAS RECOVERY

TIME BEEN
REACHED?

HAS RECOVERY

TIME BEEN

REACHED?

Figure 26. ALC Flow Diagram

ADAV801

Rev. 0 | Page 18 of 56

pair

28 steps

ded to remove high

e noise

nal

op amps, which might draw more than 50 µA or have dynamic
load changes, extra buffering should be used to preserve the
quality of the ADAV801 reference.

The digital input data source for the DAC can be selected from
a number of available sources by programming the appropriate
bits in the datapath control register. Figure 27 shows how the
digital data source and the MCLK source for the DAC are
selected. Each DAC has an independent volume register giving
256 steps of control, with each step giving approximately 0.375
dB of attenuation. Note that the DACs are muted by default to
prevent unwanted pops, clicks, and other noises from appearing
on the outputs while the ADAV801 is being configured. Each
DAC also has a peak-level register that records the peak value of
the digital audio data. Reading the register clears the peak.

electing a Sample Rate

Correct operation of

pon the data rate

)

by 2. This prevents the DAC engine from

running too fast. To compensate for the reduced MCLK rate, the
interpolator should be selected to operate in 4 × (DAC MCLK =
128 × f

). Similar combinations can be selected for different

sample rates.

DAC SECTION

The ADAV801 has two DAC channels arranged as a stereo
with single-ended analog outputs. Each channel has its own
independently programmable attenuator, adjustable in 1
of 0.375 dB per step. The DAC can receive data from the
playback or auxiliary input ports, the SRC, the ADC, or the DIR.
Each analog output pin sits at a dc level of VREF, and swings
1.0 V rms for a 0 dB digital input signal. A single op amp third-
order external low-pass filter is recommen
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth can cause high
frequency noise and tones to fold down into the audio band.
Care should be taken in selecting these components.

The FILTD and FILTR pins should be bypassed by external
capacitors to AGND. The FILTD pin is used to reduce th
of the internal DAC bias circuitry, thereby reducing the DAC
output noise. The voltage at the VREF pin, FILTR, can be use
to bias external op amps used to filter the output signals. For
applications in which the FILTR is required to drive exter

the DAC is dependent u

provided to the DAC, the master clock applied to the DAC, and
the selected interpolation rate. By default, the DAC assumes that
the MCLK rate is 256 times the sample rate, which requires an
8-times oversampling rate. This combination is suitable for
sample rates of up to 48 kHz.

For a 96 kHz data rate that has a 24.576 MHz MCLK (256 × f
associated with it, the DAC MCLK divider should be set to
divide the MCLK

04577-0-007

LL2

INTE

RNAL

LL1

INTE

RNAL

MCLKI

XIN

REG 0x76
BITS 75

REG 0x65
BITS 32

REG 0x63
BITS 53

DIR P

LL (2

× f

)

DIR P

LL (5

× f

)

DIR

PLAYBACK

AUXILIARY IN

ADC

MCLK

DIVIDER

DAC

MCLK

DAC

INPUT

Figure 27. Clock and Datapath Control on the DAC

MULTIBIT

MODULATOR

INTERPOLATOR

DAC

TO ZERO FLAG PINS

FROM DAC
DATAPATH
MULTIPLEXER

VOLUME/MUTE

CONTROL

PEAK

DETECTOR

ZERO DETECT

TO CONTROL

REGISTERS

OUTPUT

04577-0-008

Figure 28. DAC Block Diagram

ANALOG

ADAV801

Rev. 0 | Page 19 of 56

VERVIEW

le rate conversion, data can be

conv

or at

t sam

rates.

The sim

on is to use a zero-order hold between the two

m, T2

tional.

at f

S_OUT

are repeated or dropped, producing

pling process.

t r

S_OUT

ated images from the SIN(x)/x nature of the zero-

orde

es) of the zero-

order h

nfinite

he ratio of T2 to

T1 i

rom the

n never be eliminated. The error can be

tually interpolated by a factor of 2

SAMPLE RATE CONVERTER (SRC) FUNCTIONAL O

During asynchronous samp

erted at the same sample rate

differen

ple

plest approach to an asynchronous sample rate

conversi
samplers, as shown in Figure 29. In an asynchronous syste
is never equal to T1, nor is the ratio between T2 and T1 ra
As a result, samples
an error in the resam

The frequency domain shows the wide side lobes tha esult
from this error when the sampling of f

is convolved with

the attenu

r hold. The images at f

S_IN

(dc signal imag

old are i

ly attenuated. Because t

s an irrational number, the error resulting f

resampling at f

S_OUT

significantly reduced, however, through interpolation of t
input data at f

S_IN

. Therefore, the sample rate converter in t

ADAV801 is concep

04577-0-009

SPECTRUM OF

S_OUT

SAMPLING

S_OUT

2 ×

S_OUT

FREQUENCY RESPONSE OF

S_OUT

CONVOLVED

WITH ZERO-ORDER HOLD SPECTRUM

ZERO-ORDER

HOLD

S_IN

= 1/T1

S_OUT

= 1/T2

ORIGINAL SIGNAL

SAMPLED AT

S_IN

SIN(X)/X OF ZERO-ORDER HOLD

SPECTRUM OF ZERO-ORDER HOLD OUTPUT

OUT

Figure 29. Zero-Order Hold Used by f

S_ OUT

to Resample Data from f

S_IN

Conceptual High Interpolation Model

to suppress the

Interpolation of the input data by a factor of 2

involves placin

- 1) samples between each f

S_IN

sample. Figure 30 shows

both the time domain and the frequency domain of
interpolation by a factor of 2

. Conceptually, interpolation b

involves the steps of zero-stuffing (2

- 1) number of

samples between each f

S_IN

sample and convolving this

interpolated signal with a digital low-pass filter
images. In the time domain, it can be een at f

S_OUT

selects the

closest f

S_IN

× 2

sample from the zero-order hold, as opposed to

the nearest f

S_IN

sample in the case of no interpolation. This

significantly reduces the resampling error.

04577-0-010

S_IN

S_OUT

OUT

INTERPOLATE

BY N

LOW-PASS

FILTER

ZERO-ORDER

HOLD

TIME DOMAIN OF

S_IN

SAMPLES

TIME DOMAIN OUTPUT OF THE LOW-PASS FILTER

TIME DOMAIN OF

S_OUT

RESAMPLING

TIME DOMAIN OF THE ZERO-ORDER HOLD OUTPUT

Figure 30. SRC Time Domain

In the frequency domain shown in Figure 31, the interpolation
expands the frequency axis of the zero-order hold. The images
from the interpolation can be su ficiently attenuated by a good
low-pass filter. The images from the zero-order hold are now
pushed by

n point

a factor of 2

closer to the infinite attenuatio

of the zero-order hold, which is f

S_IN

× 2

. The images at the

zero-order hold are the determining factor for the fidelity of t
output at f

S_OUT

04577-0-011

S_IN

S_OUT

OUT

INTERPOLATE

BY N

LOW-PASS

FILTER

ZERO-ORDER

HOLD

FREQUENCY DOMAIN OF SAMPLES AT

S_IN

FREQUENCY DOMAIN OF THE INTERPOLATION

FREQUENCY DOMAIN OF

S_OUT

RESAMPLING

FREQUENCY DOMAIN
AFTER RESAMPLING

SIN(X)/X OF ZERO-ORDER HOLD

Figure 31. Frequency Domain of the Interpolation and Resampling

ADAV801

Rev. 0 | Page 20 of 56

The

mputed from the zero-order

× F/f

S_INTERP

)/(× F/f

S_INTERP

)

Hardware Model

The output rate of the low-pass filter in Figure 30 is the
interpolation rate:

× 192,000 kHz = 201.3 GHz

Sampling at a rate of 201.3 GHz is clearly impractical, not to
mention the number of taps required to calculate each
interpolated sample. However, because interpolation by 2

involves zero-stuffing 2

-1 samples between each f

S_IN

sample,

most of the multiplies in the low-pass FIR filter are by zero. A
further reduction can be realized, because only one interpolated
sample is taken at the output at the f

S_OUT

rate, so only one

convolution needs to be performed per f

S_OUT

period instead of

convolutions. A 64-tap FIR filter for each f

S_OUT

sample is

sufficient to suppress the images caused by the interpolation.

One difficulty with the above approach is that the correct
interpolated sample must be selected upon the arrival of

Because th

eriod, the

lyphase

aled. As the input sample rate rises over

the output sample rate, the antialiasing filter's cutoff frequency

's FIFO block adjusts the

left and right input samples and ores them for the FIR filter's
c
to the FIFO blo

l servo loop.

tion

aling

tal

worst-case images can be co

hold frequency response:

maximum image = sin (

where:

F is the frequency of the worst-case image that would be
2

× f

S_IN

± f

S_IN

/2.

S_INTERP

is f

S_IN

× 2

The following worst-case images would appear for f

S_IN

equal to

192 kHz:

Image at f

S_INTERP

- 96 kHz = -125.1 dB

Image at f

S_INTERP

+ 96 kHz = -125.1 dB

S_O

ere are 2

possible convolutions per f

S_OUT

arrival of the f

S_OUT

clock must be measured with an accuracy of

1/201.3 GHz = 4.96 ps. Measuring the f

S_OUT

period with a clock

of 201.3 GHz frequency is clearly impossible; instead, several
coarse measurements of the f

S_OUT

clock period are made and

averaged over time.

Another difficulty with the above approach is the number of
coefficients required. Because there are 2

possible convolu-

tions with a 64-tap FIR filter, there must be 2

coefficients for each tap, which requires a total of 2 coeffi-
cients. To reduce the number of coefficients in ROM, the SRC
stores a small subset of coefficients and performs a high order
interpolation between the stored coefficients.

The above approach works when f

S_OUT

> f

S_IN

. However, when

the output sample rate, f

S_OUT

, is less than the input sample rate

S_IN

, the ROM starting address, input data, and length of th

convolution must be sc

must be lowered, because the Nyquist frequency of the output
samples is less than the Nyquist frequency of the input samples.
To move the cutoff frequency of the antialiasing filter, the
coefficients are dynamically altered and the length of the
convolution is increased by a factor of (f

S_IN

S_OUT

This technique is supported by the Fourier transform propert
that, if f(t) is F(), then f(k × t) is F(/k). Thus, the range of
decimation is limited by the size of the RAM.

SRC Architecture

The architecture of the sample rate converter is shown in
Figure 32. The sample rate converter

onvolution cycle. The f

S_IN

counter provides the write address

ck and the ramp input to the digita

The ROM stores the coefficients for the FIR filter convolu
and performs a high order interpolation between the stored
coefficients. The sample rate ratio block measures the sample
rate for dynamically altering the ROM coefficients and sc
of the FIR filter length as well as the input data. The digi
servo loop automatically tracks the f

S_IN

and f

S_OUT

sample rates

and provides the RAM and ROM start addresses for the start of
the FIR filter convolution.

04577-0-012

RIGHT DATA IN

LEFT DATA IN

FIFO

ROM A

ROM B

DIGITAL

SERVO LOOP

S_IN

COUNTER

ROM C

ROM D

S_IN

S_OUT

SAMPLE RATE RATIO

SAMPLE

RATE RATIO

EXTERNAL

RATIO

INTERP

FIR FILTER

L/R DATA OUT

HIGH

ORDER

Figure 32. Architecture of the Sample Rate Converter

The FIFO receives the left and right input data and adjusts the
amplitude of the data for both the soft muting of the sample
rate converter and the scaling of the input data by the sample
rate ratio before storing the samples in the RAM. The input data
is scaled by the sample rate ratio, because, as the FIR filter
length of the convolution increases, so does the amplitude of the
convolution output. To keep the output of the FIR filter from
saturating, the input data is scaled down by multiplying it by
(f

S_OUT

S_IN

) when f

S_OUT

< f

S_IN

. The FIFO also scales the input

data for muting and unmuting of the SRC.

The RAM in the FIFO is 512 words deep for both left and right
channels. An offset to the write address provided by the f

S_IN

counter is added to prevent the RAM read pointer from
overlapping the write address. The minimum offset on the SRC
is 16 samples. However, the group delay and mute-in register
can be used to increase this offset.

ADAV801

Rev. 0 | Page 21 of 56

ut samples added to the write pointer of the

(512 - 16)/64 taps = 7.75

for short group delay and

(512 - 64)/64 taps = 7

for long group delay.

o of f

S_IN

S_OUT

The number of inp
FIFO on the SRC is 16 plus Bit 6 to Bit 0 of the group delay
register. This feature is useful in varispeed applications to
prevent the read pointer to the FIFO from running ahead of the
write pointer. When set, Bit 7 of the group delay and mute-in
register soft-mutes the sample rate. Increasing the offset of the
write address pointer is useful for applications in which small
changes in the sample rate ratio between f

S_IN

and f

S_OUT

are

expected. The maximum decimation rate can be calculated
from the RAM word depth and the group delay as

The digital servo loop is essentially a ramp filter that provides
the initial pointer to the address in RAM and ROM for the start
of the FIR convolution. The RAM pointer is the integer output
of the ramp filter, and the ROM is the fractional part. The
digital servo loop must provide excellent rejection of jitter on
the f

S_IN

and f

S_OUT

clocks, as well as measure the arrival of the

S_OUT

clock within 4.97 ps. The digital servo loop also divides

the fractional part of the ramp output by the rati
to dynamically alter the ROM coefficients when f

S_IN

> f

S_OUT

04577-0-013

DIR P

LL (2

)

ICLK2

ICLK1

REG 0x00
BITS 10

REG 0x76
BIT 0

REG 0x76

BIT 1

REG 0x62
BITS 76

DIR P

LL (5

)

DIR

PLAYBACK

AUXILIARY IN

ADC

MCLKI

XIN

SRC

MCLK

SRC

OUTPUT

SRC

INPUT

PLLINT2

PLLINT1

Figure 33. Clock and Datapath Control on the SCR

The digital servo loop is implemented with a multirate filter. To

ttle the digital servo loop filter more quickly upon startup or a

added to the

ample rate is

easonable value, the digital

During fast mode, the MUTE_OUT bi

e error

he u

at clicks

ght

pres

l audio

tput of

e mu

Bit 7 of he group delay and

l t

ged to

he MU

an be

n inter

when the SRC

ing sample rate

onve

ly.

S_IN

) × 2

ratio for

se
change in the sample rate, a fast mode has been
filter. When the digital servo loop starts up or the s
changed, the digital servo loop enters fast mode to adjust and
settle on the new sample rate. Upon sensing that the digital

servo loop is settling down to a r
servo loop returns to normal (or slow) mode.

t in the sample rat

regist r is asserted to let t

ser know th

or pops mi

ent in the digita

data. The ou

the SRC can

ted by asserting

mute registe

unti he SRC has chan

slow mode. T

TE_OUT bit

set to generate a

rupt

changes to

slow

ode, indicating that t e data is be

rted accurate

The frequency responses of the digital servo loop for fast mod
and slow mode are shown in Figure 34. The FIR filter is a 64-tap
filter when f

S_OUT

S_IN

and is (f

S_IN

S_OUT

) × 64 taps when f

S_IN

S_OUT

. The FIR filter performs its convolution by loading in the

starting address of the RAM address pointer and the ROM
address pointer from the digital servo loop at the start of the
f

S_OUT

period. The FIR filter then steps through the RAM by

decrementing its address by 1 for each tap, and the ROM
pointer increments its address by the (f

S_OUT

S_IN

> f

S_OUT

or 2

for f

S_OUT

S_IN

. Once the ROM address rolls

over, the convolution is completed.

04577-0-014

FREQUENCY (Hz)

MAGNITUDE

(dB)

20

40

60

80

100

120

140

160

180

200

0.01

0.1

100

10k

100k

SLOW MODE

FAST MODE

220

Figure 34. Frequency Response of the Digital Servo Loop. f

S_IN

is the X-Axis,

S_OUT

= 192 KHz, Master Clock is 30 MHz

The convolution is performed for both the left and right
channels, and the multiply accumulate circuit used for the
convolution is shared between the channels. The f

S_IN

S_OUT

sample rate ratio circuit is used to dynam cally alter the

in the ROM when f

S_IN

> f

S_OUT

. The ratio is

calculated by comparing the output of an f

S_OUT

counter to the

output of an f

S_IN

counter. If f

S_OUT

> f

S_IN

, the ratio is held at one.

, the sample rate ratio is updated, if it is different

by more than two f

S_OUT

periods from the previous f

S_OUT

to f

S_IN

comparison. This is done to provide some hysteresis to prevent

coefficients

If f

S_IN

> f

S_O

the filter length from oscillating and causing distortion.

ADAV801

Rev. 0 | Page 22 of 56

an external

PLL SECTION

The ADAV801 features a dual PLL configuration to generate
independent system clocks for asynchronous operation.
Figure 37 shows the block diagram of the PLL section. The PLL
generates the internal and system clocks from a 27 MHz clock.
This clock is generated either by a crystal connected between
XIN and XOUT, as shown in Figure 35, or from
clock source connected directly to XIN. A 54 MHz clock can
also be used, if the internal clock divider is used.

XTA

04577-0-015

XIN

XOU

Figure 35. Crystal Connection

Both PLLs (PLL1 and PLL2) can be programmed independently
and can accommodate a range of sampling rates (32/44.1/48
kHz) with selectable system clock oversampling rates of 256 and
384. Higher oversampling rates can also be selected by enabling
the doubling of the sampling rate to give 512 or 768 × f

ratios.

Note that this option also allows oversampling ratios of 256 or
384 at double sample r

The PLL outputs can be routed internally to act as clock sources
for the oth

, and so

on. The outputs of the PLLs are also available on the three
SYSCLK pins. Figure 38 shows how the PLLs can be configured
to provide the sampling clocks.

MCLK Selection

ates of 64/88.2/96 kH

er component blocks such as the ADC, DAC

Table 7. PLL Frequency Selection Options

PLL

Sample Rate (f

)

Normal f

Double f

32/44.1/48 kHz

256/384 × f

512/768 × f

64/88.2/96 kHz

256/384 × f

32/44.1/48 kHz

256/384 × f

512/768 × f

64/88.2/96 kHz

256/384 × f

Same as f

selected

512 × f

For PLL 2A

512 × f

The PLLs require some external components to operate
correctly. These c

6, form a loop

p and

ows

d as master clocks

r t

e ADAV801

e DAC or ADC.

nd gro

pins, which should be

t electri

se from being

ouplin

ns.

omponents, shown in Figure 3

filter that integrates the current pulses from a charge pum
produces a voltage that is used to tune the VCO. Good quali
capacitors, such as PPS film, are recommended. Figure 37 sh
a block diagram of the PLL section, including master clock
selection. Figure 38 shows how the clock frequencies at the
clock output pins, SYSCLK1 to SYSCLK 3, and the internal PLL
clock values, PLL1 and PLL2, are selected.

The clock nodes, PLL1 and PLL2, can be use
fo he other blocks in th

such as th

Th PLL has separate supply a

und

as c ean as possible to preven

cal noi

co erted into clock jitter by c

g onto the loop filter pi

04577-0-016

PLL BLOCK

3.3k

PLL_LFx

100nF

AVDD

6.8nF

Figure 36. PLL Loop Filter

04577-0-017

MCLKI

REG 0x

BIT

MCLKO

REG 0x74

BIT 5

G 0x74

BIT 4

REG 0x78

BIT 6

PHASE

DETECTOR

AND LOOP

FILTER

PLL1

SYSCLK1

SYSCLK2

SYSCLK3

PLL_LF2

XOUT

XIN

PLL_LF1

VCO

OUTPUT

SCALER N1

PHASE

DETECTOR

AND LOOP

FILTER

PLL2

VCO

OUTPUT

SCALER N2

OUTPUT

SCALER N3

Section Block Diagram

Figure 37. PLL

ADAV801

Rev. 0 | Page 23 of 56

04577-0-018

PLL1 MCLK

PLL2 MCLK

48kHz
32kHz

44.1kHz

256
384

REG 0x75
BITS 32

REG

REG 0x75
BIT 1

0x75

BIT 0

REG 0x77

BIT 0

PLL1

PLLINT1

SYSCLK1

×2

FS1

REG 0x75
BIT 5

REG 0x75

BIT 4

REG 0x77

BITS 21

76

PLL2

PLLINT2

SYSCLK2

REG 0
BITS

REG 0x74
BIT 0

SYSCLK3

48kHz
32kHz

44.1kHz

256
384

×2

FS2

FS3

256
512

Figure 38. PLL Clocking Scheme

SPDIF TRANSMITTER AND RECEIVER

The ADAV801 contains an integrated SPDIF transmitter and
receiver. The transmitter consists of a single output pin,
DITOUT, on which the biphase encoded data appears. The
SPDIF transmitter source can be selected from the different
blocks making up the ADAV801. Additionally, the clock source
for the SPDIF transmitter can be selected from the various clock
sources available in the ADAV801.

The receiver uses two pins, DIRIN and DIR_LF. DIRIN accepts
the SPDIF input data stream. The DIRIN pin can be configured
to accept a digital input level, as defined in the Specifications
section, or an input signal with a peak-to-peak level of 200 mV
minimum, as defined by the IEC60958-3 specification. DIR_LF
is a loop filter pin, required by the internal PLL, which is used to
recover the clock from the SPDIF data stream.

The components shown in Figure 42 form a loop filter, which
integrates the current pulses from a charge pump and produces
a voltage that is used to tune the VCO of the clock recovery
PLL. The recovered audio data and audio clock can be routed to
the different blocks of the ADAV801, as required. Figure 39
shows a conceptual diagram of the DIRIN block.

04577-0-019

SPDIF

* EXTERNAL CAPACITOR IS REQUIRED ONLY

FOR VARIABLE LEVEL SPDIF INPUTS.

COMPARATOR

REG 0x74
BIT 4

DIRIN

LEVEL

SPDIF

RECEIVER

Figure 39. DIRIN Block

04577-0-020

DIT
INPUT

DIT

PLAYBACK

AUXILIARY IN

SRC

REG 0x63

BITS 20

ADC

CHANNEL STATUS

AND USER BITS

DIR

DITOUT

Figure 40. Digital Output Transmitter Block Diagram

04577-0-021

DIR

DIRIN

AUDIO
DATA

RECOVERED
CLOCK

CHANNEL STATUS/
USER BITS

Figure 41. Digital Input Receiver Block Diagram

ADAV801

Rev. 0 | Page 24 of 56

04577-0-022

DIR BLOCK

DIR_LF

100nF

AVDD

6.8nF

Figure 42.

one

l Dig

udio

tand

ADAV801 can receive and tra

PDIF, AES/EBU

958 serial str

/EBU is a profe

958 has

sumer and pro

ta sheet is

tended to f

rds. Con

e full specification

e digita

audio control info

e-mark

d. This encoding me

content of the

itted signal. As c

in the

al data end up with m

e biphase-

encoded data, while 0s in

ta do not. Note

e biphase-mark encod

a transition

en bit bounda

DIR Loop Filter Comp

nts

Seria

ital A

Transmission S

ards

The

nsmit S

, and

IEC-

eams. SPDIF is a consumer audio standar

and AES

ssional audio standard. IEC-

both con

fessional definitions. This da

not in

ully define or to provide a tutorial for thes

standa

tact the international standards-setting bodies

for th

All thes

l audio communication schemes encode audio

data and

rmation using the biphas

metho

thod minimizes the dc

transm

an be seen from Figure 43, 1s

origin

idcell transitions in th

mark

the original da

that th

data always ha

betwe

ries.

04577-0-023

CLOCK

(2 TIMES BIT RATE)

BIPHASE-MARK

DATA

Figure 43. Biphase-Mark Encoding

Digital audio-communication schemes use preambles to

distinguish among channels (called subframes) and among
longer-term control information blocks (called frames).
Preambles are particular biphase-mark patterns, which contain
encoding violations that allow the receiver to uniquely
recognize them. These patterns and their relationship to frames
and subframes are shown in Table 8 and Figure 44.

Table 8. Biphase-Mark Encode Preamble

Biphase Patterns

Channel

11100010 or 00011101

Left

11100100 or 00011011

Right

11101000 or 00010111

Left and CS block start

04577-

0
2
4

PREAMBLES

LEFT CH

FRAME 191

FRAME 0

FRAME 1

RIGHT CH

LEFT CH

RIGHT CH

LEFT CH

RIGHT CH

SUB-

FRAME

SUB-

FRAME

Figure 44. Preambles, Frames, and Subframes

The biphase-mark encoding violations are shown in Figure 45.
Note that all three preambles include encoding violations.
Ordinarily, the biphase-mark en ding method results in a
polarity transition

between bit boundaries.

04577-0-025

PREAMBLE X

PREAMBLE Y

PREAMBLE Z

Figure 45. Preambles

The serial digital a

rganized

Bits

udio communication scheme is o

using a frame and subframe construction. There are two
subframes per frame (ordinarily the left and right channel).
Each subframe includes the appropriate 4-bit preamble, up to
24 bits of audio data, a validity (V) bit, a user (U) bit, a channel
status (C) bit, and an even parity (P) bit. The channel status bits
and the user bits accumulate over many frames to convey
control information. The channel status bits accumulate over a
192 frame period (called a channel status block). The user bits
accumulate over 1,176 frames when the interconnect is imple-
menting the so-called subcode scheme (EIAJ CP-2401). Th
organization of the channel status block, frames, and subframes
is shown in Table 9 and Table 10. Note that the ADAV801
supports the professional audio standard from a software
point of view only. The digital interface supports only
consumer mode.

Table 9. Consumer Audio Standard

Data

Address 7

6 5 4 3

Channel

Status

Emphasis

Copy-

Non-

Pro
Co

right

Audio

= 0

N + 1

Category Code

N + 2

Channel Number Source

Number

N + 3

Reserved

Clock

Accuracy

Sampling Frequency

N + 4

Reserved

Word Length

N + 5 to
(N + 23)

Reserved

N = 0x20 for receiver channel status buffer.
N = 0x38 for transmitter channel status buffer.

ADAV801

Rev. 0 | Page 25 of 56

Data

Bits

Table 10. Professional Audio Standard

Address 7

6 5 4 3

Sample

Frequency

Lock Emphasis

Non-

Audio

Pro/
Con

= 1

N + 1

User Bit Management

Channel Mode

N + 2

Alignm

Level

Use of Auxiliary Mode

ent

Source Word Length

Sample Bits

N + 3

Channel Identification

N + 4

Scal-

ing

Reference

Signal

Sample Frequency (f

)

Reserved

Digital Audio

N + 5

Reserved

N + 6

Alphanumeric Channel Origin Data--First Character

N + 7

Alphanumeric Channel Origin Data

N + 8

Alphanumeric Channel Origin Data

N + 9

el Origin Data--Last Character

Alphanumeric Chann

N + 1

ion Data--First Character

A hanumeric Channel Destinat

N + 11

Alphanumeric Channel Destination Data

N + 12

Alphanumeric Channel Destination Data

N + 1

phanumeric Channel Destination Data--Last Character

N + 14

Local Sample Address Code--LSW

N + 15

Local Sample Address Code

N + 16

Local Sample Address Code

N + 17

Local Sample Address Code--MSW

N + 18

Time of Day Code--LSW

N + 19

Time of Day Code

N + 20

Time of Day Code

N + 21

Time of Day Code--MSW

N + 22

Reliability Flags

Reserved

N + 23

Cyclic Redundancy Check Character (CRCC)

N = 0x20 for receiver channel status buffer.

are

organized into 24 bytes and have the interpretations shown in

the need for user intervention.

Receiver Section

The ADAV801 uses a double-buffering scheme to handle read-
ing channel status and user bit information. The channel status
bits are available as a memory buffer, taking up 24 consecutive
register locations. The user bits are read using an indirect
memory addressing scheme, where the receiver user- bit
indirect-address register is programmed with an offset to the

iver user bit data register can be read

read

N = 0x38 for transmitter channel status buffer.

The standards allow the channel status bits in each subframe to
be independent, but ordinarily the channel status bit in the two
subframes of each frame are the same. The channel status bits
are defined differently for the consumer audio standards and
the professional audio standards. The 192 channel status bits

Table 9 and Table 10.

The SPDIF transmitter and receiver have a comprehensive
register set. The registers give the user full access to the
functions of the SPDIF block, such as detecting nonaudio an
validity bits, Q subcodes, preambles, and so on. The channel
status bits as defined by the IEC60958 and AES3 specifications
are stored in register buffers for ease of use. An autobuffering
function allows channel status bits and user bits read by the
receiver to be copied directly to the transmitter block, removing

user bit buffer, and the rece
to determine the user bits at that location. Reading the receiv
user bit data register automatically updates the indirect address
register to the next location in the buffer. Typically, the receiver
user bit indirect-address register is programmed to zero (the
start of the buffer), and the receiver user bit data register is
repeatedly until all the buffer's data has been read. Figure 46 an
Figure 47 show how receiving the channel status bits and user
bits is implemented.

04577-0-026

SECONDBUFFER

RECEIVE

CHANNEL
STATUS A

(24 × 8 BITS)

DIRIN

CS BUFFER
(0x200x37)

CHANNEL
STATUS B

(24 × 8 BITS)

RxCSSWITCH

SPDIF

RECEIVE

BUFFER

FIRST BUFFER

Figure 46. Channel Status Buffer

04577-0-027

BUFFER

SPDIFIN

0...7

8...15

16...23

FIRST

0...7

8...15

16...23

USER-BIT

BUFFER

ADDRESS = 0x50

ADDRESS = 0x51

RECEIVER USER BIT

INDIRECT ADDRESS

REGISTER

RECEIVER USER BIT

DATA REGISTER

Figure 47. Receiver User Bit Buffer

The SPDIF receive buffer is updated continuously by the
incoming SPDIF stream. Once all the channel status bits f
block (192 for Channel A and 192 for Channel B) are recei

or the

ved,

This

d the

bi n the channel status switch buffer register

eth

equi

to be

fer is

bytes

g and

Because the chan
change, a software

T, is provided to

tify th

ost co

tatus

bits is available or

status

formation have changed from a previous block. The function

of the RxCSBINT is controlled by the RxBCONF3 bit in the
receiver buffer configuration register.

The size of the user bit buffer can be set by programming the
RxBCONF0 bit in the receiver buffer configuration register, as
shown in Table 11.

the bits are copied into the receiver channel status buffer.
buffer stores all 384 bits of channel status information, an
RxCSSWITCH

t i

determ es wh

er the Channel A or the Channel B status bits

are r

red

read. The receive channel status bit buf

lon

spans the address range from 0x20 to 0x37.

nel status bits of an SPDIF stream rarely

interrupt/flag bit, RxCSBIN

e h

ntrol that either a new block of channel s

that the first five bytes of channel

ADAV801

Rev. 0 | Page 26 of 56

er Bit Buffer Size

Table 11. RxBCONF3 Functionality

RxBCONF0

Receiver Us

384 bits with Preamble Z as the start of the block.

768 bits with Preamble Z as the start of the block.

The updating of the user bit buffer is controlled by Bits
RxBCONF21 and Bit 7 to Bit 4 of the channel status register, as
shown in Table 12 and Table 13.

Table 12. RxBCONF21 Functionality

RxBCONF

Bit 2

Bit 1

Receiver User Bit Buffer Configuration

User bits are ignored.

Update second buffer when first buffer is full.

1 0 Format according to Byte 1, Bit 4 to Bit 7, if

PRO bit is set. Format according to
IEC60958-3, if PRO bit is clear.

Table 13. Automatic User Bit Configuration

Bits

7 6 5 4

Automatic Receiver User Bit Buffer
Configuration

0 0 0 0 User

bits

are

ignored.

0 1 0 0 AES-18 format: the user bit buffer is treated in

the same way as when RxBCONF21 = 0b01.

1 0 0 0 User bit buffer is updated in the same way as

when RxBCONF21 = 0b01 and RxBCONF0 =
0b00.

1 1 0 0 User-defined format: the user bit buffer is

treated in the same way as when RxBCONF21
= 0b01.

When the user bit buffer has been filled, the RxUBINT
interrupt bit in the interrupt status register is set, provided that
the RxUBINT mask bit is set, to indicate that the buffer has new
information and can

se when the user data is formatted according

e and the

ed in

nel status buffer occupies

ing

r into the SPDIF transmitter buffer until

finished loading the buffers. This feature is typically

be read.

For the special ca
to the IEC60958-3 standard into messages made of information
units, called IUs, the zeros stuffed between each IU and each
message are removed and only the IUs are stored. Once the end
of the message is sensed by more that eight zeros between IUs,
the user bit buffer is updated with the complete messag
first buffer begins looking for the start of the next message.

Each IU is stored as a byte consisting of 1, Q, R, S, T, U, V, and W
bits (see the IEC60958-3 specification for more information).
When 96 IUs are received, the Q subcode of the IUs is stor
the Q subcode buffer, consisting of 10 bytes. The Q subcode is
the Q bits taken from each of the 96 IUs. The first 10 bytes
(80 bits) of the Q subcode contain information sent by CD, MD
and DAT systems. The last 16 bits of the Q subcode are used to
perform a CRC check of the Q subcode. If an error occurs in
the CRC check of the Q subcode, the QCRCERROR bit is set.
This is a sticky bit that remains high until the register is read.

Transmitter Operation

The SPDIF transmitter has a similar buffer structure to th
receive section. The transmitter chan
24 bytes of the register map. This buffer is long enough to store
the 192 bits required for one channel of channel status informa-
tion. Setting the TxCSSWITCH bit determines if the data
loaded to the transmitter channel status buffer is intended for
Channel A or Channel B. In most cases, the channel status bi
for Channel A and Channel B are the same, in which case
setting the Tx_A/B_Same bit reads the data from the trans-
mitter channel status buffer and transmits it on both channels.

Because the channel status information is rarely changed dur
transmission, the information contained in the buffer is
transmitted repeatedly. The Disable_Tx_Copy bit can be used to
prevent the channel status bits from being copied from the
transmitter CS buffe
the user has
used, if the Channel A data and Channel B data are different.
Setting the bit prevents the data from being copied. Clearing th
bit allows the data to be copied and then transmitted. Figure 48
shows how the buffers are organized.

04577-0-028

TxCSSWITCH

TRANSMIT

CS BUFFER
(0x380x4F)

CHANNEL
STATUS A

(24 × 8 BITS)

CHANNEL
STATUS B

(24 × 8 BITS)

DITOUT

SPDIF

TRANSMIT

BUFFER

Figure 48. Transmitter Channel Status Buffer

As with the receiver section, the transmitted user bits are als
double-buffered. This is required, be

cause, unlike the channel

out alignment to the Z preamble. If

itting until a

bits are 01.

ble 14. Tr

urations

BCONF2-1

status bits, the user bits do not necessarily repeat themselves.
The user bits can be buffered in various configurations, as listed
in Table 14. Transmission of the user bits is determined by th
state of the BCONF3 bit. If the bit is 0, the user bits begin
transmitting right away with
this bit is 1, the user bits do not start transm
Z preamble occurs when the TxBCONF21

ansmitter User Bit Buffer Config

Bit 2

Bit 1

Transmitter User Bit Buffer Configuration

Zeros are transmitted for the user bits.

Host writes user bits to the buffer until it is full.

1 0 Writes the user bits to the buffer in IUs

specified by IEC60958-3 and transmits them
according to the standard.

1 1 First 10 bytes of the user-bit buffer are

configured to store a Q subcode.

ADAV801

Rev. 0 | Page 27 of 56

Table 15. Transmitter User Bit Buffer Size

TxBCONF0 Buffer

Size

384 bits with Preamble Z as the start of the block.

768 bits with Preamble Z as the start of the block.

By using sticky bits and interrupts, the transmit buffers can
notify the host or microcontroller when the first user bit buffer
has been updated and when the second transmit user bit buffer
is full. The sticky bit, TxUBINT, is set when the transmit user bit
buffer has been updated and the second transmit user bit buffer
is ready to accept new user bits. The sticky bit, TxFBINT, is set
whenever the second transmit user bit buffer is full. Any new
writes to this buffer are ignored until the first transmit buffer is
updated. These two bits are located in the interrupt status
register. When the host reads the interrupt status register, these
bits are cleared. Interrupts for the TxUBINT and TxFBINT
sticky bits can be enabled by setting the TxUBMASK and
TxFBMASK bits, respectively, in the interrupt status
mask register.

04577-0-029

SPDIF 0

0...7

8...15

16...23

SECOND

BUFFER

0...7

8...15

16...23

USER-BIT

BUFFER

ADDRESS = 0x52

ADDRESS = 0x53

TRANSMITTER USER BIT

INDIRECT ADDRESS

REGISTER

TRANSMITTER USER BIT

DATA REGISTER

Figure 49. Transmitter User Bit Buffer

Autobuffering

The ADAV801 SPDIF receiver and transmitter sections have an
autobuffering mode allowing the channel status and user bits to
be copied automatically from the receiver to the transmitter
without user intervention. The channel status and user bits can
be independently selected for autobuffering using the
Auto_CSBits and Auto_UBits bits, respectively, in the autobuffer
register. When the receiver and transmitter are running at the
same sample rate, the transmitted channel status and user bits
are the same as the received channel-status and user bits.

In many systems, however, it is likely that the receiver and
transmitter are not running at the same frequency. When the
transmitter sample rate is higher than receiver sample rate, the
channel status and user bit block is sometimes repeated.
the transmitter sample rate is lower than the receiver sample

te, the channel status and user bit blocks might be dropped.

ecause the first five bytes of the channel status are typically

constant, they can be repeated or dropped with no information
loss. However, if the PRO bit in the channel status is set and the
local sample address code and time-of-day code bytes contain

958-3

sent

or repeating messages. Because zero-stuffing

essages to be subtracted, the zeros

racted as well. The Zero_Stuff_IU bit in the

rupt.

ach interrupt in the interrupt status register has an associated

mask bit in the interrupt status mask register. The interrupt
mask bit must be set for the corresponding interrupt to be
generated. This feature allows the user to determine which
functions should be responded to.

The dual function pin ZEROL/INT can be set to indicate the
presence of no audio data on the left channel or the presence of
an interrupt set in the interrupt status register. As shown in
Table 16, the function of this pin is selected by the INTRPT bit
in DAC Control Register 4.

Table 16. ZEROL/INT Pin Functionality

INTRPT Pin

Functionality

When

ra
B

information, these bytes might be repeated or dropped, in
which case information can be lost. It is up to the user to
determine how to handle this case.

When the user bits are transmitted according to the IEC60
format, the messages contained in the user bits can still be
without dropping
is allowed between IUs and messages, zeros can be added or
subtracted to preserve the messages. When the transmitter
sample rate is greater than the receiver sample rate, extra zeros
are stuffed between the messages. When the sample rate of the
transmitter is less than the sample rate of the receiver, the zero
stuffed between the messages are subtracted. If there are not

en the m

enough zeros betwe
between IUs are subt
autobuffer register enables the adding or subtracting of zeros
between messages.

Interrupts

The ADAV801 provides interrupt bits to indicate the presence
of certain conditions that require attention. Reading the
interrupt status register allows the user to determine if any of
the interrupts have been asserted. The bits of the interrupt
status register remain high, if set, until the register is read. Two
bits, SRCError and RxError, indicate interrupt conditions in the
sample rate converter and an SPDIF receiver error, respectivel
Both these conditions require a read of the appropriate error
register to determine the exact cause of the inter

Pin functions as a ZEROL flag pin.

Pin functions as an interrupt pin.

SERIAL DATA PORTS

The ADAV801 contains four flexible serial ports (SPORTs) to

ta transfer to and from the codec. All four SPORTs are

independent and can be configured as master or slave ports. In
slave mode, the xLRCLK and xBCLK signals are inputs to the
serial ports. In master mode, the serial port generates the
xLRCLK and xBCLK signals. The master clock for the SPORT
can be selected from a number of sources, as shown in
Figure 50.

allow da

ADAV801

Rev. 0 | Page 28 of 56

04577-0-031

REG 0x76

BITS 42

DIR PLL (512 ×

)

DIR PLL (256 ×

)

PLLINT1
PLLINT2

MCLKI

XIN

ICLK1
ICLK2

PLL CLOCK

REG 0x06
BITS 43

MCLK

ADC

OUTPUT

PORT

OLRCLK

OBC
OSDATA

REG 0x76

BITS 75

DIR PLL (512 ×

)

DIR PLL (256 ×

)

PLLINT1
PLLINT2

MCLKI

XIN

ICLK1
ICLK2

PLL CLOCK

REG 0x04
BITS 4-3

MCLK

DAC

INPUT

PORT

ILRCLK
IBCLK
ISDATA

REG 0x77

BITS 43

REG 0x00

BITS 32

REG 0x00

BITS 10

REG 0x00

BITS 45

REG 0x76

BITS 10

MCLKI

XIN

PLLINT1
PLLINT2

ICLK1

ICLK2

DIR PLL (512 ×

)

DIR PLL (256 ×

)

REG 0x00

BITS 1-0

MCLKI

XIN

PLLINT1
PLLINT2

DIVIDER

SRC

MCLK

Figure 50. SPORT Clocking Scheme

le,

MCLKI input to ensure that the

C and serial port are

synchronized.

The SPORTs can be set

ive data in I

S, left-

justified or right-justified formats with different word lengths
by programming the appropriate bits in the playback register,
auxiliary input port register, record register, and auxiliary
output port-control register. Figure 51 is a timing diagram of
the serial data port formats.

Clocking Scheme

The ADAV801 provides a flexible choice of on-chip and off-
chip clocking sources. The on-chip oscillator with dual PLLs is
intended to offer complete system clocking requirements for
use with available MPEG encoders, decoders, or a combination
of codecs. The oscillator function is designed for generation of a
27 MHz video clock from a 27 MHz crystal connected between
the XIN and XOUT pins. Capacitors must also be connected
between these pins and DGND, as shown in Figure 35. The
capacitor values should be specified by the crystal manufacturer.
A square wave version of the crystal clock is output on the
MCLKO pin. If the system has a 27 MHz clock available, this
clock can be connected directly to the XIN pin.

Care should be taken to ensure that the clock rate is appropriate
for whatever block is connected to the serial port. For examp
if the ADC is running from the MCLKI input at 256 × f

, then

the master clock for the SPORT should also run from the

to transmit or rece

04577-0-030

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LRCLK

BCLK

SDATA

LSB

LEFT CHANNEL

RIGHT CHANNEL

LEFT CHANNEL

RIGHT CHANNEL

MSB

RIGHT-JUSTIFIED MODE -- SELECT NUMBER OF BITS PER CHANNEL

S MODE -- 16 BITS TO 24 BITS PER CHANNEL

LEFT-JUSTIFIED MODE -- 16 BITS TO 24 BITS PER CHANNEL

Figure 51. Serial Data Modes

ADAV801

Rev. 0 | Page 30 of 56

ADAV801 has a d

cated contro

ort to allow access to

AV801. Each of the internal

ght bits w

s reserved

these bits shoul

ACE

ontrol of the ADAV8

l port is

ycle of data transfer c

s. Figure 53 shows the

rmat of an SPI write

The transfer of

ata is initiated on the

ATCH. The data

resented on the first s

ents the register

rite bit.

f data are loaded to th

provided. If this bit is

h, a read operation is indicated. The contents of the register

ess are clocked ou

n on the following eight

CLKs. For a read ope

ts after the read/write

BLOCK EADS AN

The ADAV801 provides the user with the ability to write to or
read from a block of registers in one continuous operation. In
SPI mode, the CLATCH line should be held low for longer than
the 16 CCLK periods to use the block read/write mode. For a
write operation, once the LSB has been clocked into the
ADAV801 on the 16th CCLK, the register address as specified
by the first seven bits of the write operation is incremented and
the next eight bits are clocked into the next register address.

The read operation is similar. Once the LSB of a read register
operation has been clocked out, the register address is
incremented and the data from the next register is clocked out
on the following eight CCLKs. Figure 55 and Figure 56 show the
timing diagrams for the block write and read operations.

INTERFACE CONTROL

The

edi

l p

the internal registers of the AD
registers is ei

ide. Where bits are described a

(RES),

d be programmed as zero.

SPI INTERF

01 is via an SPI-compatible serial port

The SPI contro

a 4-wire serial control port with one

onsisting of 16 bit

/read of the ADAV801.

falling edge of CL

even CCLKs repres

address read/w

If this bit is low, the following eight bits

e register address

hig
addr

t on the COUT pi

ration, the data bi

bits are ignored.

D WRITES

CLATCH

CCLK

CIN

D14

COUT

D15

04577-0-033

SPI Serial Port Timing Diagram

Figure 53.

R/W

ADDRESS [6:0]

DATA [7:0]

04577-0-036

re 54. SPI C

orm

REGISTER DATA

REGISTER + 1 DATA

REGISTER + 2 DATA

Figu

ontrol Word F

04577-0-034

REGISTER

R/W = 0

8 BITS

CLATCH

CIN

8 BITS

Figure 55. SPI Block Write Operation

REGISTER DATA

REGISTER + 1 DATA

REGISTER + 2 DATA

04577-0-035

REGISTER

R/W = 1

8 BITS

CLATCH

CIN

DON'T CARE

Figure 56. SPI Block Read Operation

OUT

ADAV801

Rev. 0 | Page 31 of 56

IV1

IV0

DIV1

Table 17. SRC and Clock Control Registe

SRCD

CLK2

CLK2DIV0

CLK1DIV1

CLK1DIV0 MCLKSEL1 MCLKSEL0

7 6 5 4 3 2 1 0

ADDRESS = 0000000 (0x00)

SRCDIV10

Divides the SRC master clock.

00 = SRC master clock is not divided.

vided by 1.5.

is divided by 2.

is divided by 3.

e by 1.5.

ck 1 (ICLK1).

01 = Divide by 1.5.
10 = Divide by 2.

selection

e SRC m

= Internal C

k 1.

ernal Clock 2.

6 × f

01 = SRC master clock is di

10 = SRC master clock

11= SRC master clock

CLK2DIV10

Clock divider for Internal Clock 2 (ICLK2).

00 = Divide by 1.

01 = Divid

10 = Divide by 2.

11 = Divide by 3.

CLK1DIV10

Clock divider for Internal Clo

00 = Divide by 1.

11 = Divide by 3.

MCLKSEL10

Clock

for th

aster clock.

loc

01 = Int

10 = PLL recovered clock (512 × f

11 = PLL recovered clock (25

Table 18. SPDIF Loop

RES RES RES RES RES TxMUX

back Control Register

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 0000011 (0x03)

TxMUX

Selects the source for SPDIF output (DITOUT).

0 = SPDIF transmitter, normal mode.

1 = DIRIN, loopback mode.

Table 19. Playback Port Control Register

CLKSRC0

SPMODE2

SPMODE1

SPMODE0

RES RES RES CLKSRC1

7 6 5 4 3 2 1 0

ADDRESS = 0000100 (0x04)

CLKSRC10

Selects the clock source for generating the ILRCLK and IBCLK.

00 = Input port is a slave.

01 = Recovered PLL clock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE20

Selects the serial format of the playback port.

000 = Left-justified.

001 = I

100 = 24-bit, right-justified.

101 = 20-bit, right-justified.

110 = 18-bit, right-justified.

111 = 16-bit, right-justified.

ADAV801

Rev. 0 | Page 32 of 56

Table 20. Auxiliary Input Port Register

RES RES RES CLKSRC1

CLKSRC0

SPMODE

SPMODE1

SPMODE0

7 6 5 4 3 2 1 0

ADDRESS = 0000101 (0x05)

CLKSRC10

Selects the clock source for generating the IAUXLRCLK and IAUXBCLK.

00 = Input port is a slave.

01 = Recovered PLL cock.

10 = Internal Clock 1.

11 = Internal Clock 2.

SPMODE20

ut port.

tified.

right-justified.
right-justified.

ustified.

Selects the serial format of auxiliary inp

000 = Left-jus

001 = I

100 = 24-bit,

101 = 20-bit,

110 = 18-bit, right-justified.

111 = 16-bit, right-j

Table 21. Record Por

RES

CLKSRC1

CLKSRC0

WLEN1 WLEN0 SPMODE1

SPMODE0

t Control Register

7 6 5 4 3 2 1 0

ADDRESS = 0000110 (0x06)

CLKSRC10

Selects the clock source for gen

RCLK and OBCLK.

erating the OL

00 = Record port is a slave.

covered PLL clock.

lock 2.

l output word length.

record port.

01 = I

10 = Reserved.

11 = Right-justified.

01 = Re

10 = Internal Clock 1.

11 = Internal C

WLEN10

Selects the seria

00 = 24 bits.

01 = 20 bits.

10 = 18 bits.

11 = 16 bits.

SPMODE10

Selects the serial format of the

00 = Left-justified.

ADAV801

Rev. 0 | Page 33 of 56

RES

0 SPMO

MODE0

Table 22. Auxiliary Output Port Register

RES

CLKSR

KSRC0

WLEN

DE1

7 6 5 4 3 2 1 0

ADDRESS = 0000111 (0x07)

CLKSRC10

CLK.

Selects the clock source for generating the OAUXLRCLK and OAUXB

00 = Auxiliary record port is a slave.

01 = Recovered PLL clock.

ecord port.

10 = Internal Clock 1.

11 = Internal Clock 2.

WLEN10

Selects the serial output word length.

00 = 24 bits.

01 = 20 bits.

10 = 18 bits.

11 = 16 bits.

SPMODE10

Selects the serial format of the auxiliary r

00 = Left-justified.

01 = I

10 = Reserved.

11 = Right-justified.

Table 23. Group Dela

GRPDLY60

y and Mute Register

MUTE_SRC

6, 5, 4, 3, 2, 1, 0

ADDRESS = 0001000

(0x08)

MUTE_SRC

Soft-mutes the output of the sample rate converter.

0 = No mute.

y to the sample rate converter FIR filter by GRPDLY60 inpu

ples.

00000 = No de

1 = 1 sample delay.

1 = Soft-mute.

GRPDLY60

Adds dela

t sam

lay

000000

0000010 = 2 sample delay.

1111110 = 126 sample delay.

1111111 = 127 sample delay.

ADAV801

Rev. 0 | Page 34 of 56

OCK RxCLK1

Table 24. Receiver Configuration 1 Register

NOCL

TO_

DEEMPH

ERR10

LOCK10

6, 5

3, 2

1, 0

ADDRESS = 0001001 (0x09)

NOCLOCK

Selects the source of the receiver clock when the PLL is not locked.

clock.

ata from the receiver based on the channel status information.

should take, if the receiver detects a parity or biphase error.

OCK10

tion the receiver should take, if the PLL loses lock.

11 = Soft-mute of the last valid audio sample.

0 = Recovered PLL clock is used.

1 = ICLK1 is used.

RxCLK10

Determines the oversampling ratio of the recovered receiver clock.

00 = RxCLK is a 128 × f

recovered clock.

01 = RxCLK is a 256 × f

recovered clock.

10 = RxCLK is a 512 × f

recovered

11 = Reserved.

AUTO_DEEM

Automatically de-emphasizes the d

0 = Automatic de-emphasis is disabled.

1 = Automatic de-emphasis is enabled.

ERR10

Defines what action the receiver
00 = No action is taken.
01 = Last valid sample is held.
10 = Invalid sample is replaced with zeros.
11 = Reserved.

Defines what ac

00 = No action is taken.

01 = Last valid sample is held.

10 = Zeros are sent out after the last valid sample.

Table 25. Receiver Co

ration 2 Register

SP_PL

SP_PLL_

SEL

RES RES NO

NONAUDIO

NO_VALIDITY

nfigu

RxMUTE

L 10

3 2 1

ADDRESS = 0001010 (0x0A)

RxMUTE

Hard-mutes the audio output for the AES3/SPDIF receiver.

0 = AES3/SPDIF receiver is not muted.

1 = AES3/SPDIF receiver is muted.

SP_PLL

AES3/SPDIF receiver PLL accepts a left/right clock from one of the four serial ports as the PLL reference clock.

ES3/SPDIF preambles is the reference clock to the PLL.

ports is the reference clock to the PLL.

reference clock to the PLL when SP_PLL is set.

NONAUDIO

er is not allowed into the sample rate converter

efined by the IEC61937 standard, then the data from

receiver is not allowed into the SRC regardless of the state of this bit.

the SRC.

s not allowed into the SRC, if the NONAUDIO bit is set.

the AES3/SPDIF receiver is not allowed into the SRC.

0 = AES3/SPDIF receiver data is sent to the SRC.

1 = Data from the AES3/SPDIF receiver is not allowed into the SRC, if the VALIDITY bit is set.

0 = Left/right clock generated from the A

1 = Left/right clock from one of the serial

SP_PLL_SEL10

Selects one of the four serial ports as the

00 = Playback port is selected.

01 = Auxiliary input port is selected.

10 = Record port is selected.

11 = Auxiliary output port is selected.

When the NONAUDIO bit is set, data from the AES3/SPDIF receiv

NAUDIO data is due to DTS, AAC, and so on, as d

(SRC). If the NO
the AES3/SPDIF

0 = AES3/SPDIF receiver data is sent to
1 = Data from the AES3/SPDIF receiver i

NO_VALIDITY

When the VALIDITY bit is set, data from

ADAV801

Rev. 0 | Page 35 of 56

RES F5

RxBCONF4

NF3 RxB

RxBCONF0

Table 26. Receiver Buffer Configuration Register

RES

RxBCON

RxBCO

CONF21

7 6 5 4 3 2,

ADDRESS = 0001011 (0x0B)

RxBCONF5

If the user bits are formatted according to the IEC60958-3 standard and the DAT category is detected, the user bit

enabled only when there is a change in the start (ID) bit.

interrupt is

0 = User bit interrupt is enabled in normal mode.

If the DAT category is detected, the user bit interrupt is enabled only if there is a change in the start (ID) bit.

termines whether Channel A and Channel B user bits are stored in the buffer together or separated

and B.

eceiver channel status is read, which is 192 audio frames.

of the receiver channel status block changes from the previous channel

IEC60958-3 standard.

xBCONF0

Defines the user bit buffer size, if RxBCONF21 = 01.

rt of the buffer.

1 =

RxBCONF4

This bit de
between A

0 = User bits are stored together.

1 = User bits are stored separately.

RxBCONF3

Defines the function of RxCSBINT.

0 = RxCSBINT are set when a new block of r

1 = RxCSBINT is set only if the first five bytes
status block.

RxBCONF21

Defines the user bit buffer.

e ignored.

00 = User bits ar

01 = Updates the second user bit buffer when the first user bit buffer is full.
10 = Formats the received user bits according to Byte 1, Bit 4 to Bit 7, of the channel status, if the PRO bit is set. If the
PRO bit is not set, formats the user bits according to the

11 = Reserved.

0 = 384 bits with Preamble Z as the sta

8 b

h Pr

1 = 76

its wit

eamble Z as the

rt of the buffer.

Table 27. Transmitter Control Register

RES

TxVALIDITY

TxRATIO20

TxCLKSEL10

TxENABLE

5, 4, 3

2, 1

ADDRESS = 0001100 (0x0C)

TxVALIDITY

This bit is used to set or clear the VALIDITY bit in the AES3/SPDIF transmit stream.

0 = Audio is suitable for D/A conversion.

1 = Audio is not suitable for D/A conversion.

TxRATIO20

Determines the AES3/SPDIF transmitter to AES3/SPDIF receiver ratio.

00 = Internal Clock 1 is the cl
01 = Internal Clock 2 is the clock source for the transmitter.

ce for the transmitter.

3/SPDIF transmitter is disabled.

000 = Transmitter to receiver ratio is 1:1.

001 = Transmitter to receiver ratio is 1:2.

010 = Transmitter to receiver ratio is 1:4.

101 = Transmitter to receiver ratio is 2:1.

110 = Transmitter to receiver ratio is 4:1.

TxCLKSEL10

Selects the clock source for the AES3/SPDIF transmitter.

ock source for the transmitter.

10 = Recovered PLL clock is the clock sour

11 = Reserved.

TxENABLE

Enables the AES3/SPDIF transmitter.

0 = AES

1 = AES3/SPDIF transmitter is enabled.

ADAV801

Rev. 0 | Page 36 of 56

TxBCONF3

TxBCONF21 TxBCONF0

Table 28. Transmitter Buffer Configuration Register

IU_Zeros30

7, 6, 5, 4

2, 1

ADDRESS = 0001101 (0x0D)

IU_Zeros30

Determines the number of zeros to be stuffed between IUs in a message up to a maximum of 8.

0000 = 0.

11 = 7.

ser bits.

size is configured according to TxBCONF0.

ter user bits when TxBCONF21 is 01.

s with Preamble Z as the start of the buffer.

0001 = 1.

...

1000 =

TxBCONF3

Transmitter user bits can be stored in separate buffers or stored together.

0 = User bits are stored together.

1 = User bits are stored separately.

TxBCONF21

Configures the transmitter user bit buffer.

00 = Zeros are transmitted for the u

01 = Transmitter user bit buffer

10 = User bits are written to the transmit buffer in IUs specified by the IEC60958-3 standard.

11 = Reserved.

TxBCONF0

Determines the buffer size of the transmit

0 = 384 bits with Preamble Z as the start of the buffer.

1 = 768 bit

Table 29. Channel Status Switch Buffer and Transmitter

Disable_Tx_Copy

RES RES TxCSSWITCH RxCSSWITCH

RES RES Tx_A/B_Same

7 6 5

3 2 1

ADDRESS = 0001110 (0x0E)

Tx_A/B_Same

Transmitter Channel Status A and B are the same. The transmitter reads only from the Channel Status A buffer and

s the data into t

place

he Channel Status B buffer.

0 = Channel status for A and B are separate.

nnel status for A and B are the same.

nsmitter channel status buffer to the SPDIF transmitter

0 = Copying transmitter channel status is enabled.

tus is disabled.

channel status buffer.

itter Channel Status A buffer can be accessed at address locations 0x38 through 0x4F.

yte Transmitter Channel Status B buffer can be accessed at address locations 0x38 through 0x4F.

0 = 24-byte Receiver Channel Status A buffer can be accessed at address locations 0x20 through 0x37.
1 = 24-byte Receiver Channel Status B buffer can be accessed at address locations 0x20 through 0x37.

1 = Cha

Disable_Tx_Copy

Disables the copying of the channel status bits from the tra
buffer.

1 = Copying transmitter channel sta

TxCSSWITCH

Toggle switch for the transmit

0 = 24-byte Transm

1 = 24-b

RxCSSWITCH

Toggle switch for the receive channel status buffer.

Table 30. Transmitte

t Significant Byte

r Message Zeros M

ros70

MSBZe

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0001111 (0x0F)

MSBZeros70

Most significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets).
Default = 0x00.

ADAV801

Rev. 0 | Page 37 of 56

icant Byte

Table 31. Transmitter Message Zeros Least Signif

LSBZeros70

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010000 (0x10)

LSBZeros70

Least significant byte of the number of zeros to be stuffed between IEC60958-3 messages (packets). Default = 0x09.

able 32. Autobuffer Register

Stuff_IU

Auto_UBits

Auto_CSBits

IU_Zeros30

RES

Zero_

7 6 5 4 3,

ADDRESS = 0010001 (0x11)

Zero_Stuff_IU

Enables the addition or subtraction of zeros between IUs during autobuffering of the user bits in IEC60958-3 format.

0 = No zeros added or subtracted.
1 = Zeros can be added or subtracted between IUs.
Enables the user bits to be autobuffered

Auto_UBits

between the AES3/SPDIF receiver and transmitter.

0 = User bits are not autobuffered.
1 = User bits are autobuffered.

ts to be autobuffered between the AES3/SPDIF receiver and transmitter.

s are not autobuffered.

bits are autobuffered.

maximum number of zero-stuffing to be added between IUs while autobuffering up to a maximum of 8.

0111 = 7.

Auto_CSBits

Enables the channel status bi

0 = Channel status bit

1 = Channel status

IU_Zeros30

Sets the

0000 = 0.
0001 = 1.

...

1000 = 8.

33. Sample Rat

SRCRATIO14SRCRATIO08

Table

e Ratio MSB egister (Re

Only)

RES

6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010010 (0x12)

SRCRATIO1408

Seven most significant bits of the15-bit sample rate ratio.

Table 34. Sam

ple Rate Ratio LSB Register (Read Only)

SRCRATIO07SRCRATIO00

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010011 (0x13)

SRCRATIO0700

Eight least significant bits of the15-bit sample rate ratio.

Table 35. Preamble-C

PRE_C15PRE_C08

MSB Register (Read Only)

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010100 (0x14)

PRE_C1508

Eight most significant bits of the 16-bit Preamble-C, when nonaudio data is detected according to the IEC60937
standard; otherwise, bits show zeros.

ADAV801

Rev. 0 | Page 38 of 56

d Only)

PRE_C07PRE_C00

Table 36. Preamble-C LSB Register (Rea

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010101 (0x15)

PRE_C0700

Eight least signif

nt bits of th

-bit Preamb -C, when nonaudio data is detected according to the IEC60937

d; otherwise, bits show zeros.

ica

e 16

standar

Table 37. Preamble-D M

SB Register (Read Only)

E_D15PRE_D08

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010110 (0x16)

PRE_D1508

nonaudio data is detected according to the IEC60937

nonaudio is used, this becomes the eight most significant bits

ght most significant bits of the 16-bit Preamble-D, when
andard; otherwise, bits show zeros. When subframe

the 16-bit Preamble-C of Channel B.

Table 38. Preamble-D LSB Register (Read Only)

PRE_D07PRE_D00

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 0010111 (0x17)

PRE_D0700

mble-D, when nonaudio data is detected according to the IEC60937

standard; otherwise, bits

becomes the eight most significant bits

ght least significant bits of the 16-bit Prea

show zeros. When subframe nonaudio is used, this

the 16-bit Preamble-C of Channel B.

Table 39. Receiver Erro

amble

CRCError NoStream BiPhase/

Parity Lock

r Register (Read Only)

Validity

Emphasis

NonAudio

Pre

NonAudio

3 2 1

6 5 4

ADDRESS = 0011000 (0x18)

RxValidity

ived stream.

is is the VALIDITY bit in the AES3 rece

Emphasis

This bit is set, if the audio data is pre-emphasized. Once it has been read, it remains high and does not generate an
interrupt unless it changes state.

onaudio) is set. Once it has been read, it does not generate another

upt unle

data bec

audio or

pe of no

nAudio

is bit is set,

e audio da

s nonaudio due to the det

ion of a pream

. The nonau

preamble type register

s what type of preamble was detected. Once read, it remains in its state and does not generate an interrupt

ster

NonAudio

This bit is set, when Channel Status Bit 1 (n
interr

ss the

omes

the ty

naudio data c

nges.

No
Preamble

indicate

if th

ta i

ect

ble

dio

unless it changes state.
This bit is the error flag for the channel status CRCError check. This bit does not clear until the receiver error regi

CRCError

is read.
This bit is set, if there is no AES3/SPDIF stream present at the AES3/SPDIF receiver. Once read, it remains high and

NoStream

does not generate an interrupt unless it changes state.
This bit is set, if a biphase or parity error occurred in the AES3/SPDIF stream. This bit is not cleared until the register is

BiPhase/Parity

read.
This bit is set, if the PLL has locked or cleared when the PLL loses lock. Once read, it remains in its state and does not
generate an interrupt unless it changes state.

Lock

ADAV801

Rev. 0 | Page 39 of 56

RxValid

Emphasis
Mask

nAudio

Mask

onA

Preamble
Mask

CRCError
Mask

Stream

Mask

BiPhas
Parity
Mask Lock

Mask

Table 40. Receiver Error Mask Register

Mask

ity

udio

7 6 5 4 3 2 1 0

ADDRESS = 0011001 (0x19)

RxValidity Mask

rating an interrupt.

Masks the RxValidity bit from gene

0 = RxValidity bit does not generate an interrupt.

terrupt.

an interrupt.

0 = NonAudio bit does not generate an interrupt.
1 = NonAudio bit generates an interrupt.

nAudio preamble bit from generating an interrupt.

0 = NonAudio preamble bit does not gene

e an interru

onAudio preamble bit generates an interrupt.

ask

NoStream Mask

BiPhase/Parity Mask

an interrupt.

1 = RxValidity bit generates an interrupt.

Emphasis Mask

Masks the emphasis bit from generating an in

0 = Emphasis bit does not generate an interrupt.

1 = Emphasis bit generates an interrupt.

NonAudio Mas

Masks the NonAudio bit from generating

NonAudio Preamble

Masks the No

Mask

rat

pt.

1 = N

CRCError M

Masks the CRCError bit from generating an interrupt.
0 = CRCError bit does not generate an interrupt.

1 = CRCError bit generates an interrupt.
Masks the NoStream bit from generating an interrupt.

0 = NoStream bit does not generate an interrupt.

1 = NoStream bit generates an interrupt.
Masks the BiPhase/Parity bit from generating

0 = BiPhase/Parity bit does not generate an interrupt.
1 = BiPhase/Parity bit generates an interrupt.

Lock Mask

Masks the Lock bit from generating an interrupt.

0 = Lock bit does not generate an interrupt.
1 = Lock bit generates an interrupt.

Table 41. Sample Rate Co

RES RES RES RES TOO_SLOW

OVRL

OVRR

MUTE_IND

nverter Error Register (Read Only)

7 6 5 4 3

2 1 0

ADDRESS = 0011010 (0x1A)

TOO_SLOW

This bit is set, when the clock to the SRC is too slow, that is, there are not enough clock cycles to complete the
internal convolution.

OVRL

This bit is set, when the left output data of the sample rate converter has gone over the full-scale range and has been
clipped. This bit is not cleared until the register is read.

OVRR

This bit is set, when the right output data of the sample rate converter has gone over the full-scale range and has
been clipped. This bit is not cleared until the register is read.

MUTE_IND

Mute indicated. This bit is set, when the SRC is in fast mode and clicks or pops can be heard in the SRC output data.
The output of the SRC can be muted, if required, until the SRC is in slow mode. Once read, this bit remains in its state
and does not generate an interrupt until it has changed state.

ADAV801

Rev. 0 | Page 40 of 56

sk Register

RES RES RES RES OVRL

Mask

Table 42. Sample Rate Converter Error Ma

RES

OVRR

MUT

IND

MASK

7 6

3 2

ADDRESS = 0011011 (0x1B)

OVRL Mask

Masks the OVRL from generating an interrupt.

0 = OVRL bit does not generate an interrupt.

1 = OVRL bit generates an interrupt.

OVRR Mask

Masks the OVRR from generating an interrupt.

ASK

interrupt.

0 = OVRR bit does not generate an interrupt.

1 = OVRR bit generates an interrupt. Reserved.

MUTE_IND M

Masks the MUTE_IND from generating an

0 = MUTE_IND bit does not generate an interrupt.

1 = MUTE_IND bit generates an interrupt.

Table 43. Interrupt St

TxCSINT

RxCSDIFF RxUBINT RxCSBINT RxERROR

atus Register

SRCError

TxCSTINT

TxUBINT

7 6 5 4 3 2 1 0

ADDRESS = 0011100 (0x1C)

SRCError

This bit is set, if one of the sample rate converter interrupts is asserted, and the host should immediately read the

gh until the interrupt status register is read.

sample rate converter error register. This bit remains hi

TxCSTINT

This bit is set, if a write to the transmitter channel status buffer was made while transmitter channel status bits were

fer to the SPDIF transmit buffer.

his bit remains high until the interrupt status register is read.

it buffer has transmitted its block of channel status. This bit remains

ceiver Channel Status B clock. This bit

remains high until read, but does not generate an interrupt.

eiver user bit buffer has a new block or message. This bit remains high until the interrupt

RxCSBIN

it is set, if

block of c

tus is rea

0, or if the

when

BCONF3 = 1.

is bit remains

gh until the interrupt status register is read.

is set, if one of the AES3/SPDIF receiver interrupts is asserted, and the host should immediately read the

ins high until the interrupt status register is read.

being copied from the transmitter CS buf

TxUBINT

This bit is set, if the SPDIF transmit buffer is empty. T

TxCSINT

This bit is set, if the transmitter channel status b
high until the interrupt status register is read.
This bit is set, if the receiver Channel Status A block is different from the re

RxCSDIFF

RxUBINT

This bit is set, if the rec
status register is read.

This b

a new

hannel sta

d when RxBC NF3 =

channel status ha changed

RxERROR

This bit
receiver error register. This bit rema

ADAV801

Rev. 0 | Page 41 of 56

xCSTINT

TxUBINT
Mask

TxCSBINT
Mask RES

RxUBINT
Mask

RxCSBINT
Mask

RxError
Mask

Table 44. Interrupt Status Mask Register

SRCError

Mask

7 6 5 4 3 2 1 0

ADDRESS = 0011101 (0x1D)

SRCError Mask

Masks the SRCError bit from generating an interrupt.

0 = SRCError bit does not generate an interrupt.

an interrupt.

INT bit from generating an interrupt.

oes not generate an interrupt.

n interrupt.

ask

1 = TxUBINT bit generates an interrupt.

rrupt.

nterrupt.

T bit from generating an interrupt.

BINT bit does not generate an interrupt.

xCSBINT Mask

Masks the RxCSBINT bit from generating an interrupt.

nerate an interrupt.

nterrupt.

rating an interrupt.

s not generate an interrupt.

rror bit generates an interrupt.

1 = SRCError bit generates

TxCSTINT Mas

Masks the TxCST

0 = TxCSTINT bit d

1 = TxCSTINT bit generates a

TxUBINT M

Masks the TxUBINT bit from generating an interrupt.
0 = TxUBINT bit does not generate an interrupt.

TxCSBINT Mask

Masks the TxCSBINT bit from generating an inte

0 = TxCSBINT bit does not generate an inte

1 = TxCSBINT bit generates an i

RxUBINT Mask

Masks the RxUBIN

0 = RxU

1 = RxUBINT bit generates an interrupt.

0 = RxCSBINT bit does not ge

1 = RxCSBINT bit generates an i
Masks the RxError bit from gene

RxError Mask

0 = RxError bit doe

1 = RxE

able 45. Mute and De-Emphasis Register

RES RES SRC_DEEM10

RES

RES RES TxMUTE

7 6 5

4 3 2,

ADDRESS = 0011110 (0x1E)

TxMUTE

Mutes the AES3/SPDIF transmitter.

0 = Transmitter is not muted.
1 = Transmitter is muted.

SRC_DEEM10

Selects the de-emphasis filter for the input data to the sample rate converter.

mphasis.

kHz de-emphasis.

00 = No de-emphasis.

01 = 32 kHz de-emphasis.

10 = 44.1 kHz de-e

11 = 48

Table 46. NonAudio Preambl

RES

DTS-CD
Preamble

NonAudio
Frame

NonAudio
Subframe_A

NonAudio
Subframe_B

e Type Register (Read Only)

RES RES RES

7 6 5 4 3 2 1

ADDRESS = 0011111 (0x1F)

DTS-CD Preamble

This bit is set, if the DTS-CD preamble is detected.

NonAudio Frame

dio

me_A

subframe nonaudio data

onAudio

Subframe_B

This bit is set, if the data received through Channel B of the AES3/SPDIF receiver is subframe nonaudio data
according to SMPTE337M.

This bit is set, if the data received through the AES3/SPDIF receiver is nonaudio data according to the IEC61937
standard or nonaudio data according to SMPTE337M.

NonAu
Subfra

This bit is set, if the data received through Channel A of the AES3/SPDIF receiver is
according to SMPTE337M.

ADAV801

Rev. 0 | Page 42 of 56

tatus Buffer

RCS

SB0

Table 47. Receiver Channel S

B7RC

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS

000 to 01

(0x20 to

= 0100

10111

0x37)

RCSB70

The 24-byte receiver channel status buffer. The PRO b

d at ad

tion 0

This bu

only if the channel status is not autob

betwee

ceiver an

mitter.

it is store

dress loca

x20, Bit 0.

ffer is rea

uffered

n the re

d trans

Table 48. T

ter Ch

tus Bu

TCS

ransmit

annel Sta

ffer

B7TCS

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS

to 10

38 to

= 0111000

01111 (0x

0x4F)

TCSB70

The 24-byte transmi

el stat

The PR

tored a

location 0x38, Bit 0. This buffer is

disa

autob

etwee

iver and transmitter is

tter chann

us buffer.

O bit is s

t address

bled when

uffering b

n the rece

enabled.

Table 49. Receiver User Bit Buffer Indire

ess Regi

RxUBADDR07RxUBADDR00

ct Addr

ster

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010000 (0x50)

RxUBADDR0700

ng to th

ss loca

he rece

r bit bu

Indirect address pointi

e addre

tion in t

iver use

ffer.

Table 50. Receiver Us

07RxUBDATA00

er Bit Buffer Data Register

RxUBDATA

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010001 (0x51)

RxUBDATA0700

egister reads eight bits of user data from the receiver user bit buffer pointed to by RxUBADDR07

ering of the user bits is enabled; otherwise, it is a read-only buffer.

A read from this r
00. This buffer can be written to when autobuff

Table 51. Transmitte

Indirect Address Register

BADDR00

r User Bit Buffer

TxUBADDR07TxU

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010010 (0x52)

TxUBADDR0700

ress pointing to the address location in the transmitter user bit buffer.

Indirect add

Table 52. Transmitter User Bit Buffer

DATA00

Data Register

07TxUB

TxUBDATA

7, 6, 5, 4, 3, 2, 1, 0

ADDRESS = 1010011 (0x53)

TxUBDATA0700

A write to this register writes eight bits of user data to the transmit user bit buffer pointed to by TxUBADDR0700.
When user bit autobuffering is enabled, this buffer is disabled.

Table 53. Q Subcode CRCError Status Register (Read-Only)

RES RES RES RES RES RES QCRCERROR

QSUB

7 6 5 4

3 2 1

ADDRESS = 1010100 (0x54)

QCRCERROR

This bit is set, if the CRC check of the Q subcode fails. This bit remains high, but does not generate an interrupt. This
bit is cleared once the register is read.

QSUB

This bit is set, if a Q subcode has been read into the Q subcode buffer (see Table 54).

ADAV801

Rev. 0 | Page 43 of 56

Bit 7

it 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit

Table 54. Q Subcode Buffer

Addres

t 0

0x55

Address Address Address

ss Control Control Control Control

Addre

0x56

Track

Tra

number

Track

Track
number

number

0x57

Index Index Index Index Index Index Index Index

0x58 Minute

te Minute Minute Minute Minute Minute Minute

Minu

0x59

Second Second Second Second Second Second Second Second

0x5A

Frame Frame Frame Frame Frame Frame Frame Frame

0x5B

Zero Zero Zero Zero Zero Zero Zero Zero

0x5C

Absolute
minute

minute

Absolute
minute

Absolute

minute

0x5D

Absolute
second

Absolu
second

0x5E

Absolute
frame

Table 55. Datapath Control Register 1

SRC1 SRC0 REC2 REC1 REC0 AUXO2

AUXO1

AUXO0

7 6 5 4 3 2 1 0

ADDRESS = 1100010 (0x62)

SRC10

Datapath source select for sample rate converter (SRC).

00 = ADC.

01 = DIR.

10 = Playback.

11 = Auxiliary in.

REC20

Datapath source select for record output port.

auxiliary output port.

000 = ADC.

001 = DIR.

010 = Playback.

011 = Auxiliary in

100 = SRC.

AUXO20

Datapath source select for

000 = ADC.

001 = DIR.

010 = Playback.

011 = Auxiliary in.

100 = SRC.

ADAV801

Rev. 0 | Page 44 of 56

r 2

DAC0 DIT2 DIT1 DIT0

Table 56. Datapath Control Registe

RES RES DAC2 DAC1

7 6 5 4 3 2 1 0

ADDRESS = 1100011 (0x63)

DAC20

Datapath source select for DAC.

00 = ADC.

01 = DIR.

10 = Playback.

11 = Auxiliary in.

IT.

100 = SRC.

DIT20

Datapath source select for D

000 = ADC.

001 = DIR.

010 = Playback.

011 = Auxiliary in.

100 = SRC.

Table 57. DAC Contr

DR_DIG

CHSEL1

CHSEL0 POL1

POL0

MUTER MUTEL

ol Register 1

DR_ALL

7 6 5 4 3 2 1 0

ADDRESS = 1100100 (0x64)

DR_ALL

Hard reset a

wer-down

nd po

0 = Normal, output pins go to V

REF

level.

d reset and low power, output pins go to AGND.

except registers.

l, left-right.

ght.

right-left.

polarity.

00 = Both positive.

tive.

= Right ne

ht channel.

1 = Har

DR_DIG

DAC digital reset.

0 = Normal.

1 = Reset all

CHSEL10

DAC channel select.

00 = Norma

01 = Both ri

10 = Both left.

11 = Swapped,

POL10

DAC channel

01 = Left nega

gative.

11 = Both negative.

MUTER

Mute rig

0 = Normal.

1 = Mute.

MUTEL

Mute left channel.

0 = Normal.

1 = Mute.

ADAV801

Rev. 0 | Page 45 of 56

Table 58. DAC Control Register 2

RES RES DMCLK1

DMCLK0

DFS1

DFS0

DEEM1

DEEM0

7 6 5 4

3 2

1 0

ADDRESS = 1100101 (0x65)

DMCLK10

DAC MCLK divider.

00 = MCLK.

01 = MCLK/1.5.

10 = MCLK/2.

11 = MCLK/3.

elect.

CLK

= 4 × (MCLK

128 × f

(MCLK = 64 × f

EEM10

elect.

10 = 32 kHz.
11 = 48 kHz.

DFS10

DAC interpolator s

00 = 8 × (M

= 256 × f

10 = 2 ×

11 = Reserved.

DAC de-emphasis s

00 = None.

01 = 44.1 kHz.

Table 59. DAC Contr

Register 3

RES RES RES RES ZFVOL

ZFDATA

ZFPOL

RES

4 3 2 1 0

6 5

ADDRESS = 1100110 (0x66)

ZFVOL

DAC zero flag on mute and zero volume.

0
1 = Disabled.

disable.

0 = Enabled.
1 = Disabled.

lag polarity.

0
1

= Enabled.

ZFDATA

DAC zero flag on zero data

ZFPOL

DAC zero f

= Active high.

= Active low.

Table 60. DAC Contr

RES INTRPT

ZEROSEL1

ZEROSEL0

RES RES RES RES

ol Register 4

7 6 5 4 3 2 1 0

ADDRESS = 1100111 (0x67)

INTRPT

This bit selects th

unctionality

the ZEROL/

pin.

e f

INT

0 = Pin functions as a ZEROL flag pin.
1

in.

lity of the ZEROR pin when the ZEROL/INT pin is used as an interrupt.

00 = Pin functions as a ZEROR flag pin.
01 = Pin functions as a ZEROL flag pin.
1

hen either the left or right channel is zero.

right channels are zero.

= Pin functions as an interrupt p

ZEROSEL10

hese bits control the functiona

0 = Pin is asserted w

1 = Pin is asserted when both the left and

ADAV801

Rev. 0 | Page 46 of 56

LL7

Table 61. DAC Left Volume Register

DVO

DVOLL6 DVOLL

DVOLL

7 6 5 4 3 2 1 0

ADDRESS = 1101000 (0x68)

DVOLL70

DAC left channel volume control

1111111 = 0 dBFS.

1111110 = -0.375 dBFS.

0000 = -95.625 dBFS.

000

Table 62. DAC Right Volume Register

LR7 DVOLR6 DVOLR5 DVOLR4 DVOLR3 DVOLR2 DVOLR1 DVOLR0

DVO

7 6 5 4 3 2 1 0

ADDRESS = 1101001 (0x69)

DVOLR70

DAC right channel volume control.

1111111 = 0 dBFS.

1111110 = -0.375 dBFS.

0000000 = -95.625 dBFS.

Table 63. DAC Left P

DLP5 DLP4 DLP3 DLP2 DLP1 DLP0

eak Volume Register

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1101010 (0x6A)

DLP50

DAC left channel peak volume detection.

000000 = 0 dBFS.

000001 = -1 dBFS.

111111 = -63 dBFS

Table 64. DAC Right Peak Volume Register

DRP5 DRP4 DRP3 DRP2 DRP1 DRP0

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1101011 (0x6B)

DRP50

DAC right channel peak volume detection.

000000 = 0 dBFS.

000001 = -1 dBFS.
111111 = -63 dBFS.

Table 65. ADC Left Chan

ter

AGL5 AGL4 AGL3 AGL2 AGL1 AGL0

nel PGA Gain Regis

RES RES

7 6 5 4

3 2 1 0

ADDRESS = 1101100 (0x6C)

AGL50

PGA left channel gain control.

000000 = 0 dB.

000001 = 0.5 dB.

...

101111 = 23.5 dB.

110000 = 24 dB.

...

111111 = 24 dB.

ADAV801

Rev. 0 | Page 48 of 56

Table 68. ADC Control Register 2

RES RES ES UF_PD

RES RES MCD1

MCD0

7 6 5 4 3 2 1 0

ADDRESS = 1101111 (0x6F)

BUF_PD

Reference buffer power-down control.

0 = Normal.

MCD10

ck divider.

y 1.

1 = Power-dow
ADC master clo

00 = Divide by 1.

01 = Divide by 2.

10 = Divide by

11 = Divide b

Table 69. ADC Left V

AVOLL6 AVOLL5 AVOLL4 AVOLL3 AVOLL2 AVOLL1 AVOLL0

olume Regist

AVOLL7

7 6 5 4 3 2 1 0

ADDRESS = 1110000 (0x70)

AVOLL70

olume control.

ADC left channel v

1111111 = 1.0 (0 dBFS).

996 (-0.00348 dBFS).

dBFS).

0039 (-48.18 dBFS).

1111110 = 0.

1000000 = 0.5 (-6

0111111 = 0.496 (-6.09 dBFS).

0000000 = 0.

Table 70. ADC Right

AVOLR6 AVOLR5 AVOLR4 AVOLR3 AVOLR2 AVOLR1 AVOLR0

Volume Register

AVOLR7

7 6 5 4 3 2 1 0

ADDRESS = 1110001 (0x71)

AVOLR70

ADC right chan

me co

nel volu

ntrol.

11111 1 = 1.0

BFS).

0 = 0.996 (-0.00348 dBFS).

96 (-6.09 dBFS).

111111

(0 d

1000000 = 0.5 (-6 dBFS).

0111111 = 0.4

0000000 = 0.0039 (-48.18 dBFS

Table 71. ADC Left P

gister

5 ALP4 ALP3 ALP2 ALP1 ALP0

eak Volume Re

RES RES ALP

7 6 5 4 3 2 1 0

ADDRESS = 1110010 (0x72)

ALP50

ADC left channel peak volume detection.

000000 = 0 dBFS.

BFS.

000001 = -1 d

111111 = -63 dBFS.

Table 72. ADC Right

egister

RES ARP5 ARP4 ARP3 ARP2 ARP1 ARP0

Peak Volume R

RES

7 6 5 4 3 2 1 0

ADDRESS = 1110011 (0x73)

ARP50

ADC right channel peak volume detection.

000000 = 0 dBFS.

000001 = -1 dBFS.
111111 = -63 dBFS.

ADAV801

Rev. 0 | Page 49 of 56

LK1

LK0

DIV

Table 73. PLL Control Register 1

DIRIN_C

MCLKO

PLLDIV

PLL2PD

PLL1PD

XTLPD SYSCLK3

7 6 5

3 2 1 0

ADDRESS = 1110100 (0x74)

DIRIN_CLK1-0

nt to SYSCLK3.

Recovered SPDIF clock se
00 = SYSCLK3 comes from PLL block.

the recovered SPDIF clock from DIRIN.

CLKODIV

generate MCLKO.

y 2 to generate the PLL master clock.

LL2.

own.

n XTAL oscillator.

down.

for SYSCLK3.

01 = Reserved

10 = Reserved.

11 = SYSCLK3 is

Divide input MCLK by 2 to

0 = Disabled.

1 = Enabled

PLLDIV

Divide XIN b

0 = Disabled.

1 = Enabled

PLL2PD

Power-down P

0 = Normal.

1 = Power-down.

PLL1PD

Power-down PLL1.

0 = Normal.

1 = Power-d

XTLPD

Power-dow

0 = Normal.

1 = Power-

SYSCLK3

Clock output

0 = 512 × f

1 = 256 × f

Table 74. PLL Control Register 2

SEL2

DOUB2

FS1 FS0 SEL1

DOUB1

FS2_1

FS2_0

7 6 5 4 3 2 1 0

ADDRESS = 1110101 (0x75)

FS2_10

Sampl rate se

t for PLL2.

lec

00 = 48 kHz.

io select for PLL2.

UB2

lected sample rate on PLL2.

select for PLL1.

rved.

11 = 44.1 kHz.

SEL1

Oversample ratio select for PLL1.

0 = 256 × f

1 = 384 × f

DOUB1

Double-selected sample rate on PLL1.

0 = Disabled.

1 = Enabled.

01 = Reserved.

10 = 32 kH

11 = 44.1 kHz

SEL2

Oversample rat

0 = 256 × f

1 = 384 × f

Double-se

0 = Disabled.

1 = Enable

FS10

Sample rate

00 = 48 kHz.

01 = Rese

10 = 32 kHz

ADAV801

Rev. 0 | Page 50 of 56

egister 1

ACLK1 ACLK0 I

Table 75. Internal Clocking Control R

DCLK2 CLK1 D LK0

LK2

CLK2

ICLK2

7 6

5 4 3 2 1 0

ADDRESS = 1110110 (0x76)

DCLK20

DAC clock source select.

000 = XIN.

LINT2.

LL (512 × f

101 = DIR PLL (256 × f

XIN.

C clock source select.

IN.

r for internal clock ICLK2.

001 = MCLK

010 = PLLINT1.

011 = PL

100 = DIR P

110 = XIN.

111 =

ACLK20

000 = X

001 = MCLKI.

010 = PLLINT

011 = PLLINT2.

100 = DIR PLL (512 × f

101 = DIR PLL (256 × f

110 = XIN.

111 = XIN.

ICLK2_10

Source selecto

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

Table

76. Internal Clo

l Register 2

RES ICLK1_1

ICLK1_0

PLL2INT1

PLL2INT0

PLL1INT

cking Contro

RES RES

7 6 5 4 3 2 1 0

ADDRESS = 1110111 (0x77)

ICLK1_10

Source selector for internal clock ICLK1.

00 = XIN.

01 = MCLKI.

10 = PLLINT1.

11 = PLLINT2.

PLL2INT10

PLL2 internal selector (see Figure 38).

00 = FS2.

01 = FS2/2.

10 = FS3.

11 = FS3/2.

PLL1INT

PLL1 internal selector.

0 = FS1.

1 = FS1/2.

ADAV801

Rev. 0 | Page 52 of 56

GAINCNTR10

RECMODE10 LIMDET

ALCEN

Table 79. ALC Control Register 1

FSSEL10

7, 6

5, 4

3, 2

ADDRESS = 1111011 (0x7B)

FSSEL10

These bits should equal the sample rate of the ADC.

00 = 96 kHz.

01 = 48 kHz.

10 = 32 kHz.

11 = Reserved.

GAINCNTR10

These bits determine the limit of the counter used in limited recovery mode.

00 = 3.

01 = 7.

10 = 15.

11 = 31.

RECMODE10

These bits determine which recovery mode is used by the ALC section.

00 = No recovery.

01 = Normal recovery.

10 = Limited recovery.

11 = Reserved.

LIMDET

These bits limit detect mode.

0 = ALC is used when either channel exceeds the set limit.

1 = ALC is used only when both channels exceed the set limit.

ALCEN

These bits enable ALC.

0 = Disable ALC.

1 = Enable ALC.

Table 80. ALC Control Register 2

RES

RECTH10

ATKTH10

RECTIME10

ATKTIME

6, 5

4, 3

2, 1

ADDRESS = 1111100 (0x7C)

RECTH10

Recovery threshold.

00 = -2 dB.

01 = -3 dB.

10 = -4 dB.

11 = -6 dB.

ATKTH10

Attack threshold.

00 = 0 dB.

01 = -1 dB.

10 = -2 dB.

11 = -4 dB.

RECTIME10

Recovery time selection.

00 = 32 ms.

01 = 64 ms.

10 = 128 ms.

11 = 256 ms.

ATKTIME

Attack timer selection.

0 = 1 ms.

1 = 4 ms.

ADAV801

Rev. 0 | Page 54 of 56

LAYOUT CONSIDERATIONS

Getting the best performance from the ADAV801 requires a
careful layout of the printed circuit board (PCB). Using separate
analog and digital ground planes is recommended, because
these give the currents a low resistance path back to the power
supplies. The ground planes should be connected in only one
place, usually under the ADAV801, to prevent ground loops.

The analog and digital supply pins should be decoupled to their
respective ground pins with a 10 µF to 47 µF tantalum capacitor
and a 0.1 µF ceramic capacitor. These capacitors should be
placed as close as possible to the supply pins.

ADC

The ADC uses a switch capacitor input stage and is, therefore,
particularly sensitive to digital noise. Sources of noise, such as
PLLs or clocks, should not be routed close to the ADC section.
The CAPxN and CAPxP pins form a charge reservoir for the
switched capacitor section of the ADC, so keeping these nodes
electrically quiet is a key factor in ensuring good performance.
The capacitors connected to these pins should be of good
quality, either NPO or COG, and should be placed as close as
possible to CAPxN and CAPxP.

DAC

The DAC requires an analog filter to filter out-of-band noise
from the analog output. A third-order Bessel filter is
recommended, although the filter to use depends on the

f the application.

PLL

The PLL can be used to generate digital clocks, either for use
internally or to clock external circuitry. Because every clock is a
potential source of noise, care should be taken when using the
PLL. The ADAV801's PLL outputs can be enabled or disabled, as
required. If the PLL clocks are not required by external circuitry,
it is recommended that the outputs be disabled. To reduce
cross-coupling between clocks, a digital ground trace can be
routed on either side of the PLL clock signal, if required.

The PLL has its own power supply pins. To get the best
performance from the PLL and from the rest of the ADAV801,
it is recommended that a separate analog supply be used. Where
this is not possible, the user must decide whether to connect the
PLL supply to the analog (AV

) or digital (DV

) supply.

Connecting the PLL supply to AV

gives the best jitter

performance, but can degrade the performance of the ADC and
DAC sections slightly due to the increased digital noise created
on the AV

by the PLL. Connecting the PLL supply to DV

keeps digital noise away from the analog supply, but the jitter
specifications might be reduced depending on the quality of the
digital supply. Using the layout recommendations described in
this section helps to reduce these effects.

RESET AND POWER-DOWN CONSIDERATIONS

When the ADAV801 is held in reset by bringing the RESET

requirements o

pin low, a number of circuit blocks remain powered up. For
example, the crystal oscillator circuit based around the XIN
and XOUT pins is still active, so that a stable clock source is
available when the ADAV801 is taken out of reset. Also, the
VCO associated with the SPDIF receiver is active so that the
receiver locks to the incoming SPDIF stream in the shortest
possible time. Where power consumption is a concern, the
individual blocks of the ADAV801 can be powered down via
the control registers to gain significant power savings. Table 82
shows typical power savings when using the power-down bits
in the control registers.

Table 82. Typical Power Requirements

Operating
Mode

(mA)

ODV

(mA)

DIR_V

(mA)

Power
(mW)

Normal 50

5 280.5

Reset low

2.5

123.75

Power-down

bits

12 0.1

1.3 0.7 46.53

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Document Outline

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