Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
Fractional-N Frequency Synthesizer
ADF4154
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
RF bandwidth 500 MHz to 4 GHz
2.7 V to 3.3 V power supply
Separate V
P
allows extended tuning voltage
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the ADF4110/ADF4111/
ADF4112/ADF4113, ADF4106 and ADF4153
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance
Fast-lock mode with built-in timer
APPLICATIONS
CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
GENERAL DESCRIPTION
The ADF4154 is a fractional-N frequency synthesizer that
implements local oscillators in the up conversion and down
conversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD),
a precision charge pump, and a programmable reference divider.
There is a - based fractional interpolator to allow program-
mable fractional-N division. The INT, FRAC, and MOD regis-
ters define an overall N divider (N = (INT + (FRAC/MOD))).
In addition, the 4-bit reference counter (R counter) allows
selectable REF
IN
frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and a voltage controlled
oscillator (VCO).
A key feature of the ADF4154 is the fast-lock mode with a built-
in timer. The user can program a predetermined count-down
time value so that the PLL will remain in wide bandwidth mode,
instead of having to control this time externally.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V, and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
LOCK
DETECT
FAST-LOCK
SWITCH
N COUNTER
CP
RFCP3 RFCP2 RFCP1
REFERENCE
DATA
LE
24-BIT
DATA
REGISTER
CLOCK
REF
IN
AV
DD
AGND
V
DD
V
DD
DGND
R
DIV
N
DIV
DGND
CPGND
DV
DD
V
P
SDV
DD
R
SET
RF
IN
A
RF
IN
B
OUTPUT
MUX
MUXOUT
+
HIGH Z
PHASE
FREQUENCY
DETECTOR
ADF4154
THIRD ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
REG
FRACTION
REG
INTEGER REG
P = 4/5 OR 8/9
B = 9 BITS; A = 3 BITS
CURRENT
SETTING
2
DOUBLER
4-BIT
R COUNTER
CHARGE
PUMP
04833-0-001
Figure 1.
ADF4154
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Pin Function Descriptions...................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
RF Input Stage............................................................................... 9
RF INT Divider............................................................................. 9
INT, FRAC, MOD, and R Relationship...................................... 9
RF R Counter ................................................................................ 9
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect...................................................... 10
Input Shift Registers ................................................................... 10
Program Modes .......................................................................... 10
Registers ........................................................................................... 11
Register Definition ..................................................................... 15
R-Divider Register, R1 ............................................................... 15
Control Register, R2 ................................................................... 15
Noise and Spur Register, R3 ...................................................... 16
Reserved Bits............................................................................... 16
RF Synthesizer: A Worked Example ........................................ 16
Modulus....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus................................................ 17
Spurious Optimization and Fast-lock...................................... 17
Fast-Lock Timer and Register Sequences ............................... 17
Fast-Lock: A Worked Example ................................................. 18
Fast-Lock: Loop Filter Topology .............................................. 18
Spurious Signals.......................................................................... 18
Filter Design--ADIsimPLL....................................................... 18
Interfacing ................................................................................... 18
PCB Design Guidelines for Chip Scale Package .................... 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 20
ADF4154
Rev. 0 | Page 3 of 20
SPECIFICATIONS
Table 1. AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted; dBm referred to 50 . The operating temperature for the B version is -40C to +80C.
Parameter
B Version
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
See
Figure 18
for input circuit.
RF Input Frequency (RF
IN
)
1
0.5/4.0
GHz min/max
-8 dBm/0 dBm min/max. For lower frequencies, ensure slew rate > 396 V/s.
1.0/4.0
GHz min/max
-10 dBm/0 dBm min/max.
REFERENCE CHARACTERISTICS
See Figure 17 for input circuit.
REF
IN
Input Frequency
1
10/250 MHz
min/max
For f < 10 MHz, use a dc-coupled, CMOS compatible square wave, slew rate >
21 V/s.
REF
IN
Input Sensitivity
0.7/AV
DD
V
p-p
min/max
AC-coupled.
0 to AV
DD
V max
CMOS compatible.
REF
IN
Input Capacitance
10
pF max
REF
IN
Input Current
100
A max
PHASE DETECTOR
Phase Detector Frequency
2
32
MHz
max
CHARGE PUMP
I
CP
Sink/Source
Programmable. See Table 5.
High Value
5
mA typ
With R
SET
= 5.1 k.
Low Value
312.5
A typ
Absolute Accuracy
2.5
% typ
With R
SET
= 5.1 k.
R
SET
Range
1.5/10
k min/max
I
CP
Three-State Leakage Current
1
nA typ
Sink and source current.
Matching
2
% typ
0.5 V < V
CP
< V
P
0.5.
I
CP
vs. V
CP
2
% typ
0.5 V < V
CP
< V
P
0.5.
I
CP
vs. Temperature
2
% typ
V
CP
= V
P
/2.
LOGIC INPUTS
V
INH
, Input High Voltage
1.4
V min
V
INL
, Input Low Voltage
0.6
V max
I
INH
/I
INL
, Input Current
1
A max
C
IN
, Input Capacitance
10
pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage
1.4
V min
Open-drain 1 k pull-up to 1.8 V.
V
OL
, Output Low Voltage
0.4
V max
I
OL
= 500 A.
POWER SUPPLIES
AV
DD
2.7/3.3
V min/V max
DV
DD
, SDV
DD
AV
DD
V
P
AV
DD
/5.5
V min/V max
I
DD
3
24
mA max
20 mA typical.
Low Power Sleep Mode
1
A typ
NOISE CHARACTERISTICS
Phase Noise Figure of Merit
4
-213
dBc/Hz
typ
ADF4154 Phase Noise Floor
5
-143
dBc/Hz typ
@ 10 MHz PFD frequency.
-139
dBc/Hz typ
@ 26 MHz PFD frequency.
Phase Noise Performance
6
@ VCO output.
1750 MHz Output
7
-102
dBc/Hz typ
@ 1 kHz offset, 26 MHz PFD frequency.
1
Use a square wave for frequencies below f
MIN
.
2
Guaranteed by design. Sample tested to ensure compliance.
3
AC coupling ensures AV
DD
/2 bias. See
for typical circuit.
Figure 17
4
This figure can be used to calculate phase noise for any application. Use the formula 213 + 10log(f
PFD
) + 20logN to calculate in-band phase noise performance, as seen
at the VCO output. The value given is the lowest noise mode.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N-divider value).
The value given is the lowest noise mode.
6
The phase noise is measured with the EVAL-ADF4154EB1 evaluation board and the HP8562E spectrum analyzer.
7
f
REFIN
= 26 MHz; f
PFD
= 26 MHz; offset frequency = 1 kHz; RF
OUT
= 1750 MHz; loop B/W = 20 kHz; lowest noise mode.
ADF4154
Rev. 0 | Page 4 of 20
TIMING CHARACTERISTICS
Table 2. AV
DD
= DV
DD
= SDV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted; dBm referred to 50 .
Parameter
1
Limit at T
MIN
to T
MAX
(B Version)
Unit
Test Conditions/Comments
t
1
20
ns min
LE Setup Time
t
2
10
ns min
DATA to CLOCK Setup Time
t
3
10
ns min
DATA to CLOCK Hold Time
t
4
25
ns min
CLOCK High Duration
t
5
25
ns min
CLOCK Low Duration
t
6
10
ns min
CLOCK to LE Setup Time
t
7
20
ns min
LE Pulse Width
1
Guaranteed by design, but not production tested.
CLOCK
DATA
LE
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
04833-0-026
Figure 2. Timing Diagram
ADF4154
Rev. 0 | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3. Absolute Maximum Ratings.
1,
2,
3
T
A
= 25C, unless
otherwise noted.
Parameter Rating
V
DD
to GND
-0.3 V to +4 V
V
DD
to V
DD
-0.3 V to +0.3 V
V
P
to GND
-0.3 V to +5.8 V
V
P
to V
DD
-0.3 V to +5.8 V
Digital I/O Voltage to GND
-0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND
-0.3 V to V
DD
+ 0.3 V
REF
IN
, RF
IN
to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version)
-40C to +85C
Storage Temperature Range
-65C to +150C
Maximum Junction Temperature
150C
TSSOP
JA
Thermal Impedance
150.4C/W
LFCSP
JA
Thermal Impedance
(Paddle Soldered)
122C/W
LFCSP
JA
Thermal Impedance
(Paddle Not Soldered)
216C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
215C
Infrared 220C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
This device is a high performance RF integrated circuit with an ESD rating of
< 2 kV, and it is ESD sensitive. Proper precautions should be taken for
handling and assembly.
2
GND = A
GND
= D
GND
= 0 V.
3
V
DD
= AV
DD
= DV
DD
= SDV
DD
.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADF4154
Rev. 0 | Page 6 of 20
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
ADF4154
TOP VIEW
(Not to Scale)
AGND
4
RF
IN
B
5
RF
IN
A
6
AV
DD
7
REF
IN
8
LE
DATA
CLK
SDV
DD
DGND
13
12
11
10
R
SET
1
CP
2
CPGND
3
V
P
DV
DD
MUXOUT
16
15
14
9
04833-0-002
Figure 3. TSSOP Pin Configuration
04833-0-003
15
MUXOUT
LE
DATA
CLK
SDV
DD
14
13
12
1
2
3
20
11
6
7
8
9
10
DGND
DGND
RE
F
IN
AV
DD
AV
DD
4
5
RF
IN
A
RF
IN
B
AGND
AGND
CPGND
19
18
17
16
ADF4154
TOP VIEW
CP
R
SET
V
P
DV
D
D
DV
D
D
PIN 1
INDICATOR
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP LFCSP Mnemonic Description
1 19
R
SET
Connecting a resistor between this pin and ground sets the maximum charge pump output current.
The relationship between I
CP
and R
SET
is
SET
CP
R
5
25
I
.
max
=
where R
SET
= 5.1 k and I
CPmax
= 5 mA.
2 20
CP Charge Pump Output. When enabled, this provides I
CP
to the external loop filter, which in turn drives
the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5 4 RF
IN
B
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a
small bypass capacitor, typically 100 pF (see Figure 18).
6 5 RF
IN
A
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6,
7
AV
DD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
DD
has a value of 3 V 10%. AV
DD
must have the same voltage
as DV
DD
.
8 8 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and an equivalent input
resistance of 100 k (see Figure 17). This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10 11 SDV
DD
- Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to
this pin. SDV
DD
has a value of 3 V 10%. SDV
DD
must have the same voltage as DV
DD
.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a
high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
14 15 MUXOUT
This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15 16,
17
DV
DD
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should
be placed as close as possible to this pin. DV
DD
has a value of 3 V 10%. DV
DD
must have the same
voltage as AV
DD
.
16 18 V
P
Charge Pump Power Supply. This should be greater than or equal to V
DD
. In systems where V
DD
is 3 V, it
can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
ADF4154
Rev. 0 | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5 to Figure 10, and Figure 12: RF
OUT
= 1.722 GHz, PFD Frequency = 26 MHz, INT = 66, Channel Spacing = 200 kHz,
Modulus = 130, Fraction = 30/130, and I
CP
= 5 mA.
Loop Bandwidth = 20 kHz, Reference = 26 MHz, VCO = Vari-L VCO190-1750T, Evaluation Board = EVAL-ADF4154EB1. Measurements
were taken on the HP8562E spectrum analyzer.
OUTP
UT P
O
WE
R (dB)
0
30
50
80
90
100
60
70
40
20
10
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 30/130
RBW = 10Hz
REFERENCE
LEVEL = 4dBm
102dBc/Hz
2kHz
1kHz
1kHz
2kHz
1.722GHz
04833-0-004
Figure 5. Phase Noise (Lowest Noise Mode)
OUTP
UT P
O
WE
R (dB)
0
30
50
80
90
100
60
70
40
20
10
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
N = 66 30/130
RBW = 10Hz
REFERENCE
LEVEL = 4.2dBm
95dBc/Hz
2kHz
1kHz
1kHz
2kHz
1.722GHz
04833-0-005
Figure 6. Phase Noise (Low Noise Mode and Spur Mode)
OUTP
UT P
O
WE
R (dB)
0
30
50
80
90
100
60
70
40
20
10
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR MODE
N = 66 30/130
RBW = 10Hz
REFERENCE
LEVEL = 4.2dBm
90dBc/Hz
2kHz
1kHz
1kHz
2kHz
1.722GHz
04833-0-006
Figure 7. Phase Noise (Lowest Spur Mode)
OUTP
UT P
O
WE
R (dB)
0
30
50
80
90
60
70
40
20
10
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 30/130
RBW = 10Hz
REFERENCE
LEVEL = 4.2dBm
71dBc@200kHz
400kHz
200kHz
200kHz
400kHz
1.722GHz
100
04833-0-007
Figure 8. Spurs (Lowest Noise Mode)
OUTP
UT P
O
WE
R (dB)
0
30
50
80
90
100
60
70
40
20
10
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
N = 66 30/130
RBW = 10Hz
REFERENCE
LEVEL = 4.2dBm
74dBc@200kHz
400kHz
200kHz
200kHz
400kHz
1.722GHz
04833-0-008
Figure 9. Spurs (Low Noise and Spur Mode)
OUTP
UT P
O
WE
R (dB)
0
30
50
80
90
100
60
70
40
20
10
V
DD
= 3V, V
P
= 5V
I
CP
= 5mA
PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR NOISE
N = 66 30/130
RBW = 10Hz
REFERENCE
LEVEL = 4.2dBm
400kHz
200kHz
200kHz
400kHz
1.722GHz
04833-0-009
Figure 10. Spurs (Lowest Spur Mode)
ADF4154
Rev. 0 | Page 8 of 20
PH
A
SE N
O
ISE (
d
B
c
/H
z)
PHASE DETECTOR FREQUENCY (kHz)
130
140
150
160
170
100
1000
10000
100000
04833-0-010
Figure 11. PFD Noise Floor vs. PFD Frequency (Lowest Noise Mode)
FREQUENCY (GHz)
AMP
L
ITUDE
(dBm)
5
0
5
10
20
15
25
30
35
0
0.5
1.0
1.5
4.0
3.5
3.0
2.5
2.0
4.5
P = 4/5
P = 8/9
04833-0-011
Figure 12. RF Input Sensitivity
V
CP
(V)
6
0
6
I
CP
(mA)
4
2
2
4
5
3
1
1
3
5
0
1
2
3
4
5
04833-0-012
Figure 13. Charge Pump Output Characteristics
R
SET
VALUE (k
)
80
85
110
0
3
30
25
20
15
10
5
PH
A
SE N
O
ISE (
d
B
c
/H
z)
90
95
5
105
100
04833-0-013
Figure 14. Phase Noise vs. R
SET
TEMPERATURE(C)
90
94
104
60
100
40
PH
A
SE N
O
ISE (
d
B
c
/H
z)
20
0
20
40
60
96
98
92
102
100
80
04833-0-014
Figure 15. Phase Noise vs. Temperature
04833-0-028
TIME (
s)
100
0
10
20
30
40
50
60
65
75
85
95
FRE
Q
UE
NCY
(GHz)
1.700
1.696
1.692
1.688
1.684
1.680
1.676
1.672
1.668
1.664
1.660
1.656
1.652
1.648
1.644
1.640
A
B
Figure 16. A) Lock Time in Fast-lock Mode. Fast Counter = 150, Low Spur
Mode: a 1649.7 MHz to 1686.8 MHz Frequency Jump.
Final Loop Bandwidth = 60 kHz
B) Lock Time with the PLL in Normal Mode (Non Fast-lock), Low Spur Mode, a
1649.7 MHz to 1686.8 MHz Frequency Jump. Final Loop Bandwidth = 60 kHz
ADF4154
Rev. 0 | Page 9 of 20
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that the REF
IN
pin is not loaded on
power-down.
BUFFER
TO R COUNTER
REF
IN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
04833-0-027
Figure 17. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AV
DD
2k
2k
RF
IN
B
RF
IN
A
04833-0-015
Figure 18. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies that
are spaced by fractions of the phase frequency detector (PFD).
See the RF Synthesizer: A Worked Example section for more
information. The RF VCO frequency (RF
OUT
) equation is
(
)
(
)
MOD
FRAC
INT
F
RF
PFD
OUT
+
=
(1)
where RF
OUT
is the output frequency of the external voltage
controlled oscillator (VCO).
(
)
R
D
REF
F
IN
PFD
+
=
1
(2)
where:
REF
IN
is the reference input frequency.
D
is the REF
IN
doubler bit.
R
is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT
is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD
is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC
is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD).
RF R COUNTER
The 4-bit RF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N COUNTER
04833-0-016
Figure 19. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
U3
CLR2
Q2
D2
U2
DOWN
UP
HI
HI
CP
IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1
D1
U1
04833-0-017
Figure 20. PFD Simplified Schematic
ADF4154
Rev. 0 | Page 10 of 20
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4154 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (see Table 9).
Figure 21 shows the MUXOUT section in block diagram form.
The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 k nominal.
When lock has been detected, the lock detect is high with
narrow low-going pulses.
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
ANALOG LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DV
DD
LOGIC LOW
FAST-LOCK CONTROL
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
04833-0-018
LOGIC HIGH
Figure 21. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4154 digital section includes a 4-bit RF R counter, a
9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 24-bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of four latches
on the rising edge of LE. The destination latch is determined by
the state of the two control bits (C2 and C1) in the shift register.
These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The
truth table for these bits is shown in Table 5. Table 6 shows a
summary of how the latches are programmed.
PROGRAM MODES
Table 5 through Table 10 show how to set up the program
modes in the ADF4154.
The ADF4154 programmable modulus is double-buffered. This
means that two events have to occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
then be written to so that the modulus value is loaded correctly.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1 Data
Latch
0 0 N-divider
register
0 1 R-divider
register
1 0 Control
register
1
1
Noise and spur register
ADF4154
Rev. 0 | Page 11 of 20
REGISTERS
Table 6. Register Summary
NOISE AND SPUR REG
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB1
DB0
C2 (1) C1 (1)
T1
T2
T3
T4
T5
T6
T7
T8
NOISE AND SPUR
MODE
DB2
T9
NOI
S
E
AND S
P
U
R
MO
DE
RESERVED
N-DIVIDER REG
DB20 DB19 DB18 DB17 DB16 DB15 DB14
DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
N1
N3
N4
N5
N6
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
CONTROL
BITS
12-BIT RF FRACTIONAL VALUE
DB23
DB22
DB21
N7
N8
N9
9-BIT RF INTEGER VALUE
N2
FAS
T
-LOCK
FL1
R-DIVIDER REG
DB18
DB17 DB16 DB15 DB14 DB13
DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
R1
R3
R4
12-BIT MODULUS
4-BIT
R COUNTER
R2
MUXOUT
P2
DB20
DB19
P1
M1
DB23 DB22
DB21
M2
M3
P3
LOAD
CONTROL
R
ESER
VED
R
ESER
VED
PR
ESC
A
L
ER
CONTROL REG
RE
FE
RE
NCE
DOUBLE
R
DB14
DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
U1
U2
U3
U4
U5
CP0
CP1
CP2
U6
0
0
0
0
CP CURRENT
SETTING
PD
POL
A
R
I
T
Y
RESERVED
LDP
POWER
-
DOW
N
CP
T
H
R
EE-
ST
A
T
E
COUNTE
R
R
ESET
DB15
CP3
CP
/
2
04833-
0-
019
Table 7. Noise and Spur Register
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB1
DB0
C2 (1)
C1 (1)
T1
T2
T3
T4
T5
T6
T7
T8
CONTROL
BITS
NOISE AND SPUR
MODE
DB2
T9
NOIS
E
AND S
P
U
R
MO
DE
RESERVED
R
ESER
VED
RESERVED
RESERVED
DB10, DB5, DB4, DB3
0
NOISE AND SPUR SETTING
LOWEST SPUR MODE
LOW NOISE AND SPUR MODE
LOWEST NOISE MODE
DB9, DB8, DB7, DB6, DB2
00000
11100
11111
THESE BITS MUST BE SET TO 0
FOR NORMAL OPERATION.
04833-0-023
ADF4154
Rev. 0 | Page 12 of 20
Table 8. N-Divider Register Map
F12
0
0
0
0
.
.
.
1
1
1
1
F11
0
0
0
0
.
.
.
1
1
1
1
F10
0
0
0
0
.
.
.
1
1
1
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
F3
0
0
0
0
.
.
.
1
1
1
1
F2
0
0
1
1
.
.
.
0
0
1
1
F1
0
1
0
1
.
.
.
0
1
0
1
FRACTIONAL VALUE (FRAC)
0
1
2
3
.
.
.
4092
4093
4094
4095
N9
0
0
0
0
.
.
.
1
1
1
N8
0
0
0
0
.
.
.
1
1
1
N7
0
0
0
0
.
.
.
1
1
1
N6
0
1
1
1
.
.
.
1
1
1
N5
1
0
0
0
.
.
.
1
1
1
N4
1
0
0
0
.
.
...
1
1
1
N3
1
0
0
0
.
.
.
1
1
1
N2
1
0
0
1
.
.
.
0
1
1
N1
1
0
1
0
.
.
.
1
0
1
INTEGER VALUE (INT)
31
32
33
34
.
.
.
509
510
511
FL1
0
1
FAST-LOCK
NORMAL OPERATION
FAST-LOCK ENABLED
DB20 DB19 DB18 DB17
DB16 DB15 DB14
DB13
DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
N1
N3
N4
N5
N6
CONTROL
BITS
12-BIT FRACTIONAL VALUE (FRAC)
DB23 DB22 DB21
N7
N8
N9
9-BIT INTEGER VALUE (INT)
N2
FAS
T-LOCK
FL1
04833-
0-
020
ADF4154
Rev. 0 | Page 13 of 20
Table 9. R-Divider Register Map
M12
0
0
0
.
.
.
1
1
1
1
INTERPOLATOR
MODULUS VALUE (MOD)
2
3
4
.
.
.
4092
4093
4094
4095
M11
0
0
0
.
.
.
1
1
1
1
M10
0
0
0
.
.
.
1
1
1
1
M3
0
0
1
.
.
.
1
1
1
1
M2
1
1
0
.
.
.
0
0
1
1
M1
0
1
0
.
.
.
0
1
0
1
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
RF R-COUNTER
DIVIDE RATIO
1
2
3
4
.
.
.
12
13
14
15
R4
0
0
0
0
.
.
.
1
1
1
1
R3
0
0
0
1
.
.
.
1
1
1
1
R2
0
1
1
0
.
.
.
0
0
1
1
R1
1
0
1
0
.
.
.
0
1
0
1
P1
0
1
PRESCALER
4/5
8/9
DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
R1
R3
R4
CONTROL
BITS
12-BIT INTERPOLATOR MODULUS VALUE (MOD)
4-BIT R COUNTER
R2
MUXOUT
P2
DB20 DB19
P1
M1
DB23 DB22 DB21
M2
M3
P3
LOAD
CONTROL
R
ESER
VED
PR
ESC
A
L
ER
P3
0
1
LOAD CONTROL
NORMAL OPERATION
LOAD FAST-LOCK TIMER
M3
0
0
0
0
1
1
1
1
M2
0
0
1
1
0
0
1
1
M1
0
1
0
1
0
1
0
1
MUXOUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
ANALOG LOCK DETECT
N-DIVIDER OUTPUT
LOGIC HIGH
LOGIC LOW
R-DIVIDER OUTPUT
FAST-LOCK SWITCH
04833-
0-
021
ADF4154
Rev. 0 | Page 14 of 20
Table 10. Control Register Map
U3
0
1
POWER-DOWN
NORMAL OPERATION
POWER-DOWN
U4
0
1
LDP
3
5
I
CP
(mA)
3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CP0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.700k
1.090
2.180
3.260
4.350
5.440
6.530
7.620
8.700
0.540
1.100
1.640
2.180
2.730
3.270
3.810
4.350
5.100k
0.630
1.250
1.880
2.500
3.130
3.750
4.380
5.000
0.310
0.630
0.940
1.250
1.570
1.880
2.190
2.500
10.00k
0.290
0.590
0.880
1.150
1.470
1.760
2.060
2.350
0.150
0.300
0.440
0.588
0.740
0.880
1.030
1.180
U5
0
1
PD POLARITY
NEGATIVE
POSITIVE
U2
0
1
CP THREE-STATE
DISABLED
THREE-STATE
U1
0
1
COUNTER RESET
DISABLED
ENABLED
REFERENCE
DOUBLER
DISABLED
ENABLED
U6
0
1
RE
FE
RE
NCE
DOUBLE
DB14
DB13
DB12 DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
U1
U2
U3
U4
U5
CP0
CP1
CP2
U6
0
0
0
0
CONTROL
BITS
CP CURRENT
SETTING
PD
POLA
R
I
TY
RESERVED
LDP
POW
E
R
-
DOWN
CP
TH
R
EE-
STA
T
E
COUNTE
R
R
ESET
DB15
CP3
CP
/2
04833-0-022
ADF4154
Rev. 0 | Page 15 of 20
REGISTER DEFINITION
N-Divider Register, R0
The on-chip N-divider register is programmed by setting
R0[1, 0] to [0, 0]. Table 8 shows the input data format for
programming this register.
9-Bit INT Value
These nine bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor (see
Equation 1).
12-Bit FRAC Value
These 12 bits control what is loaded as the FRAC value into the
fractional interpolator. This value helps determine the overall
feedback division factor (see Equation 1). The FRAC value must
be less than the value loaded into the MOD register.
Fast-Lock
Setting the part to logic high enables fast-lock mode. To use
fast-lock, the required time value for wide bandwidth mode
needs to be loaded into the R-divider register.
The charge pump current increases from 16 the minimum
current and reverts back to 1 the minimum current once the
time value loaded has expired.
See the Fast-Lock Timer and Register Sequences section for
more information.
R-DIVIDER REGISTER, R1
The on-chip R-divider register is programmed by setting
R1[1, 0] to [0, 1]. Table 9 shows the input data format for
programming this register.
Load Control
When set to logic high, the value being programmed in the
modulus is not loaded into the modulus. Instead, it sets the fast-
lock timer. The value of the fast-lock timer/F
PFD
is the amount
of time the PLL stays in wide bandwidth mode.
MUXOUT
The on-chip multiplexer is controlled by R1[22...20] on the
ADF4154. Table 9 shows the truth table.
Digital Lock Detect
The digital lock detect output goes high if there are 40
successive PFD cycles with an input error of less than 15 ns. It
stays high until a new channel is programmed or until the error
at the PFD input exceeds 30 ns for one or more cycles. If the
loop bandwidth is narrow compared to the PFD frequency, the
error at the PFD inputs may drop below 15 ns for 40 cycles
around a cycle slip. Therefore, the digital lock detect may go
falsely high for a short period until the error again exceeds
30 ns. In this case, the digital lock detect is reliable only as a
loss-of-lock detector.
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF
IN
to the PFD input. Operating at CML levels, it
takes the clock from the RF input stage and divides it down for
the counters. It is based on a synchronous 4/5 core. When set to
4/5, the maximum RF frequency allowed is 2 GHz. Therefore,
when operating the ADF4154 above 2 GHz, this must be set to
8/9. The prescaler limits the INT value.
With P = 4/5, N
MIN
= 31.
With P = 8/9, N
MIN
= 91.
The prescaler can also influence the phase noise performance. If
INT < 91, a prescaler of 4/5 should be used. For applications
where INT > 91, P = 8/9 should be used for optimum noise
performance (see Table 9).
4-Bit RF R Counter
The 4-bit RF R counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the phase frequency detector (PFD). Division ratios from 1 to
15 are allowed.
12-Bit Interpolator Modulus/Fast-Lock Timer
Bits DB13DB2 have two functions depending on the value of
the load control bit: modulus or fast lock timer value.
When the load control bit = 0 (DB23), the required modulus
may be programmed into the R-divider register (DB13DB2).
When the load control bit = 1 (DB23), the required fast-lock
timer value may be programmed into the R-divider register
(DB13DB2).
This programmable register sets the fractional modulus, which
is the ratio of the PFD frequency to the channel step resolution
on the RF output. Refer to the RF Synthesizer: A Worked
Example section for more information.
The ADF4154 programmable modulus is double-buffered. This
means that two events must occur before the part uses a new
modulus value. First, the new modulus value is latched into the
device by writing to the R-divider register. Second, a new write
must be performed on the N-divider register. Therefore, when-
ever the modulus value is updated, the N-divider register must
be written to so that the modulus value is loaded correctly.
CONTROL REGISTER, R2
The on-chip control register is programmed by setting R2[1, 0]
to [0, 1]. Table 10 shows the input data format for programming
this register.
RF Counter Reset
DB3 is the RF counter reset bit for the ADF4154. When this is 1,
the RF synthesizer counters are held in reset. For normal
operation, this bit should be 0.
ADF4154
Rev. 0 | Page 16 of 20
RF Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to 1. It should be set to 0 for normal operation.
RF Power-Down
DB4 on the ADF4154 provides the programmable power-down
mode. Setting Bit DB4 to 1 powers down the device. Setting
Bit DB4 to 0 returns the synthesizer to normal operation. While
in software power-down mode, the part retains all information
in its registers. Only when supplies are removed are the register
contents lost.
When a power-down is activated, the following events occur:
1. All active dc current paths are removed.
2. The synthesizer counters are forced to their load
state conditions.
3. The charge pump is forced into three-state mode.
4. The digital lock detect circuitry is reset.
5. The
RF
IN
input is de-biased.
6. The input register remains active and capable of loading
and latching data.
Lock Detect Precision (LDP)
When the LDP bit is programmed to 0, 24 consecutive reference
cycles of 15 ns must occur before the digital lock detect is set.
When this bit is programmed to 1, 40 consecutive reference
cycles of 15 ns must occur before digital lock detect is set.
Phase Detector Polarity
DB6 in the ADF4154 sets the phase detector polarity. When the
VCO characteristics are positive, this should be set to 1. When
they are negative, it should be set to 0.
Charge Pump Current Setting
DB7, DB8, DB9, and DB10 set the charge pump current, which
should be set according to the loop filter design (see Table 10).
REF
IN
Doubler
Setting the REF
IN
bit to 0 feeds the REF
IN
signal directly to the
4-bit RF R counter, which disables the doubler. Setting the REF
IN
bit to 1 multiplies the REF
IN
frequency by a factor of 2 before
feeding into the 4-bit R counter. When the doubler is disabled,
the REF
IN
falling edge is the active edge at the PFD input to the
fractional synthesizer. When the doubler is enabled, both the
rising and falling edges of REF
IN
become active edges at the
PFD input.
When the doubler is enabled and the lowest spur mode is
chosen, the in-band phase noise performance is sensitive to the
REF
IN
duty cycle. The phase noise degradation can be as much
as 5 dB for the REF
IN
duty cycles outside a 45% to 55% range.
The phase noise is insensitive to the REF
IN
duty cycle in the
lowest noise mode and in the lowest noise and spur mode. The
phase noise is insensitive to the REF
IN
duty cycle when the
doubler is disabled.
NOISE AND SPUR REGISTER, R3
The on-chip noise and spur register is programmed by setting
R3[1, 0] to [1, 1]. Table 7 shows the input data format for
programming this register.
Noise and Spur Mode
Noise and spur mode allows the user to optimize a design either
for improved spurious performance or for improved phase
noise performance. When the lowest spur setting is chosen,
dither is enabled. This randomizes the fractional quantization
noise so that it looks more like white noise rather than spurious
noise. This means that the part is optimized for improved
spurious performance. This operation would normally be used
when the PLL closed-loop bandwidth is wide for fast-locking
applications. A wide-loop bandwidth is seen as a loop
bandwidth greater than 1/10 of the RF
OUT
channel step
resolution (f
RES
). A wide-loop filter does not attenuate the spurs
to a level that a narrow-loop bandwidth would. When the low
noise and spur setting is enabled, dither is disabled. This
optimizes the synthesizer to operate with improved noise
performance. However, the spurious performance is degraded
in this mode compared to the lowest spurs setting. To further
improve noise performance, the lowest noise setting option can
be used, which reduces the phase noise. As well as disabling the
dither, it ensures that the charge pump operates in an optimum
region for noise performance. This setting is extremely useful
where a narrow-loop filter bandwidth is available. The
synthesizer ensures extremely low noise and the filter attenuates
the spurs. The typical performance characteristics give the user
an idea of the trade-off in a typical WCDMA setup for the
different noise and spur settings.
RESERVED BITS
These bits should be set to 0 for normal operation.
RF SYNTHESIZER: A WORKED EXAMPLE
This equation governs how the synthesizer should be
programmed.
RF
OUT
= [INT + (FRAC/MOD)] [F
PFD
] (3)
where:
RF
OUT
is the RF frequency output.
INT
is the integer division factor.
FRAC
is the fractionality.
MOD
is the modulus.
F
PFD
= [REF
IN
(1 = D)/R] (4)
where:
REF
IN
is the reference frequency input.
D
is the RF REF
IN
doubler bit.
R
is the RF reference division factor.
ADF4154
Rev. 0 | Page 17 of 20
For example, in a GSM 1800 system, where a 1.8 GHz RF
frequency output (RF
OUT
) is required, a 13 MHz reference
frequency input (REF
IN
) is available and a 200 kHz channel
resolution (f
RES
) is required on the RF output.
65
kHz
200
MHz
13
=
=
=
MOD
f
REF
MOD
RES
IN
From Equation 4,
F
PFD
= [13 MHz (1 + 0)/1] = 13 MHz
(5)
(
)
30
;
138
65
MHz
13
8
.
1
=
=
+
=
FRAC
INT
FRAC
INT
G
(6)
MODULUS
The choice of modulus (MOD) depends on the reference signal
(REF
IN
) available and the channel resolution (f
RES
) required at
the RF output. For example, a GSM system with 13 MHz REF
IN
would set the modulus to 65, resulting in the RF output resolu-
tion (f
RES
) of 200 kHz (13 MHz/65) that is necessary for GSM.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The reference doubler on-chip allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency. Making the PFD frequency higher improves the
noise performance of the system. Doubling the PFD frequency
usually results in an improvement in noise performance of 3 dB.
It is important to note that the PFD cannot be operated above
32 MHz due to a limitation in the speed of the - circuit of
the N divider.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4154 allows the
user to program the modulus over a 12-bit range. This means
that the user can set up the part in many different configura-
tions for the application, when combined with the reference
doubler and the 4-bit R counter.
For example, consider an application that requires a 1.75 GHz
RF and a 200 kHz channel step resolution. The system has a
13 MHz reference signal.
One possible setup is feeding the 13 MHz directly to the PFD
and programming the modulus to divide by 65, which would
result in the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz signal is
then fed into the PFD, which programs the modulus to divide
by 130. This setup also results in 200 kHz resolution and offers
superior phase noise performance over the previous setup.
The programmable modulus is also very useful for multi-
standard applications. If a dual-mode phone requires PDC and
GSM 1800 standards, the programmable modulus is a huge
benefit. The PDC requires a 25 kHz channel step resolution,
whereas the GSM 1800 requires a 200 kHz channel step
resolution. A 13 MHz reference signal could be fed directly to
the PFD. The modulus would be programmed to 520 when in
PDC mode (13 MHz/520 = 25 kHz). The modulus would be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65 =
200 kHz). It is important that the PFD frequency remains con-
stant (13 MHz). By keeping the PFD constant, the user can
design a one-loop filter that can be used in both setups without
running into stability issues. The ratio of the RF frequency to
the PFD frequency affects the loop design. Keeping this
relationship constant instead of changing the modulus factor
results in a stable filter.
SPURIOUS OPTIMIZATION AND FAST-LOCK
The ADF4154 can be optimized for low spurious signals by
using the noise and spur register. However, in order to achieve
fast-lock time, a wider loop bandwidth is needed. Note that a
wider loop bandwidth can lead to notable spurious signals,
which cannot be reduced significantly by the loop filter.
Using the fast-lock feature can achieve the same fast-lock time
as the noise and spur register, but with the advantage of lower
spurious signals, since the final loop bandwidth is reduced by
a quarter.
FAST-LOCK TIMER AND REGISTER SEQUENCES
If the fast-lock mode is used, a timer value needs to be loaded
into the PLL to determine the time of the wide bandwidth.
When the load control bit = 1, the timer value is loaded via the
12-bit modulus value. To use fast-lock, the PLL must be written
to in the following sequence:
1.
Load the R-divider register with DB23 = 1 and the chosen
fast-lock timer value (DB13DB2) instead of the modulus.
Note that the duration of time the PLL remains in wide
bandwidth is equal to the fast-lock timer/F
PFD
.
2.
Load the noise and spur register.
3.
Load the control register.
4.
Load R-divider register with DB23 = 0 and MUXOUT =
110 (DB22DB20). All the other needed parameters,
including the modulus, also need to be loaded.
5.
Load the N-divider register, including fast-lock = 1
(DB23), to activate fast-lock mode.
Once this procedure is completed, future frequency jumps
deploying fast-lock need to repeat only Step 5.
ADF4154
Rev. 0 | Page 18 of 20
If fast-lock is not used, then use the following sequence:
1.
Load the noise and spur register.
2.
Load the control register.
3.
Load the R-divider register with DB23 = 0 and other
necessary parameters.
4.
Load the N-divider register, including fast-lock = 0
(DB23) for normal operation.
To change frequency, only Step 4 need be repeated.
FAST-LOCK: A WORKED EXAMPLE
Consider an example in which PLL has reference frequencies of
13 MHz and F
PFD
= 13 MHz and a required lock time of 50 s.
Therefore, the PLL is set to wide bandwidth for 40 s.
If the time period chosen for the wide bandwidth is 40 s, then
Fast-lock timer value = time in wide bandwidth F
PFD
Fast-lock timer value = 40 s 13 MHz = 520
Therefore, 520 has to be loaded into the R-divider register in
Step 1 of the sequence described in the Fast-Lock Timer and
Register Sequences section.
FAST-LOCK: LOOP FILTER TOPOLOGY
To use fast-lock mode, an extra connection from the PLL to the
loop filter is needed. The MUXOUT must reduce the damping
resistor in the loop filter to while in wide bandwidth mode.
This is required because the charge pump current is increased
by 16 while in wide bandwidth mode and stability must be
ensured. This can be done with the following two topologies:
1.
Divide the damping resistor (R1) into two values (R1 and
R1A) of ratio 1:3 (see Figure 22).
2.
Use an extra resistor (R1A) and connect it directly from the
MUXOUT, as shown in Figure 22. The extra resistor must
be chosen such that the parallel combination of an extra
resistor and the damping resistor (R1) is reduced to of
the original value of R1 alone (see Figure 23).
ADF4154
CP
MUXOUT
C1
C2
R2
R1
R1A
C3
VCO
04833-0-029
Figure 22 Fast-lock Loop Filter Topology--Topology 1
ADF4154
CP
MUXOUT
C1
C2
R2
R1
R1A
C3
VCO
04833-0-030
Figure 23. Fast-lock Loop Filter Topology--Topology 2
SPURIOUS SIGNALS
Predicting Where They Appear
As in integer-N PLLs, spurs appear at PFD frequency offsets
from the carrier. In a fractional-N PLL, spurs also appear at
frequencies equal to the RF
OUT
channel step resolution (f
RES
).
The third-order fractional interpolator engine of the ADF4154
may also introduce subfractional spurs. If the fractional deno-
minator (MOD) is divisible by 2, spurs appear at f
RES.
If the
fractional denominator (MOD) is divisible by 3, spurs appear at
1/3 f
RES.
Harmonics of all spurs mentioned also appear. With the
lowest spur mode enabled, the fractional and subfractional
spurs are attenuated dramatically. The worst-case spurs appear
when the fraction is programmed to 1/MOD. For example, in a
GSM 900 MHz system with a 26 MHz PFD frequency and an
RF
OUT
channel step resolution (f
RES
) of 200 kHz, the MOD = 130.
PFD spurs appear at 26 MHz offset and fractional spurs appear
at 200 kHz offset. Since the MOD is divisible by 2, subfractional
spurs are also present at 100 kHz offset.
FILTER DESIGN--ADISIMPLL
A filter design and analysis program is available to help the user
implement the PLL design. Visit www.analog.com/pll for a free
download of the ADIsimPLL software. The software designs,
simulates, and analyzes the entire PLL frequency and time
domain response. Various passive and active filter architectures
are allowed. Rev. 2 of ADIsimPLL allows analysis of the
ADF4154.
INTERFACING
The ADF4154 has a simple, SPI compatible serial interface for
writing to the device. SCLK, SDATA, and LE control the data
transfer. When LE (latch enable) is high, the 22 bits that have
been clocked into the input register on each rising edge of
SCLK are transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
909 kHz or one update every 1.1 s. This is more than adequate
for systems that have typical lock times in the hundreds of
microseconds.
ADF4154
Rev. 0 | Page 19 of 20
ADuC812 Interface
ADSP-21xx
ADF4154
SCLOCK
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
DT
TFS
I/O FLAGS
04833-0-025
Figure 24 shows the interface between the ADF4154 and the
ADuC812 MicroConverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, bring the I/O
port driving LE low. Each latch of the ADF4154 needs a 24-bit
word, which is accomplished by writing three 8-bit bytes from
the MicroConverter to the device. After the third byte is written,
the LE input should be brought high to complete the transfer.
Figure 25. ADSP-21xx to ADF4154 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
When operating in the mode described, the maximum
SCLOCK rate of the ADuC812 is 4 MHz. This means that the
maximum rate at which the output frequency can be changed is
180 kHz.
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized.
ADuC812
ADF4154
SCLOCK
SCLK
SDATA
LE
MUXOUT
(LOCK DETECT)
MOSI
I/O PORTS
04833-0-024
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to avoid shorting.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz. of
copper to plug the via.
Figure 24. ADuC812 to ADF4154 Interface
ADSP-2181 Interface
Figure 25 shows the interface between the ADF4154 and the
ADSP-21xx digital signal processor. As discussed previously, the
ADF4154 needs a 24-bit serial word for each latch write. The
easiest way to accomplish this using the ADSP-21xx family is to
use the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for eight bits and use three memory locations for each
24-bit word. To program each 24-bit latch, store each of the
three 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
The user should connect the printed circuit board thermal pad
to AGND.
ADF4154
Rev. 0 | Page 20 of 20
OUTLINE DIMENSIONS
16
9
8
1
PIN 1
SEATING
PLANE
8
0
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 26. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
1
20
5
6
11
16
15
BOTTOM
VIEW
10
2.25
2.10 SQ
1.95
0.75
0.55
0.35
0.30
0.23
0.18
0.50
BSC
12 MAX
0.20
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
4.0
BSC SQ
COPLANARITY
0.08
0.60
MAX
0.60
MAX
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 27. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm 4 mm Body, (CP-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Description
Temperature Range
Package Option
ADF4154BRU
Thin Shrink Small Outline Package (TSSOP)
-40C to +85C
RU-16
ADF4154BRU-REEL
Thin Shrink Small Outline Package (TSSOP)
-40C to +85C
RU-16
ADF4154BRU-REEL7
Thin Shrink Small Outline Package (TSSOP)
-40C to +85C
RU-16
ADF4154BCP
Lead Frame Chip Scale Package (LFCSP)
-40C to +85C
CP-20
ADF4154BCP-REEL
Lead Frame Chip Scale Package (LFCSP)
-40C to +85C
CP-20
ADF4154BCP-REEL7
Lead Frame Chip Scale Package (LFCSP)
-40C to +85C
CP-20
EVAL-ADF4154EB1
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Philips I
2
C Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specifications as defined by Philips.
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registered trademarks are the property of their respective owners.
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