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REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADSP-2106x SHARC
DSP Microcomputer Family
ADSP-21060/ADSP-21060L
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced MQFP Package
225 PBGA Package
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel
with Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
4 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
SHARC is a registered trademark of Analog Devices, Inc.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
SUMMARY
High Performance Signal Processor for Communica-
tions, Graphics, and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch, and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units--
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals--A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
DATA
REGISTER
FILE
16 40-BIT
BARREL
SHIFTER
ALU
MULTIPLIER
7
JTAG
TEST &
EMULATION
32
48
ADDR BUS
MUX
DATA BUS
MUX
MULTIPROCESSOR
INTERFACE
HOST PORT
EXTERNAL
PORT
4
6
6
36
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS &
DATA BUFFERS
I/O PROCESSOR
LINK PORTS
(6)
SERIAL PORTS
(2)
DMA
CONTROLLER
IOA
17
IOD
48
ADDR
DATA
BLOCK 1
ADDR
DATA
ADDR
DATA
ADDR
DATA
TWO INDEPENDENT
DUAL-PORTED BLOCKS
BLOCK 0
PROCESSOR PORT
I/O PORT
DUAL-PORTED SRAM
24
32
48
40/32
PROGRAM
SEQUENCER
INSTRUCTION
CACHE
32 48-BIT
TIMER
BUS
CONNECT
(PX)
PM DATA BUS
DM DATA BUS
DM ADDRESS BUS
PM ADDRESS BUS
DAG1
8 4 32
DAG2
8 4 24
CORE PROCESSOR
Figure 1. Block Diagram
2
ADSP-21060/ADSP-21060L
REV. D
DMA Controller
10 DMA Channels for Transfers Between ADSP-2106x
Internal Memory and External Memory, External
Peripherals, Host Processor, Serial Ports, or Link
Ports
Background DMA Transfers at 40 MHz, in Parallel with
Full-Speed Processor Execution
Host Processor Interface to 16- and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-2106x Internal
Memory
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-2106xs Plus Host
Six Link Ports for Point-to-Point Connectivity and Array
Multiprocessing
240 Mbytes/s Transfer Rate Over Parallel Bus
240 Mbytes/s Transfer Rate Over Link Ports
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 3
ADSP-21060/ADSP-21060L FEATURES . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
TARGET BOARD CONNECTOR FOR EZ-ICE
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RECOMMENDED OPERATING CONDITIONS (5 V) . 13
ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 13
POWER DISSIPATION ADSP-21060 (5 V) . . . . . . . . . . . . 14
RECOMMENDED OPERATING CONDITIONS (3.3 V) 15
ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 15
POWER DISSIPATION ADSP-21060L (3.3 V) . . . . . . . . . 16
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Read--Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Write--Bus Master . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous Read/Write--Bus Master . . . . . . . . . . . . . . 22
Synchronous Read/Write--Bus Slave . . . . . . . . . . . . . . . . 24
Multiprocessor Bus Request and Host Bus Request . . . . . 25
Asynchronous Read/Write--Host to ADSP-2106x . . . . . . 27
Three-State Timing--Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Link Ports: 1
CLK Speed Operation . . . . . . . . . . . . . . 32
Link Ports: 2
CLK Speed Operation . . . . . . . . . . . . . . 33
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 38
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 39
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 42
240-LEAD MQFP PIN CONFIGURATIONS . . . . . . . . . . 43
PACKAGE DIMENSIONS (240-Lead MQFP) . . . . . . . . . 44
225-Ball Plastic Ball Grid Array (PBGA)
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45, 46
PACKAGE DIMENSIONS (225-Ball Grid Array PBGA) . . . 47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FIGURES
Figure 1. ADSP-21060/ADSP-21060L Block Diagram . . . . 1
Figure 2. ADSP-2106x System . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6
Figure 4. ADSP-21060/ADSP-21060L Memory Map . . . . . 7
Figure 5. Target Board Connector For ADSP-2106x
EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11
Figure 6. JTAG Scan Path Connections for Multiple
ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. JTAG Clocktree for Multiple ADSP-2106x
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Memory Read--Bus Master . . . . . . . . . . . . . . . . 20
Figure 14. Memory Write--Bus Master . . . . . . . . . . . . . . . 21
Figure 15. Synchronous Read/Write--Bus Master . . . . . . . 23
Figure 16. Synchronous Read/Write--Bus Slave . . . . . . . . . 24
Figure 17. Multiprocessor Bus Request and Host Bus
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 27
Figure 18b. Asynchronous Read/Write--Host to
ADSP-2106x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19a. Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19b. Three-State Timing (Host Transition Cycle) . . 29
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 31
Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 37
Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 38
Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 40
Figure 26. Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 40
Figure 28. ADSP-2106x Typical Drive Currents
(V
DD
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 29. Typical Output Rise Time (10%90% V
DD
)
vs. Load Capacitance (V
DD
= 5 V) . . . . . . . . . . . . . . . . . . . 41
Figure 30. Typical Output Rise Time (0.8 V2.0 V)
vs. Load Capacitance (V
DD
= 5 V) . . . . . . . . . . . . . . . . . . . 41
Figure 31. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (V
DD
= 5 V) . . . . . . . . . 41
Figure 32. ADSP-2106x Typical Drive Currents
(V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 33. Typical Output Rise Time (10%90% V
DD
)
vs. Load Capacitance (V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . 41
Figure 34. Typical Output Rise Time (0.8 V2.0 V) vs. Load
Capacitance (V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (V
DD
= 3.3 V) . . . . . . . . 42
EZ-ICE is a registered trademark of Analog Devices, Inc.
ADSP-21060/ADSP-21060L
3
REV. D
GENERAL DESCRIPTION
The ADSP-21060 SHARC--Super Harvard Architecture Com-
puter--is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-2106x
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-2106x builds on the ADSP-
21000 DSP core to form a complete system-on-a-chip, adding a
dual-ported on-chip SRAM and integrated I/O peripherals sup-
ported by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-2106x has a 25 ns instruction cycle time and operates
at 40 MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-2106x.
The ADSP-2106x SHARC represents a new standard of inte-
gration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
including a 4 Mbit SRAM memory host processor interface,
DMA controller, serial ports, and link port and parallel bus
connectivity for glueless DSP multiprocessing.
Figure 1 shows a block diagram of the ADSP-2106x, illustrating
the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Table I. ADSP-21060/ADSP-21060L Benchmarks (@ 40 MHz)
1024-Pt. Complex FFT
0.46 ms
18,221 cycles
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
25 ns
1 cycle
IIR Filter (per Biquad)
100 ns
4 cycles
Divide (y/x)
150 ns
6 cycles
Inverse Square Root (1/
x)
225 ns
9 cycles
DMA Transfer Rate
240 Mbytes/s
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-2106x includes the following architectural features
of the ADSP-21000 family core. The ADSP-21060 is code- and
function-compatible with the ADSP-21061 and ADSP-21062.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier opera-
tions. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
3
4
RESET
JTAG
7
ADSP-2106x
BMS
ADDR
31-0
DATA
47-0
CONTROL
ADDRESS
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
ADDR
ACK
CS
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
WE
DATA
DMA DEVICE
(OPTIONAL)
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
1x CLOCK
LINK
DEVICES
(6 MAXIMUM)
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
CS
HBR
HBG
REDY
RD
WR
PAGE
ADRCLK
ACK
MS
3-0
SBTS
SW
BR
1-6
CPA
DMAR1-2
DMAG1-2
SERIAL
DEVICE
(OPTIONAL)
CLKIN
EBOOT
LBOOT
IRQ
2-0
FLAG
3-0
TIMEXP
LxCLK
LxACK
LxDAT
3-0
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RFS1
DT1
DR1
RPBA
ID
2-0
Figure 2. ADSP-2106x System
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-2106x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
S
4
ADSP-21060/ADSP-21060L
REV. D
Instruction Cache
The ADSP-2106x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective--only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-2106x's two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-2106x contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 second-
ary). The DAGs automatically handle address pointer wrap-
around, reducing overhead, increasing performance, and
simplifying implementation. Circular buffers can start and end
at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
2106x can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21060/ADSP-21060L FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21060
adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21060 contains four megabits of on-chip SRAM,
organized as two blocks of 2 Mbits each, which can be config-
ured for different combinations of code and data storage.
Each memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
On the ADSP-21060, the memory can be configured as a maxi-
mum of 128K words of 32-bit data, 256K words of 16-bit data,
80K words of 48-bit instructions (or 40-bit data), or combina-
tions of different word sizes up to four megabits. All of the
memory can be accessed as 16-bit, 32-bit, or 48-bit words.
A 16-bit floating-point storage format is supported that effec-
tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit floating-
point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
2106x's external port.
Off-Chip Memory and Peripherals Interface
The ADSP-2106x's external port provides the processor's inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-2106x's unified
address space. The separate on-chip buses--for PM addresses,
PM data, DM addresses, DM data, I/O addresses, and I/O
data--are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-2106x
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to DRAM
and peripherals with variable access, hold, and disable time
requirements.
Host Processor Interface
The ADSP-2106x's host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-2106x's exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-2106x's external bus
with the host bus request (
HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-2106x, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA Controller
The ADSP-2106x's on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
DMA transfers can occur between the ADSP-2106x's internal
memory and either external memory, external peripherals or a
host processor. DMA transfers can also occur between the
ADSP-2106x's internal memory and its serial ports or link
ports. DMA transfers between external memory and external
peripheral devices are another option. External bus packing to
16-, 32-, or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-2106x--two
via the link ports, four via the serial ports, and four via the
processor's external port (for either host processor, other
ADSP-2106xs, memory or I/O transfers). Four additional link
port DMA channels are shared with serial port 1 and the exter-
nal port. Programs can be downloaded to the ADSP-2106x
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(
DMAR1-2, DMAG1-2). Other DMA features include inter-
rupt generation upon completion of DMA transfers and DMA
chaining for automatic linked DMA transfers.
ADSP-21060/ADSP-21060L
5
REV. D
Serial Ports
The ADSP-2106x features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional
-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
Multiprocessing
The ADSP-2106x offers powerful features tailored to multi-
processing DSP systems. The unified address space (see
Figure 4) allows direct interprocessor accesses of each ADSP-
2106x's internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems
containing up to six ADSP-2106xs and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus lock
allows indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is 240 Mbytes/s
over the link ports or external port. Broadcast writes allow simulta-
neous transmission of data to all ADSP-2106xs and can be used
to implement reflective semaphores.
Link Ports
The ADSP-2106x features six 4-bit link ports that provide addi-
tional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits per cycle. Link port
I/O is especially useful for point-to-point interprocessor commu-
nication in multiprocessing systems.
The link ports can operate independently and simultaneously,
with a maximum data throughput of 240 Mbytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Program Booting
The internal memory of the ADSP-2106x can be booted at
system power-up from either an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the
BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.
32-bit and 16-bit host processors can be used for booting.
6
ADSP-21060/ADSP-21060L
REV. D
ADDR
31-0
DATA
47-0
CPA
BR
2-6
BR
1
BMS
CONTROL
ADSP-2106x #1
5
CPA
BR
1,
BR
3-6
BR
2
CONTROL
ADSP-2106x #2
ADDR
31-0
DATA
47-0
CPA
BR
1-2
,
BR
4-6
BR
3
CONTROL
ADSP-2106x #3
5
3
011
ID
2-0
RESET
RPBA
CLKIN
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
CONTROL
ADDRESS
DATA
1x
CLOCK
RESET
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
CS
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
WE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
WR
MS
3-0
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
ACK
ADDR
31-0
DATA
47-0
5
3
010
ID
2-0
RESET
RPBA
CLKIN
ID
2-0
RESET
RPBA
CLKIN
3
001
CONTROL
ADDRESS
DATA
PAGE
Figure 3. Shared Memory Multiprocessing System
ADSP-21060/ADSP-21060L
7
REV. D
IOP REGISTERS
NORMAL WORD ADDRESSING
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
INTERNAL
MEMORY
SPACE
0x003F FFFF
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=010
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=001
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=011
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=100
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
BROADCAST WRITE
TO ALL
ADSP-2106xs
MULTIPROCESSOR
MEMORY SPACE
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
MS
0
BANK 0
0x0040 0000
0xFFFF FFFF
BANK 1
BANK 2
DRAM
(OPTIONAL)
BANK 3
NONBANKED
MS
1
MS
2
MS
3
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
EXTERNAL
MEMORY
SPACE
Figure 4. ADSP-21060/ADSP-21060L Memory Map
CBUG and SHARCPAC are trademarks of Analog Devices, Inc.
EZ-LAB is a registered trademark of Analog Devices, Inc.
DEVELOPMENT TOOLS
The ADSP-21060 is supported with a complete set of software
and hardware development tools, including an EZ-ICE
In-
Circuit Emulator, EZ-Kit, and development software. The
SHARC
EZ-Kit is a complete low cost package for DSP evalua-
tion and prototyping. The EZ-Kit contains a PC plug-in card
(EZ-LAB
) with an ADSP-21062 (5 V) processor. The EZ-Kit
also includes an optimizing compiler, assembler, instruction
level simulator, run-time libraries, diagnostic utilities and a
complete set of example programs.
The same EZ-ICE hardware can be used for the ADSP-21061/
ADSP-21062, to fully emulate the ADSP-21060, with the excep-
tion of displaying and modifying the two new SPORTS registers
unique to ADSP-21061.
Analog Devices ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
Assembly Library/Librarian, Linker, instruction-level Simulator,
an ANSI C optimizing Compiler, the CBUGTM C Source--
Level Debugger and a C Runtime Library including DSP and
mathematical functions. The Optimizing Compiler includes
Numerical C extensions based on the work of the ANSI Nu-
merical C Extensions Group. Numerical C provides extensions
to the C language for array selections, vector math operations,
complex data types, circular pointers and variably dimensioned
arrays. The ADSP-21000 Family Development Software is
available for both the PC and Sun platforms.
The ADSP-21060 EZ-ICE
Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-21060 processor to monitor
and control the target board processor during emulation. The
EZ-ICE
provides full-speed emulation, allowing inspection
and modification of memory, registers, and processor stacks.
Nonintrusive in-circuit emulation is assured by the use of the
processor's JTAG interface--the emulator does not affect target
system loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware and Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC
processor family. Hard-
ware tools include SHARC
PC plug-in cards multiprocessor
SHARC
VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPACTM module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21060
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer
to the ADSP-2106x SHARC User's Manual, Second Edition.
8
ADSP-21060/ADSP-21060L
REV. D
Pin
Type
Function
ADDR
31-0
I/O/T
External Bus Address. The ADSP-2106x outputs addresses for external memory and peripherals on
these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the internal
memory or IOP registers of other ADSP-2106xs. The ADSP-2106x inputs addresses when a host
processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
DATA
47-0
I/O/T
External Bus Data. The ADSP-2106x inputs and outputs data and instructions on these pins. 32-bit
single-precision floating-point data and 32-bit fixed-point data is transferred over bits 4716 of the
bus. 40-bit extended-precision floating-point data is transferred over bits 478 of the bus. 16-bit short
word data is transferred over bits 3116 of the bus. In PROM boot mode, 8-bit data is transferred over
bits 2316. Pull-up resistors on unused DATA pins are not necessary.
MS
3-0
O/T
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks of
external memory. Memory bank size must be defined in the ADSP-2106x's system control register
(SYSCON). The
MS
3-0
lines are decoded memory address lines that change at the same time as the
other address lines. When no external memory access is occurring the
MS
3-0
lines are inactive; they are
active however when a conditional memory access instruction is executed, whether or not the condition
is true.
MS
0
can be used with the PAGE signal to implement a bank of DRAM memory (Bank 0). In a
multiprocessing system the
MS
3-0
lines are output by the bus master.
RD
I/O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-2106x reads from external memory
devices or from the internal memory of other ADSP-2106xs. External devices (including other ADSP-
2106xs) must assert
RD to read from the ADSP-2106x's internal memory. In a multiprocessing system
RD is output by the bus master and is input by all other ADSP-2106xs.
WR
I/O/T
Memory Write Strobe. This pin is asserted (low) when the ADSP-2106x writes to external memory
devices or to the internal memory of other ADSP-2106xs. External devices must assert
WR to write to
the ADSP-2106x's internal memory. In a multiprocessing system
WR is output by the bus master and
is input by all other ADSP-2106xs.
PAGE
O/T
DRAM Page Boundary. The ADSP-2106x asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-2106x's memory control
register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE signal can
only be activated for Bank 0 accesses. In a multiprocessing system PAGE is output by the bus master.
ADRCLK
O/T
Clock Output Reference. In a multiprocessing system ADRCLK is output by the bus master.
SW
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous
memory devices (including other ADSP-2106xs). The ADSP-2106x asserts
SW (low) to provide an
early indication of an impending write cycle, which can be aborted if
WR is not later asserted (e.g., in a
conditional write instruction). In a multiprocessing system,
SW is output by the bus master and is
input by all other ADSP-2106xs to determine if the multiprocessor memory access is a read or write.
SW is asserted at the same time as the address output. A host processor using synchronous writes must
assert this pin when writing to the ADSP-2106x(s).
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off
completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add wait
states to a synchronous access of its internal memory. In a multiprocessing system, a slave ADSP-
2106x deasserts the bus master's ACK input to add wait state(s) to an access of its internal memory.
The bus master has a keeper latch on its ACK pin that maintains the input at the level it was last
driven to.
PIN FUNCTION DESCRIPTIONS
ADSP-21060 pin definitions are listed below. All pins are iden-
tical on the ADSP-21060 and ADSP-21060L. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for
TRST).
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR
31-0
, DATA
47-0
, FLAG
3-0
,
SW, and inputs that
have internal pull-up or pull-down resistors (
CPA, ACK, DTx,
DRx, TCLKx, RCLKx, LxDAT
3-0
, LxCLK, LxACK, TMS and
TDI)--these pins can be left floating. These pins have a logic-
level hold circuit that prevents the input from floating
internally.
A = Asynchronous
G = Ground
I = Input
O = Output
P = Power Supply
S = Synchronous
(A/D) = Active Drive
(O/D) = Open Drain
T = Three-State (when
SBTS is asserted, or when the
ADSP-2106x is a bus slave)
ADSP-21060/ADSP-21060L
9
REV. D
Pin
Type
Function
SBTS
I/S
Suspend Bus Three-State. External devices can assert
SBTS (low) to place the external bus address,
data, selects and strobes in a high impedance state for the following cycle. If the ADSP-2106x
attempts to access external memory while
SBTS is asserted, the processor will halt and the memory
access will not be completed until
SBTS is deasserted. SBTS should only be used to recover from host
processor/ADSP-2106x deadlock, or used with a DRAM controller.
IRQ
2-0
I/A
Interrupt Request Lines. May be either edge-triggered or level-sensitive.
FLAG
3-0
I/O/A
Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be
tested as a condition. As an output, it can be used to signal external peripherals.
TIMEXP
O
Timer Expired. Asserted for four cycles when the timer is enabled and TCOUNT decrements to
zero.
HBR
I/A
Host Bus Request. Must be asserted by a host processor to request control of the ADSP-2106x's
external bus. When
HBR is asserted in a multiprocessing system, the ADSP-2106x that is bus master
will relinquish the bus and assert
HBG. To relinquish the bus, the ADSP-2106x places the address,
data, select and strobe lines in a high impedance state.
HBR has priority over all ADSP-2106x bus
requests (
BR
6-1
) in a multiprocessing system.
HBG
I/O
Host Bus Grant. Acknowledges an
HBR bus request, indicating that the host processor may take
control of the external bus.
HBG is asserted (held low) by the ADSP-2106x until HBR is released. In a
multiprocessing system,
HBG is output by the ADSP-2106x bus master and is monitored by all others.
CS
I/A
Chip Select. Asserted by host processor to select the ADSP-2106x.
REDY (O/D) O
Host Bus Acknowledge. The ADSP-2106x deasserts REDY (low) to add wait states to an asynchro-
nous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can
be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be
output if the
CS and HBR inputs are asserted.
DMAR1
I/A
DMA Request 1 (DMA Channel 7).
DMAR2
I/A
DMA Request 2 (DMA Channel 8).
DMAG1
O/T
DMA Grant 1 (DMA Channel 7).
DMAG2
O/T
DMA Grant 2 (DMA Channel 8).
BR
6-1
I/O/S
Multiprocessing Bus Requests. Used by multiprocessing ADSP-2106xs to arbitrate for bus master-
ship. An ADSP-2106x only drives its own
BRx line (corresponding to the value of its ID
2-0
inputs) and
monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the unused
BRx pins
should be pulled high; the processor's own
BRx line must not be pulled high or low because it is an
output.
ID
2-0
I
Multiprocessing ID. Determines which multiprocessing bus request (
BR1 BR6) is used by ADSP-
2106x. ID = 001 corresponds to
BR1, ID = 010 corresponds to BR2, etc. ID = 000 in single-processor
systems. These lines are a system configuration selection which should be hardwired or only changed
at reset.
RPBA
I/S
Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor
bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system con-
figuration selection which must be set to the same value on every ADSP-2106x. If the value of RPBA is
changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-2106x.
CPA (O/D)
I/O
Core Priority Access. Asserting its
CPA pin allows the core processor of an ADSP-2106x bus slave
to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain
output that is connected to all ADSP-2106xs in the system. The
CPA pin has an internal 5 k
pull-up
resistor. If core access priority is not required in a system, the
CPA pin should be left unconnected.
DTx
O
Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k
internal pull-up resistor.
DRx
I
Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k
internal pull-up resistor.
TCLKx
I/O
Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k
internal pull-up resistor.
RCLKx
I/O
Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k
internal pull-up resistor.
10
ADSP-21060/ADSP-21060L
REV. D
Pin
Type
Function
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
LxDAT
3-0
I/O
Link Port Data (Link Ports 05). Each LxCLK pin has a 50 k
internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxCLK
I/O
Link Port Clock (Link Ports 05). Each LxCLK pin has a 50 k
internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
LxACK
I/O
Link Port Acknowledge (Link Ports 05). Each LxACK pin has a 50 k
internal pull-down resistor
that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-
bit EPROM. When EBOOT is low, the LBOOT and
BMS inputs determine booting mode. See table
below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When
LBOOT is low, the ADSP-2106x is configured for host processor booting or no booting. See table
below. This signal is a system configuration selection that should be hardwired.
BMS
I/O/T*
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1,
LBOOT = 0). In a multiprocessor system,
BMS is output by the bus master. Input: When low, indi-
cates that no booting will occur and that ADSP-2106x will begin executing instructions from external
memory. See table below. This input is a system configuration selection that should be hardwired.
*Three-statable only in EPROM boot mode (when
BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect
BMS to EPROM chip select.)
0
0
1 (Input)
Host Processor
0
1
1 (Input)
Link Port
0
0
0 (Input)
No Booting. Processor executes from external memory.
0
1
0 (Input)
Reserved
1
1
x (Input)
Reserved
CLKIN
I
Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN.
CLKIN may not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-2106x to a known state and begins execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k
internal pull-up
resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k
internal
pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine.
TRST must be asserted (pulsed low) after power-
up or held low for proper operation of the ADSP-2106x.
TRST has a 20 k
internal pull-up resistor.
EMU (O/D)
O
Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.
ICSA
O
Reserved, leave unconnected.
VDD
P
Power Supply; nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices. (30 pins).
GND
G
Power Supply Return. (30 pins).
NC
Do Not Connect. Reserved pins which must be left open and unconnected.
ADSP-21060/ADSP-21060L
11
REV. D
TARGET BOARD CONNECTOR FOR EZ-ICE
PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. The EZ-ICE probe
requires the ADSP-2106x's CLKIN, TMS, TCK,
TRST, TDI,
TDO,
EMU, and GND signals be made accessible on the target
system via a 14-pin connector (a 2 row
7 pin strip header) such
as that shown in Figure 5. The EZ-ICE
probe plugs directly onto
this connector for chip-on-board emulation. You must add this
connector to your target board design if you intend to use the
ADSP-2106x EZ-ICE. The total trace length between the EZ-
ICE connector and the furthest device sharing the EZ-ICE
JTAG pins should be limited to 15 inches maximum for guaran-
teed operation. This length restriction must include EZ-ICE
JTAG signals that are routed to one or more ADSP-2106x
devices, or a combination of ADSP-2106x devices and other
JTAG devices on the chain.
TOP VIEW
13
14
11
12
9
10
9
7
8
5
6
3
4
1
2
EMU
CLKIN (OPTIONAL)
TMS
TCK
TRST
TDI
TDO
GND
KEY (NO PIN)
BTMS
BTCK
BTRST
BTDI
GND
Figure 5. Target Board Connector For ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)
EMU
TRST
TRST
EMU
TRST
ADSP-2106x
#1
JTAG
DEVICE
(OPTIONAL)
ADSP-2106x
n
TDI
EZ-ICE
JTAG
CONNECTOR
OTHER
JTAG
CONTROLLER
OPTIONAL
TCK
TMS
EMU
TMS
TCK
TDO
CLKIN
TRST
TCK
TMS
TCK
TMS
TDI
TDO
TDI
TDO
TDO
TDI
Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location --
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1
0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK,
BTRST and BTDI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie
BTRST to GND
and tie or pull BTCK up to VDD. The
TRST pin must be
asserted after power-up (through
BTRST on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE
probe.
The JTAG signals are terminated on the EZ-ICE probe as
follows:
Signal
Termination
TMS
Driven through 22
Resistor (16 mA Driver)
TCK
Driven at 10 MHz through 22
Resistor (16 mA
Driver)
TRST* Active Low Driven through 22
Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 k
Resistor)
TDI
Driven by 22
Resistor (16 mA Driver)
TDO
One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU
Active Low 4.7 k
Pull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
*
TRST is driven low until the EZ-ICE
probe is turned on by the emulator at
software start-up. After software start-up,
TRST is driven high.
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
12
ADSP-21060/ADSP-21060L
REV. D
SYSTEM
CLKIN
EMU
5k
*
TDI
TDO
5k
*
TDI
EMU
TMS
TCK
TDO
TRST
CLKIN
*
OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
TDI
TDO
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
Connecting CLKIN to Pin 4 of the EZ-ICE
header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping and single-stepping mul-
tiple ADSP-21061 in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE
header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP-
21061/ADSP-21061L processors and the CLKIN pin on the
EZ-ICE
header must be minimal. If the skew is too large, syn-
chronous operations may be off by one or more cycles between
processors. For synchronous multiprocessor operation TCK,
TMS, CLKIN and
EMU should be treated as critical signals in
terms of skew, and should be laid out as short as possible on
your board. If TCK, TMS and CLKIN are driving a large num-
ber of ADSP-21061 (more than eight) in your system, then
treat them as a clock tree using multiple drivers to minimize
skew. (See Figure 7, JTAG Clock Tree, and Clock Distribution
in the High Frequency Design Considerations section of the
ADSP-2106x User's Manual, Second Edition.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO,
EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the ADSP-
2100 Family JTAG EZ-ICE User's Guide and Reference
.
ADSP-21060SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)
K Grade
Parameter
Test Conditions
Min
Max
Units
V
DD
Supply Voltage
4.75
5.25
V
T
CASE
Case Operating Temperature
0
+85
C
V
IH1
High Level Input Voltage
1
@ V
DD
= max
2.0
V
DD
+ 0.5
V
V
IH2
High Level Input Voltage
2
@ V
DD
= max
2.2
V
DD
+ 0.5
V
V
IL
Low Level Input Voltage
1, 2
@ V
DD
= min
0.5
0.8
V
NOTES
1
Applies to input and bidirectional pins: DATA
47-0
, ADDR
31-0
,
RD, WR, SW, ACK, SBTS, IRQ
2-0
, FLAG
3-0
,
HBG, CS, DMAR1, DMAR2, BR
6-1
, ID
2-0
, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK, EBOOT, LBOOT,
BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.
2
Applies to input pins: CLKIN,
RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)
Parameter
Test Conditions
Min
Max
Units
V
OH
High Level Output Voltage
1
@ V
DD
= min, I
OH
= 2.0 mA
2
4.1
V
V
OL
Low Level Output Voltage
1
@ V
DD
= min, I
OL
= 4.0 mA
2
0.4
V
I
IH
High Level Input Current
3, 4
@ V
DD
= max, V
IN
= V
DD
max
10
A
I
IL
Low Level Input Current
3
@ V
DD
= max, V
IN
= 0 V
10
A
I
ILP
Low Level Input Current
4
@ V
DD
= max, V
IN
= 0 V
150
A
I
OZH
Three-State Leakage Current
5, 6, 7, 8
@ V
DD
= max, V
IN
= V
DD
max
10
A
I
OZL
Three-State Leakage Current
5, 9
@ V
DD
= max, V
IN
= 0 V
10
A
I
OZHP
Three-State Leakage Current
9
@ V
DD
= max, V
IN
= V
DD
max
350
A
I
OZLC
Three-State Leakage Current
7
@ V
DD
= max, V
IN
= 0 V
1.5
mA
I
OZLA
Three-State Leakage Current
10
@ V
DD
= max, V
IN
= 1.5 V
350
A
I
OZLAR
Three-State Leakage Current
8
@ V
DD
= max, V
IN
= 0 V
4.2
mA
I
OZLS
Three-State Leakage Current
6
@ V
DD
= max, V
IN
= 0 V
150
A
C
IN
Input Capacitance
11, 12
f
IN
= 1 MHz, T
CASE
= 25
C, V
IN
= 2.5 V
4.7
pF
NOTES
1
1
Applies to output and bidirectional pins: DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3-0
, TIMEXP,
HBG, REDY, DMAG1,
DMAG2, BR
6-1
,
CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK,
BMS, TDO, EMU, ICSA.
1
2
See "Output Drive Currents" for typical drive current capabilities.
1
3
Applies to input pins:
SBTS, IRQ
2-0
,
HBR, CS, DMAR1, DMAR2, ID
2-0
, RPBA, EBOOT, LBOOT, CLKIN,
RESET, TCK.
1
4
Applies to input pins with internal pull-ups: DR0, DR1,
TRST, TMS, TDI.
1
5
Applies to three-statable pins: DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3-0
, REDY,
HBG, DMAG1, DMAG2, BMS, BR
61
,
TFS
X
, RFS
X
, TDO,
EMU. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another ADSP-21060 is
not requesting bus mastership.)
1
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
1
7
Applies to
CPA pin.
1
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another
ADSP-21060 is not requesting bus mastership).
1
9
Applies to three-statable pins with internal pull-downs: LxDAT
3-0
, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
ADSP-21060/ADSP-21060L
REV. D
13
14
ADSP-21060/ADSP-21060L
REV. D
POWER DISSIPATION ADSP-21060 (5 V)
These specifications apply to the internal power portion of V
DD
only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note "SHARC Power Dissipation Measurements."
Specifications are based on the following operating scenarios:
Operation
Peak Activity (I
DDINPEAK
)
High Activity (I
DDINHIGH
)
Low Activity (I
DDINLOW
)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK
I
DDINPEAK
+ %HIGH
I
DDINHIGH
+ %LOW
I
DDINLOW
+ %IDLE
I
DDIDLE
= power consumption
Parameter
Test Conditions
Max
Units
I
DDINPEAK
Supply Current (Internal)
1
t
CK
= 30 ns, V
DD
= max
745
mA
t
CK
= 25 ns, V
DD
= max
850
mA
I
DDINHIGH
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= max
575
mA
t
CK
= 25 ns, V
DD
= max
670
mA
I
DDINLOW
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= max
340
mA
t
CK
= 25 ns, V
DD
= max
390
mA
I
DDIDLE
Supply Current (Idle)
3
V
DD
= max
200
mA
NOTES
S
1
The test program used to measure I
DDINPEAK
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
I
DDINHIGH
is a composite average based on a range of high activity code. I
DDINLOW
is a composite average based on a range of low activity code.
3
Idle denotes ADSP-21060L state during execution of IDLE instruction.
ADSP-21060LSPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (3.3 V)
K Grade
Parameter
Test Conditions
Min
Max
Units
V
DD
Supply Voltage
3.15
3.45
V
T
CASE
Case Operating Temperature
0
+85
C
V
IH1
High Level Input Voltage
1
@ V
DD
= max
2.0
V
DD
+ 0.5
V
V
IH2
High Level Input Voltage
2
@ V
DD
= max
2.2
V
DD
+ 0.5
V
V
IL
Low Level Input Voltage
1, 2
@ V
DD
= min
0.5
0.8
V
NOTES
1
Applies to input and bidirectional pins: DATA
47-0
, ADDR
31-0
,
RD, WR, SW, ACK, SBTS, IRQ
2-0
, FLAG
3-0
,
HBG, CS, DMAR1, DMAR2, BR
6-1
, ID
2-0
, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK, EBOOT, LBOOT,
BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0,
RCLK1.
2
Applies to input pins: CLKIN,
RESET, TRST.
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter
Test Conditions
Min
Max
Units
V
OH
High Level Output Voltage
1
@ V
DD
= min, I
OH
= 2.0 mA
2
2.4
V
V
OL
Low Level Output Voltage
1
@ V
DD
= min, I
OL
= 4.0 mA
2
0.4
V
I
IH
High Level Input Current
3, 4
@ V
DD
= max, V
IN
= V
DD
max
10
A
I
IL
Low Level Input Current
3
@ V
DD
= max, V
IN
= 0 V
10
A
I
ILP
Low Level Input Current
4
@ V
DD
= max, V
IN
= 0 V
150
A
I
OZH
Three-State Leakage Current
5, 6, 7, 8
@ V
DD
= max, V
IN
= V
DD
max
10
A
I
OZL
Three-State Leakage Current
5, 9
@ V
DD
= max, V
IN
= 0 V
10
A
I
OZHP
Three-State Leakage Current
9
@ V
DD
= max, V
IN
= V
DD
max
350
A
I
OZLC
Three-State Leakage Current
7
@ V
DD
= max, V
IN
= 0 V
1.5
mA
I
OZLA
Three-State Leakage Current
10
@ V
DD
= max, V
IN
= 1.5 V
350
A
I
OZLAR
Three-State Leakage Current
8
@ V
DD
= max, V
IN
= 0 V
4.2
mA
I
OZLS
Three-State Leakage Current
6
@ V
DD
= max, V
IN
= 0 V
150
A
C
IN
Input Capacitance
11, 12
f
IN
= 1 MHz, T
CASE
= 25
C, V
IN
= 2.5 V
4.7
pF
NOTES
S
1
1
Applies to output and bidirectional pins: DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3-0
, TIMEXP,
HBG, REDY, DMAG1,
DMAG2, BR
6-1
,
CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK,
BMS, TDO, EMU, ICSA.
1
2
See "Output Drive Currents" for typical drive current capabilities.
1
3
Applies to input pins:
SBTS, IRQ
2-0
,
HBR, CS, DMAR1, DMAR2, ID
2-0
, RPBA, EBOOT, LBOOT, CLKIN,
RESET, TCK.
1
4
Applies to input pins with internal pull-ups: DR0, DR1,
TRST, TMS, TDI.
1
5
Applies to three-statable pins: DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK, FLAG
3-0
, REDY,
HBG, DMAG1, DMAG2, BMS, BR
61
,
TFS
X
, RFS
X
, TDO,
EMU. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another ADSP-21060 is
not requesting bus mastership.)
1
6
Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.
1
7
Applies to
CPA pin.
1
8
Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k
during reset in a multiprocessor system, when ID
2-0
= 001 and another
ADSP-21060 is not requesting bus mastership).
1
9
Applies to three-statable pins with internal pull-downs: LxDAT
3-0
, LxCLK, LxACK.
10
Applies to ACK pin when keeper latch enabled.
11
Applies to all signal pins.
12
Guaranteed but not tested.
Specifications subject to change without notice.
ADSP-21060/ADSP-21060L
15
REV. D
16
ADSP-21060/ADSP-21060L
REV. D
POWER DISSIPATION ADSP-21060L (3.3 V)
These specifications apply to the internal power portion of V
DD
only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note "SHARC Power Dissipation Measurements."
Specifications are based on the following operating scenarios:
Operation
Peak Activity (I
DDINPEAK
)
High Activity (I
DDINHIGH
)
Low Activity (I
DDINLOW
)
Instruction Type
Multifunction
Multifunction
Single Function
Instruction Fetch
Cache
Internal Memory
Internal Memory
Core Memory Access
2 per Cycle (DM and PM)
1 per Cycle (DM)
None
Internal Memory DMA
1 per Cycle
1 per 2 Cycles
1 per 2 Cycles
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK
I
DDINPEAK
+ %HIGH
I
DDINHIGH
+ %LOW
I
DDINLOW
+ %IDLE
I
DDIDLE
= power consumption
Parameter
Test Conditions
Max
Units
I
DDINPEAK
Supply Current (Internal)
1
t
CK
= 30 ns, V
DD
= max
540
mA
t
CK
= 25 ns, V
DD
= max
600
mA
I
DDINHIGH
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= max
425
mA
t
CK
= 25 ns, V
DD
= max
475
mA
I
DDINLOW
Supply Current (Internal)
2
t
CK
= 30 ns, V
DD
= max
250
mA
t
CK
= 25 ns, V
DD
= max
275
mA
I
DDIDLE
Supply Current (Idle)
3
V
DD
= max
180
mA
NOTES
S
1
The test program used to measure I
DDINPEAK
represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.
2
I
DDINHIGH
is a composite average based on a range of high activity code. I
DDINLOW
is a composite average based on a range of low activity code.
3
Idle denotes ADSP-21060L state during execution of IDLE instruction.
ADSP-21060/ADSP-21060L
17
REV. D
ABSOLUTE MAXIMUM RATINGS (5 V)*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . 0.5 V to V
DD
+ 0.5 V
Output Voltage Swing . . . . . . . . . . . . . 0.5 V to V
DD
+ 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280
C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS (3.3 V)*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . 0.5 V to V
DD
+ 0.5 V
Output Voltage Swing . . . . . . . . . . . . . 0.5 V to V
DD
+ 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280
C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
TIMING SPECIFICATIONS
Two speed grades of the ADSP-21060 are offered, 40 MHz and
33.3 MHz. The specifications shown are based on a CLKIN
frequency of 40 MHz (t
CK
= 25 ns). The DT derating allows
specifications at other CLKIN frequencies (within the minmax
range of the t
CK
specification; see Clock Input below). DT is
the difference between the actual CLKIN period and a CLKIN
period of 25 ns:
DT = t
CK
25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
See Figure 28 under Test Conditions for voltage reference
levels.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing--circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2106x features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
18
ADSP-21060/ADSP-21060L
REV. D
ADSP-21060
ADSP-21060L
40 MHz
33 MHz
40 MHz
33 MHz
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
Clock Input
Timing Requirements:
t
CK
CLKIN Period
25
100
30
100
25
100
30
100
ns
t
CKL
CLKIN Width Low
7
7
8.75
8.75
ns
t
CKH
CLKIN Width High
5
5
5
5
ns
t
CKRF
CLKIN Rise/Fall (0.4 V2.0 V)
3
3
3
3
ns
CLKIN
t
CKH
t
CK
t
CKL
Figure 8. Clock Input
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Reset
Timing Requirements:
t
WRST
RESET Pulsewidth Low
1
4t
CK
4t
CK
ns
t
SRST
RESET Setup before CLKIN High
2
14 + DT/2
t
CK
14 + DT/2
t
CK
ns
NOTES
1
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET
is low, assuming stable V
DD
and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
RESET
t
WRST
t
SRST
Figure 9. Reset
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Interrupts
Timing Requirements:
t
SIR
IRQ2-0 Setup before CLKIN High
1
18 + 3DT/4
18 + 3DT/4
ns
t
HIR
IRQ2-0 Hold before CLKIN High
1
12 + 3DT/4
12 + 3DT/4
ns
t
IPW
IRQ2-0 Pulsewidth
2
2 + t
CK
2 + t
CK
ns
NOTES
1
Only required for
IRQx recognition in the following cycle.
2
Applies only if t
SIR
and t
HIR
requirements are not met.
CLKIN
IRQ2-0
t
IPW
t
SIR
t
HIR
Figure 10. Interrupts
ADSP-21060/ADSP-21060L
19
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timer
Switching Characteristic:
t
DTEX
CLKIN High to TIMEXP
15
15
ns
CLKIN
t
DTEX
t
DTEX
TIMEXP
Figure 11. Timer
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Flags
Timing Requirements:
t
SFI
FLAG3-0
IN
Setup before CLKIN High
1
8 + 5DT/16
8 + 5DT/16
ns
t
HFI
FLAG3-0
IN
Hold after CLKIN High
1
0 5DT/16
0 5DT/16
ns
t
DWRFI
FLAG3-0
IN
Delay after
RD/WR Low
1
5 + 7DT/16
5 + 7DT/16
ns
t
HFIWR
FLAG3-0
IN
Hold after
RD/WR Deasserted
1
0
0
ns
Switching Characteristics:
t
DFO
FLAG3-0
OUT
Delay after CLKIN High
16
16
ns
t
HFO
FLAG3-0
OUT
Hold after CLKIN High
4
4
ns
t
DFOE
CLKIN High to FLAG3-0
OUT
Enable
3
3
ns
t
DFOD
CLKIN High to FLAG3-0
OUT
Disable
14
14
ns
NOTE
1
Flag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
CLKIN
FLAG3-0
OUT
FLAG OUTPUT
t
DFO
t
HFO
t
DFO
t
DFOD
t
DFOE
CLKIN
RD, WR
FLAG INPUT
t
SFI
t
HFI
t
HFIWR
t
DWRFI
FLAG3-0
IN
Figure 12. Flags
20
ADSP-21060/ADSP-21060L
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
DAD
Address, Selects Delay to Data Valid
1, 2
18 + DT + W
18 + DT + W
ns
t
DRLD
RD Low to Data Valid
1
12 + 5DT/8 + W
12 + 5DT/8 + W
ns
t
HDA
Data Hold from Address, Selects
3
0.5
0.5
ns
t
HDRH
Data Hold from
RD High
3
2.0
2.0
ns
t
DAAK
ACK Delay from Address, Selects
2, 4
14 + 7DT/8 + W
14 + 7DT/8 + W
ns
t
DSAK
ACK Delay from
RD Low
4
8 + DT/2 + W
8 + DT/2 + W
ns
Switching Characteristics:
t
DRHA
Address, Selects Hold after
RD High
0 + H
0 + H
ns
t
DARL
Address, Selects to
RD Low
2
2 + 3DT/8
2 + 3DT/8
ns
t
RW
RD Pulsewidth
12.5 + 5DT/8 + W
12.5 + 5DT/8 + W
ns
t
RWR
RD High to WR, RD, DMAGx Low
8 + 3DT/8 + HI
8 + 3DT/8 + HI
ns
t
SADADC
Address, Selects Setup before
ADRCLK High
2
0 + DT/4
0 + DT/4
ns
W = (number of wait states specified in WAIT register)
t
CK.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1
Data Delay/Setup: User must meet t
DAD
or t
DRLD
or synchronous spec t
SSDATI
.
2
The falling edge of
MSx, SW, BMS is referenced.
3
Data Hold: User must meet t
HDA
or t
HDRH
or synchronous spec t
HSDATI
. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
4
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
WR, DMAG
ACK
DATA
RD
ADDRESS
MSx, SW
BMS
t
DARL
t
RW
t
DAD
t
SADADC
t
DAAK
t
HDRH
t
HDA
t
RWR
t
DRLD
ADRCLK
(OUT)
t
DRHA
t
DSAK
Figure 13. Memory Read--Bus Master
Memory Read--Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
ADSP-21060/ADSP-21060L
21
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
DAAK
ACK Delay from Address, Selects
1, 2
14 + 7DT/8 + W
14 + 7DT/8 + W
ns
t
DSAK
ACK Delay from
WR Low
1
8 + DT/2 + W
8 + DT/2 + W
ns
Switching Characteristics:
t
DAWH
Address, Selects to
WR Deasserted
2
17 + 15DT/16 + W
17 + 15DT/16 + W
ns
t
DAWL
Address, Selects to
WR Low
2
3 + 3DT/8
3 + 3DT/8
ns
t
WW
WR Pulsewidth
12 + 9DT/16 + W
12 + 9DT/16 + W
ns
t
DDWH
Data Setup before
WR High
7 + DT/2 + W
7 + DT/2 + W
ns
t
DWHA
Address Hold after
WR Deasserted
0.5 + DT/16 + H
0.5 + DT/16 + H
ns
t
DATRWH
Data Disable after
WR Deasserted
3
1 + DT/16 + H
6 + DT/16 + H
1 + DT/16 + H
6 + DT/16 + H
ns
t
WWR
WR High to WR, RD, DMAGx Low
8 + 7DT/16 + H
8 + 7DT/16 + H
ns
t
DDWR
Data Disable before
WR or RD Low
5 + 3DT/8 + I
5 + 3DT/8 + I
ns
t
WDE
WR Low to Data Enabled
1 + DT/16
1 + DT/16
ns
t
SADADC
Address, Selects to ADRCLK High
2
0 + DT/4
0 + DT/4
ns
Memory Write--Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-2106x is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/WriteBus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
W = (number of wait states specified in WAIT register)
t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
2
The falling edge of
MSx, SW, BMS is referenced.
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
RD , DMAG
ACK
DATA
WR
ADDRESS
MSx , SW
BMS
t
DAWL
t
WW
t
SADADC
t
DAAK
t
WWR
t
WDE
ADRCLK
(OUT)
t
DDWR
t
DATRWH
t
DWHA
t
DDWH
t
DAWH
t
DSAK
Figure 14. Memory Write--Bus Master
22
ADSP-21060/ADSP-21060L
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SSDATI
Data Setup before CLKIN
3 + DT/8
3 + DT/8
ns
t
HSDATI
Data Hold after CLKIN
3.5 DT/8
3.5 DT/8
ns
t
DAAK
ACK Delay after Address,
MSx,
SW, BMS
1, 2
14 + 7 DT/8 + W
14 + 7 DT/8 + W
ns
t
SACKC
ACK Setup before CLKIN
2
6.5 + DT/4
6.5 + DT/4
ns
t
HACK
ACK Hold after CLKIN
1 DT/4
1 DT/4
ns
Switching Characteristics:
t
DADRO
Address,
MSx, BMS, SW Delay
after CLKIN
1
7 DT/8
7 DT/8
ns
t
HADRO
Address,
MSx, BMS, SW Hold
after CLKIN
1 DT/8
1 DT/8
ns
t
DPGC
PAGE Delay after CLKIN
9 + DT/8
16 + DT/8
9 + DT/8
16 + DT/8
ns
t
DRDO
RD High Delay after CLKIN
2 DT/8
4 DT/8
2 DT/8
4 DT/8
ns
t
DWRO
WR High Delay after CLKIN
3 3DT/16
4 3DT/16
3 3DT/16
4 3DT/16
ns
t
DRWL
RD/WR Low Delay after CLKIN
8 + DT/4
12.5 + DT/4
8 + DT/4
12.5 + DT/4
ns
t
SDDATO
Data Delay after CLKIN
19 + 5DT/16
19 + 5DT/16
ns
t
DATTR
Data Disable after CLKIN
3
0 DT/8
7 DT/8
0 DT/8
7 DT/8
ns
t
DADCCK
ADRCLK Delay after CLKIN
4 + DT/8
10 + DT/8
4 + DT/8
10 + DT/8
ns
t
ADRCK
ADRCLK Period
t
CK
t
CK
ns
t
ADRCKH
ADRCLK Width High
(t
CK
/2) 2
(t
CK
/2) 2
ns
t
ADRCKL
ADRCLK Width Low
(t
CK
/2) 2
(t
CK
/2) 2
ns
W = (number of Wait states specified in WAIT register)
t
CK
.
NOTES
1
The falling edge of
MSx, SW, BMS is referenced.
2
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or synchronous specification t
SACKC
for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).
3
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Synchronous Read/Write--Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN--relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read--Bus
Master and Memory Write--Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave's timing requirements for synchronous
read/writes (see Synchronous Read/Write--Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
ADSP-21060/ADSP-21060L
23
REV. D
CLKIN
ADRCLK
ADDRESS
MSx, SW
ACK
(IN)
PAGE
RD
DATA
(OUT)
WR
t
DADCCK
t
ADRCK
t
ADRCKL
t
HADRO
t
DAAK
t
DPGC
t
DRWL
t
SACKC
t
HACK
t
HSDATI
t
SSDATI
t
DRDO
t
DWRO
t
DATTR
t
SDDATO
t
DRWL
DATA
(IN)
t
DADRO
t
ADRCKH
WRITE CYCLE
READ CYCLE
Figure 15. Synchronous Read/Write--Bus Master
24
ADSP-21060/ADSP-21060L
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SADRI
Address,
SW Setup before CLKIN
15 + DT/2
15 + DT/2
ns
t
HADRI
Address,
SW Hold before CLKIN
5 + DT/2
5 + DT/2
ns
t
SRWLI
RD/WR Low Setup before CLKIN
1
9.5 + 5DT/16
9.5 + 5DT/16
ns
t
HRWLI
RD/WR Low Hold after CLKIN
4 5DT/16
8 + 7DT/16
4 5DT/16
8 + 7DT/16
ns
t
RWHPI
RD/WR Pulse High
3
3
ns
t
SDATWH
Data Setup before
WR High
5
5
ns
t
HDATWH
Data Hold after
WR High
1
1
ns
Switching Characteristics:
t
SDDATO
Data Delay after CLKIN
19 + 5DT/16
19 + 5DT/16
ns
t
DATTR
Data Disable after CLKIN
2
0 DT/8
7 DT/8
0 DT/8
7 DT/8
ns
t
DACKAD
ACK Delay after Address,
SW
3
9
9
ns
t
ACKTR
ACK Disable after CLKIN
3
1 DT/8
6 DT/8
1 DT/8
6 DT/8
ns
NOTES
1
t
SRWLI
(min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t
SRWLI
(min)
= 4 + DT/8.
2
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
3
t
DACKAD
is true only if the address and
SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with t
ACKTR
.
CLKIN
ADDRESS
SW
ACK
RD
DATA
(OUT)
WR
WRITE ACCESS
t
SADRI
t
HADRI
t
DACKAD
t
ACKTR
t
RWHPI
t
HRWLI
t
SRWLI
t
SDDATO
t
DATTR
t
SRWLI
t
HRWLI
t
RWHPI
t
HDATWH
t
SDATWH
DATA
(IN)
READ ACCESS
Figure 16. Synchronous Read/Write--Bus Slave
Synchronous Read/Write--Bus Slave
Use these specifications for ADSP-2106x bus master accesses of
a slave's IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
ADSP-21060/ADSP-21060L
25
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
HBGRCSV
HBG Low to RD/WR/CS Valid
1
20+ 5DT/4
20+ 5DT/4
ns
t
SHBRI
HBR Setup before CLKIN
2
20 + 3DT/4
20 + 3DT/4
ns
t
HHBRI
HBR Hold before CLKIN
2
14 + 3DT/4
14 + 3DT/4
ns
t
SHBGI
HBG Setup before CLKIN
13 + DT/2
13 + DT/2
ns
t
HHBGI
HBG Hold before CLKIN High
6 + DT/2
6 + DT/2
ns
t
SBRI
BRx, CPA Setup before CLKIN
3
13 + DT/2
13 + DT/2
ns
t
HBRI
BRx, CPA Hold before CLKIN High
6 + DT/2
6 + DT/2
ns
t
SRPBAI
RPBA Setup before CLKIN
21 + 3DT/4
21 + 3DT/4
ns
t
HRPBAI
RPBA Hold before CLKIN
12 + 3DT/4
12 + 3DT/4
ns
Switching Characteristics:
t
DHBGO
HBG Delay after CLKIN
7 DT/8
7 DT/8
ns
t
HHBGO
HBG Hold after CLKIN
2 DT/8
2 DT/8
ns
t
DBRO
BRx Delay after CLKIN
7 DT/8
7 DT/8
ns
t
HBRO
BRx Hold after CLKIN
2 DT/8
2 DT/8
ns
t
DCPAO
CPA Low Delay after CLKIN
8 DT/8
8 DT/8
ns
t
TRCPA
CPA Disable after CLKIN
2 DT/8
4.5 DT/8
2 DT/8
4.5 DT/8
ns
t
DRDYCS
REDY (O/D) or (A/D) Low from
CS
and
HBR Low
4
8.5
9.25
ns
t
TRDYHG
REDY (O/D) Disable or REDY (A/D)
High from
HBG
4
44 + 23DT/16
44 + 23DT/16
ns
t
ARDYTR
REDY (A/D) Disable from
CS or
HBR High
4
10
10
ns
NOTES
1
For first asynchronous access after
HBR and CS asserted, ADDR
31-0
must be a non-MMS value 1/2 t
CK
before
RD or WR goes low or by t
HBGRCSV
after
HBG goes
low. This is easily accomplished by driving an upper address signal high when
HBG is asserted. See the "Host Processor Control of the ADSP-2106x" section in the
ADSP-2106x SHARC User's Manual, Second Edition.
2
Only required for recognition in the current cycle.
3
CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4
(O/D) = open drain, (A/D) = active drive.
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106xs (
BRx) or a host processor
(
HBR, HBG).
26
ADSP-21060/ADSP-21060L
REV. D
CLKIN
HBR
HBG
(OUT)
BRx
(OUT)
HBG (IN)
BRx (IN)
REDY (O/D)
RD
WR
CS
HBG (OUT)
REDY (A/D)
RPBA
CPA (OUT)
(O/D)
CPA (IN) (O/D)
t
SHBGI
t
SBRI
t
HHBGI
t
HBRI
t
HBGRCSV
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
t
DRDYCS
t
TRDYHG
t
SHBRI
t
HHBRI
t
HHBGO
t
DHBGO
t
HBRO
t
DBRO
t
DCPAO
t
TRCPA
t
ARDYTR
t
SRPBAI
t
HRPBAI
HBR AND CS
Figure 17. Multiprocessor Bus Request and Host Bus Request
ADSP-21060/ADSP-21060L
27
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Read Cycle
Timing Requirements:
t
SADRDL
Address Setup/
CS Low before RD Low
1
0
0
ns
t
HADRDH
Address Hold/
CS Hold Low after RD
0
0
ns
t
WRWH
RD/WR High Width
6
6
ns
t
DRDHRDY
RD High Delay after REDY (O/D) Disable
0
0
ns
t
DRDHRDY
RD High Delay after REDY (A/D) Disable
0
0
ns
Switching Characteristics:
t
SDATRDY
Data Valid before REDY Disable from Low
2
2
ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay after
RD Low
10
10.5
ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth
for Read
45 + 21DT/16
45 + 21DT/16
ns
t
HDARWH
Data Disable after
RD High
2
8
2
8.5
ns
Write Cycle
Timing Requirements:
t
SCSWRL
CS Low Setup before WR Low
0
0
ns
t
HCSWRH
CS Low Hold after WR High
0
0
ns
t
SADWRH
Address Setup before
WR High
5
5
ns
t
HADWRH
Address Hold after
WR High
2
2
ns
t
WWRL
WR Low Width
7
7
ns
t
WRWH
RD/WR High Width
6
6
ns
t
DWRHRDY
WR High Delay after REDY
(O/D) or (A/D) Disable
0
0
ns
t
SDATWH
Data Setup before
WR High
5
5
ns
t
HDATWH
Data Hold after
WR High
1
1
ns
Switching Characteristics:
t
DRDYWRL
REDY (O/D) or (A/D) Low Delay
after
WR/CS Low
10
10.5
ns
t
RDYPWR
REDY (O/D) or (A/D) Low Pulsewidth
for Write
15 + 7DT/16
15 + 7DT/16
ns
t
SRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
1 + 7DT/16
8 + 7DT/16
1 + 7DT/16
8 + 7DT/16
ns
NOTE
1
Not required if
RD and address are valid t
HBGRCSV
after
HBG goes low. For first access after HBR asserted, ADDR
31-0
must be a non-MMS value 1/2 t
CLK
before
RD
or
WR goes low or by t
HBGRCSV
after HBG goes low. This is easily accomplished by driving an upper address signal high when
HBG is asserted. See the "Host Proces-
sor Control of the ADSP-2106x" section in the ADSP-2106x SHARC User's Manual, Second Edition.
CLKIN
REDY (O/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
t
SRDYCK
REDY (A/D)
Figure 18a. Synchronous REDY Timing
Asynchronous Read/Write--Host to ADSP-2106x
Use these specifications for asynchronous host processor accesses
of an ADSP-2106x, after the host has asserted
CS and HBR
(low). After
HBG is returned by the ADSP-2106x, the host can
drive the
RD and WR pins to access the ADSP-2106x's internal
memory or IOP registers.
HBR and HBG are assumed low for
this timing.
28
ADSP-21060/ADSP-21060L
REV. D
t
SADRDL
REDY (O/D)
RD
t
DRDYRDL
t
WRWH
t
HADRDH
t
HDARWH
t
RDYPRD
t
DRDHRDY
t
SDATRDY
READ CYCLE
ADDRESS/
CS
DATA (OUT)
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
t
SDATWH
t
HDATWH
t
WWRL
REDY (O/D)
WR
t
DRDYWRL
t
WRWH
t
HADWRH
t
RDYPWR
t
DWRHRDY
WRITE CYCLE
t
SADWRH
DATA (IN)
ADDRESS
REDY (A/D)
t
SCSWRL
CS
t
HCSWRH
Figure 18b. Asynchronous Read/Write--Host to ADSP-2106x
ADSP-21060/ADSP-21060L
29
REV. D
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
STSCK
SBTS Setup before CLKIN
12 + DT/2
12 + DT/2
ns
t
HTSCK
SBTS Hold before CLKIN
6 + DT/2
6 + DT/2
ns
Switching Characteristics:
t
MIENA
Address/Select Enable after CLKIN
1.5 DT/8
1.25 DT/8
ns
t
MIENS
Strobes Enable after CLKIN
1
1.5 DT/8
1.5 DT/8
ns
t
MIENHG
HBG Enable after CLKIN
1.5 DT/8
1.5 DT/8
ns
t
MITRA
Address/Select Disable after CLKIN
0 DT/4
0 DT/4
ns
t
MITRS
Strobes Disable after CLKIN
1
1.5 DT/4
1.5 DT/4
ns
t
MITRHG
HBG Disable after CLKIN
2.0 DT/4
2.0 DT/4
ns
t
DATEN
Data Enable after CLKIN
2
9 + 5DT/16
9 + 5DT/16
ns
t
DATTR
Data Disable after CLKIN
2
0 DT/8
7 DT/8
0 DT/8
7 DT/8
ns
t
ACKEN
ACK Enable after CLKIN
2
7.5 + DT/4
7.5 + DT/4
ns
t
ACKTR
ACK Disable after CLKIN
2
1 DT/8
6 DT/8
1 DT/8
6 DT/8
ns
t
ADCEN
ADRCLK Enable after CLKIN
2 DT/8
2 DT/8
ns
t
ADCTR
ADRCLK Disable after CLKIN
8 DT/4
8 DT/4
ns
t
MTRHBG
Memory Interface Disable before
HBG Low
3
0 + DT/8
0 + DT/8
ns
t
MENHBG
Memory Interface Enable after
HBG High
3
19 + DT
19 + DT
ns
NOTES
1
Strobes =
RD, WR, SW, PAGE, DMAG.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address,
RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
Three-State Timing--Bus Master, Bus Slave,
HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
CLKIN
SBTS
ACK
t
MITRA,
t
MITRS,
t
MITRHG
t
STSCK
t
HTSCK
t
DATTR
t
DATEN
t
ACKTR
t
ACKEN
t
ADCTR
t
ADCEN
ADRCLK
DATA
t
MIENA,
t
MIENS,
t
MIENHG
MEMORY
INTERFACE
Figure 19a. Three-State Timing (Bus Transition Cycle,
SBTS Assertion)
MEMORY
INTERFACE
t
MENHBG
t
MTRHBG
HBG
MEMORY INTERFACE = ADDRESS,
RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
Figure 19b. Three-State Timing (Host Transition Cycle)
and the
SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the
SBTS pin.
30
ADSP-21060/ADSP-21060L
REV. D
transfer is controlled by ADDR
31-0
,
RD, WR, MS
3-0
, and ACK
(not
DMAG). For Paced Master mode, the Memory ReadBus
Master, Memory WriteBus Master, and Synchronous Read/
WriteBus Master timing specifications for ADDR
31-0
,
RD, WR,
MS
3-0
,
SW, PAGE, DATA
47-0
, and ACK also apply.
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
SDRLC
DMARx Low Setup before CLKIN
1
5
5
ns
t
SDRHC
DMARx High Setup before CLKIN
1
5
5
ns
t
WDR
DMARx Width Low
(Nonsynchronous)
6
6
ns
t
SDATDGL
Data Setup after
DMAGx Low
2
10 + 5DT/8
10 + 5DT/8
ns
t
HDATIDG
Data Hold after
DMAGx High
2
2
ns
t
DATDRH
Data Valid after
DMARx High
2
16 + 7DT/8
16 + 7DT/8
ns
t
DMARLL
DMARx Low Edge to Low Edge
23 + 7DT/8
23 + 7DT/8
ns
t
DMARH
DMARx Width High
6
6
ns
Switching Characteristics:
t
DDGL
DMAGx Low Delay after CLKIN
9 + DT/4
15 + DT/4
9 + DT/4
15 + DT/4
ns
t
WDGH
DMAGx High Width
6 + 3DT/8
6 + 3DT/8
ns
t
WDGL
DMAGx Low Width
12 + 5DT/8
12 + 5DT/8
ns
t
HDGC
DMAGx High Delay after CLKIN
2 DT/8
6 DT/8
2 DT/8
6 DT/8
ns
t
VDATDGH
Data Valid before
DMAGx High
3
8 + 9DT/16
8 + 9DT/16
ns
t
DATRDGH
Data Disable after
DMAGx High
4
0
7
0
7
ns
t
DGWRL
WR Low before DMAGx Low
0
2
0
2
ns
t
DGWRH
DMAGx Low before WR High
10 + 5DT/8 + W
10 + 5DT/8 + W
ns
t
DGWRR
WR High before DMAGx High
1 + DT/16
3 + DT/16
1 + DT/16
3 + DT/16
ns
t
DGRDL
RD Low before DMAGx Low
0
2
0
2
ns
t
DRDGH
RD Low before DMAGx High
11 + 9DT/16 + W
11 + 9DT/16 + W
ns
t
DGRDR
RD High before DMAGx High
0
3
0
3
ns
t
DGWR
DMAGx High to WR, RD, DMAGx
Low
5 + 3DT/8 + HI
5 + 3DT/8 + HI
ns
t
DADGH
Address/Select Valid to
DMAGx High 17 + DT
17 + DT
ns
t
DDGHA
Address/Select Hold after
DMAGx
High
0.5
0.5
ns
W = (number of wait states specified in WAIT register)
t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
NOTES
1
Only required for recognition in the current cycle.
2
t
SDATDGL
is the data setup requirement if
DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the
data can be driven t
DATDRH
after
DMARx is brought high.
3
t
VDATDGH
is valid if
DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then t
VDATDGH
= 8 + 9DT/16 + (n
t
CK
) where
n equals the number of extra cycles that the access is prolonged.
4
See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
DMA Handshake
These specifications describe the three DMA handshake modes.
In all three modes DMAR is used to initiate transfers. For hand-
shake mode, DMAG controls the latching or enabling of data
externally. For external handshake mode, the data transfer is
controlled by the ADDR
31-0
,
RD, WR, SW, PAGE, MS
3-0
,
ACK, and
DMAG signals. For Paced Master mode, the data
ADSP-21060/ADSP-21060L
31
REV. D
CLKIN
t
SDRLC
DMARx
DATA (FROM
ADSP-2106x TO
EXTERNAL DRIVE)
DATA (FROM
EXTERNAL DRIVE
TO ADSP-2106x)
RD
WR
t
WDR
t
SDRHC
t
DMARH
t
DMARLL
t
HDGC
t
WDGH
t
DDGL
t
WDGL
DMAGx
t
VDATDGH
t
DATDRH
t
DATRDGH
t
HDATIDG
t
DGWRL
t
DGWRH
t
DGWRR
t
DGRDL
t
DRDGH
t
DGRDR
t
SDATDGL
*
MEMORY READ BUS MASTER, MEMORY WRITE BUS MASTER, AND SYNCHRONOUS READ/WRITE BUS MASTER
TIMING SPECIFICATIONS FOR ADDR
31-0
,
RD, WR, SW, MS
3-0
AND ACK ALSO APPLY HERE.
(EXTERNAL DEVICE
TO EXTERNAL
MEMORY)
(EXTERNAL
MEMORY TO
EXTERNAL DEVICE)
TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE)
t
DDGHA
ADDRESS
MSx,
SW
t
DADGH
Figure 20. DMA Handshake Timing
32
ADSP-21060/ADSP-21060L
REV. D
Link Ports: 1
CLK Speed Operation
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Receive
Timing Requirements:
t
SLDCL
Data Setup before LCLK Low
3.5
3
ns
t
HLDCL
Data Hold after LCLK Low
3
3
ns
t
LCLKIW
LCLK Period (1
Operation)
t
CK
t
CK
ns
t
LCLKRWL
LCLK Width Low
6
6
ns
t
LCLKRWH
LCLK Width High
5
5
ns
Switching Characteristics:
t
DLAHC
LACK High Delay after CLKIN High
18 + DT/2
28.5 + DT/2
18 + DT/2
28.5 + DT/2
ns
t
DLALC
LACK Low Delay after LCLK High
1
3
13
3
13
ns
t
ENDLK
LACK Enable from CLKIN
5 + DT/2
5 + DT/2
ns
t
TDLK
LACK Disable from CLKIN
20 + DT/2
20 + DT/2
ns
Transmit
Timing Requirements:
t
SLACH
LACK Setup before LCLK High
18
20
ns
t
HLACH
LACK Hold after LCLK High
7
7
ns
Switching Characteristics:
t
DLCLK
LCLK Delay after CLKIN (1
operation)
15.5
16.5
ns
t
DLDCH
Data Delay after LCLK High
3
2.5
ns
t
HLDCH
Data Hold after LCLK High
3
3
ns
t
LCLKTWL
LCLK Width Low
(t
CK
/2) 2
(t
CK
/2) + 2
(t
CK
/2) 1
(t
CK
/2) + 1.25
ns
t
LCLKTWH
LCLK Width High
(t
CK
/2) 2
(t
CK
/2) + 2
(t
CK
/2) 1.25
(t
CK
/2) + 1.0
ns
t
DLACLK
LCLK Low Delay after LACK High
(t
CK
/2) + 8.5
(3
t
CK
/2) + 17
(t
CK
/2) + 8.0
(3
t
CK
/2) + 17.5
ns
t
ENDLK
LDAT, LCLK Enable after CLKIN
5 + DT/2
5 + DT/2
ns
t
TDLK
LDAT, LCLK Disable after CLKIN
20 + DT/2
20 + DT/2
ns
Link Port Service Request Interrupts: 1
and
2
Speed Operations
Timing Requirements:
t
SLCK
LACK/LCLK Setup before CLKIN Low
2
10
10
ns
t
HLCK
LACK/LCLK Hold after CLKIN Low
2
2
2
ns
NOTES
1
LACK will go low with t
DLALC
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver's link buffer is not about to fill.
2
Only required for interrupt recognition in the current cycle.
ADSP-21060/ADSP-21060L
33
REV. D
Link Ports: 2
CLK Speed Operation
Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can
be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in
LDATA relative to LCLK, (setup skew = t
LCLKTWH
min t
DLDCH
t
SLDCL
). Hold skew is the maximum delay that can be intro-
duced in LCLK relative to LDATA, (hold skew = t
LCLKTWL
min t
HLDCH
t
HLDCL
). Calculations made directly from 2
speed
specifications will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew
times shown below are calculated to include only one tester guardband.
ADSP-21060 Setup Skew
= 1.93 ns max
ADSP-21060 Hold Skew
= 2.95 ns max
ADSP-21060L Setup Skew = 1.87 ns max
ADSP-21060L Hold Skew = 1.69 ns max
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Receive
Timing Requirements:
t
SLDCL
Data Setup before LCLK Low
2.5
2.25
ns
t
HLDCL
Data Hold after LCLK Low
2.25
2.25
ns
t
LCLKIW
LCLK Period (2
Operation)
t
CK
/2
t
CK
/2
ns
t
LCLKRWL
LCLK Width Low
4.5
5.0
ns
t
LCLKRWH
LCLK Width High
4.25
4.0
ns
Switching Characteristics:
t
DLAHC
LACK High Delay after CLKIN High
18 + DT/2
28.5 + DT/2
18 + DT/2
29.5 + DT/2
ns
t
DLALC
LACK Low Delay after LCLK High
1
6
16
6
18
ns
Transmit
Timing Requirements:
t
SLACH
LACK Setup before LCLK High
19
19
ns
t
HLACH
LACK Hold after LCLK High
6.75
6.5
ns
Switching Characteristics:
t
DLCLK
LCLK Delay after CLKIN
8
8
ns
t
DLDCH
Data Delay after LCLK High
2.5
2.25
ns
t
HLDCH
Data Hold after LCLK High
2.0
2.0
ns
t
LCLKTWL
LCLK Width Low
(t
CK
/4) 1
(t
CK
/4) + 1
(t
CK
/4) 0.75 (t
CK
/4) + 1.5
ns
t
LCLKTWH
LCLK Width High
(t
CK
/4) 1
(t
CK
/4) + 1
(t
CK
/4) 1.5 (t
CK
/4) + 1
ns
t
DLACLK
LCLK Low Delay after LACK High
(t
CK
/4) + 9
(3
*
t
CK
/4) + 16.5
(t
CK
/4) + 9
(3
*
t
CK
/4) + 16.5
ns
NOTE
1
LACK will go low with t
DLALC
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver's link buffer is not about to fill.
34
ADSP-21060/ADSP-21060L
REV. D
CLKIN
LCLK
LDAT(3:0)
LACK
LCLK 1x
OR
LCLK 2x
CLKIN
LDAT(3:0)
LACK (IN)
LCLK 1x
OR
LCLK 2x
LDAT(3:0)
LACK (OUT)
THE
t
SLACH
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
CLKIN
TRANSMIT
t
DLDCH
t
HLDCH
t
DLCLK
t
LCLKTWH
t
LCLKTWL
t
SLACH
t
HLACH
t
DLACLK
t
SLDCL
t
HLDCL
t
LCLKRWH
t
DLAHC
t
DLALC
LINK PORT ENABLE OR THREE-STATE TAKES EFFECT 2 CYCLES AFTER A WRITE TO A LINK PORT CONTROL REGISTER.
t
ENDLK
t
TDLK
RECEIVE
LINK PORT ENABLE/THREE-STATE DELAY FROM INSTRUCTION
t
LCLKRWL
t
LCLKIW
CLKIN
t
SLCK
t
HLCK
LINK PORT INTERRUPT SETUP TIME
LCLK
LACK
LAST NIBBLE
TRANSMITTED
FIRST NIBBLE
TRANSMITTED
LCLK INACTIVE
(HIGH)
OUT
IN
Figure 21. Link Ports
ADSP-21060/ADSP-21060L
35
REV. D
Serial Ports
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
External Clock
Timing Requirements:
t
SFSE
TFS/RFS Setup before TCLK/RCLK
1
3.5
3.5
ns
t
HFSE
TFS/RFS Hold after TCLK/RCLK
1, 2
4
4
ns
t
SDRE
Receive Data Setup before RCLK
1
1.5
1.5
ns
t
HDRE
Receive Data Hold after RCLK
1
4
4
ns
t
SCLKW
TCLK/RCLK Width
9.5
9.0
ns
t
SCLK
TCLK/RCLK Period
t
CK
t
CK
ns
Internal Clock
Timing Requirements:
t
SFSI
TFS Setup before TCLK
1
; RFS Setup
before RCLK
1
8
8
ns
t
HFSI
TFS/RFS Hold after TCLK/RCLK
1, 2
1
1
ns
t
SDRI
Receive Data Setup before RCLK
1
3
3
ns
t
HDRI
Receive Data Hold after RCLK
1
3
3
ns
External or Internal Clock
Switching Characteristics:
t
DFSE
RFS Delay after RCLK (Internally
Generated RFS)
3
13
13
ns
t
HOFSE
RFS Hold after RCLK (Internally
Generated RFS)
3
3
3
ns
External Clock
Switching Characteristics:
t
DFSE
TFS Delay after TCLK (Internally
Generated TFS)
3
13
13
ns
t
HOFSE
TFS Hold after TCLK (Internally
Generated TFS)
3
3
3
ns
t
DDTE
Transmit Data Delay after TCLK
3
16
16
ns
t
HODTE
Transmit Data Hold after TCLK
3
5
5
ns
Internal Clock
Switching Characteristics:
t
DFSI
TFS Delay after TCLK (Internally
Generated TFS)
3
4.5
4.5
ns
t
HOFSI
TFS Hold after TCLK (Internally
Generated TFS)
3
1.5
1.5
ns
t
DDTI
Transmit Data Delay after TCLK
3
7.5
7.5
ns
t
HDTI
Transmit Data Hold after TCLK
3
0
0
ns
t
SCLKIW
TCLK/RCLK Width
(t
SCLK
/2) 2
(t
SCLK
/2) + 2
(t
SCLK
/2) 2.5
(t
SCLK
/2) + 2.5
ns
Enable and Three-State
Switching Characteristics:
t
DDTEN
Data Enable from External TCLK
3
3.5
4.0
ns
t
DDTTE
Data Disable from External TCLK
3
10.5
10.5
ns
t
DDTIN
Data Enable from Internal TCLK
3
0
0
ns
t
DDTTI
Data Disable from Internal TCLK
3
3
3
ns
t
DCLK
TCLK/RCLK Delay from CLKIN
22 + 3DT/8
22 + 3DT/8
ns
t
DPTR
SPORT Disable after CLKIN
17
17
ns
Gated SCLK with External TFS
(Mesh Multiprocessing)
4
Timing Requirements:
t
STFSCK
TFS Setup before CLKIN
5
5
ns
t
HTFSCK
TFS Hold after CLKIN
t
CK
/2
t
CK
/2
ns
External Late Frame Sync
Switching Characteristics:
t
DDTLFSE
Data Delay from Late External TFS or
12
12.8
ns
External RFS with MCE = 1, MFD = 0
5
t
DDTENFS
Data Enable from late FS or MCE = 1,
MFD = 0
5
3
3.5
ns
To
determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay & frame sync se
tup
and hold, 2) data delay & data setup and hold, and 3) SCLK width.
36
ADSP-21060/ADSP-21060L
REV. D
NOTES
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
3
Referenced to drive edge.
4
Applies only to gated serial clock mode used for serial port system I/O in mesh multiprocessing systems.
5
MCE = 1, TFS enable and TFS valid follow t
DDTLFSE
and t
DDTENFS
.
DT
DT
t
DDTTE
t
DDTEN
t
DDTTI
t
DDTIN
DRIVE EDGE
DRIVE EDGE
DRIVE
EDGE
DRIVE
EDGE
TCLK / RCLK
TCLK (INT)
TCLK / RCLK
TCLK (EXT)
CLKIN
SPORT ENABLE AND
THREE-STATE
LATENCY
IS TWO CYCLES
t
DPTR
SPORT DISABLE DELAY
FROM INSTRUCTION
t
DCLK
LOW TO HIGH ONLY
TCLK (INT)
RCLK (INT)
TCLK, RCLK
TFS, RFS, DT
CLKIN
TFS (EXT)
t
HTFSCK
t
STFSCK
NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH
EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O FOR
MESH MULTIPROCESSING.
t
SDRI
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
t
HDRI
t
SFSI
t
HFSI
t
DFSE
t
HOFSE
t
SCLKIW
DATA RECEIVE INTERNAL CLOCK
t
SDRE
DATA RECEIVE EXTERNAL CLOCK
RCLK
RFS
DR
DRIVE
EDGE
SAMPLE
EDGE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTI
t
HDTI
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
t
SFSI
t
HFSI
t
SCLKIW
t
DFSI
t
HOFSI
DATA TRANSMIT INTERNAL CLOCK
t
DDTE
t
HDTE
TCLK
TFS
DT
DRIVE
EDGE
SAMPLE
EDGE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DATA TRANSMIT EXTERNAL CLOCK
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
Figure 22. Serial Ports
ADSP-21060/ADSP-21060L
37
REV. D
t
HOFSE/ I
t
SFSE/ I
(SEE NOTE 2)
DRIVE
SAMPLE
DRIVE
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
EXTERNAL RFS with MCE = 1, MFD = 0
1ST BIT
2ND BIT
DT
RCLK
RFS
TCLK
t
HOFSE/ I
t
SFSE/ I
TFS
DT
DRIVE
SAMPLE
DRIVE
t
DDTE/ I
t
DDTENFS
t
DDTLFSE
t
HDTE/ I
LATE EXTERNAL TFS
1ST BIT
2ND BIT
(SEE NOTE 2)
Figure 23. External Late Frame Sync
38
ADSP-21060/ADSP-21060L
REV. D
JTAG Test Access Port and Emulation
ADSP-21060
ADSP-21060L
Parameter
Min
Max
Min
Max
Units
Timing Requirements:
t
TCK
TCK Period
t
CK
t
CK
ns
t
STAP
TDI, TMS Setup before TCK High
5
5
ns
t
HTAP
TDI, TMS Hold after TCK High
6
6
ns
t
SSYS
System Inputs Setup before TCK Low
1
7
7
ns
t
HSYS
System Inputs Hold after TCK Low
1
18
18.5
ns
t
TRSTW
TRST Pulsewidth
4t
CK
4t
CK
ns
Switching Characteristics:
t
DTDO
TDO Delay from TCK Low
13
13
ns
t
DSYS
System Outputs Delay after TCK Low
2
18.5
18.5
ns
NOTES
1
System Inputs = DATA
47-0
, ADDR
31-0
,
RD, WR, ACK, SBTS, SW, HBR, HBG, CS, DMAR1, DMAR2, BR
6-1
, ID
2-0
, RPBA,
IRQ
2-0
, FLAG
3-0
, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK, EBOOT, LBOOT,
BMS, CLKIN, RESET.
2
System Outputs = DATA
47-0
, ADDR
31-0
,
MS
3-0
,
RD, WR, ACK, PAGE, ADRCLK, SW, HBG, REDY, DMAG1, DMAG2, BR
6-1
,
CPA, FLAG
3-0
, TIMEXP, DT0,
DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT
3-0
, LxCLK, LxACK,
BMS.
TCK
t
STAP
t
TCK
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
Figure 24. IEEE 11499.1 JTAG Test Access Port
ADSP-21060/ADSP-21060L
39
REV. D
Table III. External Power Calculations (3.3 V Device)
Pin
# of
%
Type
Pins
Switching
C
f
V
DD
2
= P
EXT
Address
15
50
44.7 pF 10 MHz 10.9 V = 0.037 W
MS0
1
0
44.7 pF 10 MHz 10.9 V = 0.000 W
WR
1
44.7 pF 20 MHz 10.9 V = 0.010 W
Data
32
50
14.7 pF 10 MHz 10.9 V = 0.026 W
ADDRCLK
1
4.7 pF
20 MHz 10.9 V = 0.001 W
P
EXT
= 0.074 W
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
TOTAL
= P
EXT
+ (I
DDIN2
5.0 V )
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by
V is dependent on the capacitive load, C
L
and
the load current, I
L
. This decay time can be approximated by
the following equation:
t
DECAY
=
C
L
V
I
L
The output disable time t
DIS
is the difference between t
MEASURED
and t
DECAY
as shown in Figure 25. The time t
MEASURED
is the
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. t
DECAY
is calculated with test loads C
L
and
I
L
, and with
V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t
ENA
is the interval from when a
reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (Figure 25). If multiple
pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.
OUTPUT DRIVE CURRENTS
Figure 28 shows typical I-V characteristics for the output drivers
of the ADSP-2106x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry and one due to the switching of external output
drivers. Internal power dissipation is dependent on the instruc-
tion execution sequence and the data operands involved. Inter-
nal power dissipation is calculated in the following way:
P
INT
= I
DDIN
V
DD
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
the number of output pins that switch during each cycle (O)
the maximum frequency at which they can switch (f)
their load capacitance (C)
their voltage swing (V
DD
)
and is calculated by:
P
EXT
= O
C V
DD
2
f
The load capacitance should include the processor's package
capacitance (C
IN
). The switching frequency includes driving the
load high and then back low. Address and data pins can drive
high and low at a maximum rate of 1/(2t
CK
). The write strobe
can switch every cycle at a frequency of 1/t
CK
. Select pins switch
at 1/(2t
CK
), but selects can switch on each cycle.
Example:
Estimate P
EXT
with the following assumptions:
A system with one bank of external data memory RAM (32-bit)
Four 128K
8 RAM chips are used, each with a load of 10 pF
External data memory writes occur every other cycle, a rate
of 1/(4t
CK
), with 50% of the pins switching
The instruction cycle rate is 40 MHz (t
CK
= 25 ns).
The P
EXT
equation is calculated for each class of pins that can
drive:
Table II. External Power Calculations (5 V Device)
Pin
# of
%
Type
Pins
Switching
C
f
V
DD
2
= P
EXT
Address
15
50
44.7 pF 10 MHz 25 V = 0.084 W
MS0
1
0
44.7 pF 10 MHz 25 V = 0.000 W
WR
1
44.7 pF 20 MHz 25 V = 0.022 W
Data
32
50
14.7 pF 10 MHz 25 V = 0.059 W
ADDRCLK
1
4.7 pF
20 MHz 25 V = 0.002 W
P
EXT
= 0.167 W
40
ADSP-21060/ADSP-21060L
REV. D
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V
to be the difference between the ADSP-2106x's output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L
is the total bus capacitance (per
data line), and I
L
is the total leakage or three-state current (per
data line). The hold time will be t
DECAY
plus the minimum
disable time (i.e., t
DATRWH
for the write cycle).
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
V
V
OL (MEASURED)
+ V
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
V
OH (MEASURED)
V
OL (MEASURED)
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE TO BE
APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
ENA
t
DECAY
Figure 25. Output Enable/Disable
+1.5V
50pF
TO
OUTPUT
PIN
I
OL
I
OH
Figure 26. Equivalent Device Loading for AC Measure-
ments (Includes All Fixtures)
1.5V
1.5V
INPUT OR
OUTPUT
Figure 27. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see Figure 26). The delay and hold specifica-
tions given should be derated by a factor of 1.5 ns/50 pF for
loads other than the nominal value of 50 pF. Figures 2930,
3334 show how output rise time varies with capacitance. Fig-
ures 31, 35 show graphically how output delays and holds vary
with load capacitance. (Note that this graph or derating does
not apply to output disable delays; see the previous section
Output Disable Time under Test Conditions.) The graphs of
Figures 29, 30 and 31 may not be linear outside the ranges
shown.
ADSP-21060/ADSP-21060L
41
REV. D
SOURCE VOLTAGE V
100
75
150
0
5.25
SOURCE CURRENT
mA
0.75
1.50
2.25
3.00
3.75
4.50
75
50
100
125
25
25
50
0
175
200
4.75V, +85
C
5.0V, +25
C
5.25V, 40
C
4.75V, +85
C
5.0V, +25
C
5.25V, 40 C
Figure 28. ADSP-2106x Typical Drive Currents (V
DD
= 5 V)
LOAD CAPACITANCE pF
16.0
8.0
0
0
200
20
40
60
80
100
120
140
160
180
14.0
12.0
4.0
2.0
10.0
6.0
RISE AND FALL TIMES
ns
(0.5V
4.5V, 10%
90%)
Y = 0.005X + 3.7
Y = 0.0031X + 1.1
FALL TIME
RISE TIME
Figure 29. Typical Output Rise Time (10%90% V
DD
) vs.
Load Capacitance (V
DD
= 5 V)
3.5
0
RISE AND FALL TIMES
ns (0.8V
2.0V)
3.0
2.5
2.0
1.5
1.0
0.5
LOAD CAPACITANCE pF
0
200
20
40
60
80
100
120
140
160
180
FALL TIME
RISE TIME
Y = 0.009X + 1.1
Y = 0.005X + 0.6
Figure 30. Typical Output Rise Time (0.8 V2.0 V) vs.
Load Capacitance (V
DD
= 5 V)
LOAD CAPACITANCE pF
OUTPUT DELAY OR HOLD
ns
5
1
25
200
50
75
100
125
150
175
4
3
2
1
NOMINAL
Y = 0.03X 1.45
Figure 31. Typical Output Delay or Hold vs. Load Capaci-
tance (at Maximum Case Temperature) (V
DD
= 5 V)
SOURCE VOLTAGE V
120
20
80
0
3.5
SOURCE CURRENT
mA
0.5
1
1.5
2
2.5
3
100
0
40
60
60
20
80
40
100
120
3.0V, +85
C
3.3V, +25
C
3.6V, 40
C
3.6V, 40
C
3.3V, +25
C
3.0V, +85 C
V
OH
V
OL
Figure 32. ADSP-2106x Typical Drive Currents (V
DD
= 3.3 V)
LOAD CAPACITANCE pF
0
2
0
20
40
60
80
100
120
Y = 0.0796X + 1.17
Y = 0.0467X + 0.55
RISE TIME
FALL TIME
140
160
180
200
4
6
8
10
12
14
16
18
RISE AND FALL TIMES
ns (10%
90%)
Figure 33. Typical Output Rise Time (10%90% V
DD
) vs.
Load Capacitance (V
DD
= 3.3 V)
42
ADSP-21060/ADSP-21060L
REV. D
LOAD CAPACITANCE pF
0
0
20
40
60
80
100
120
Y = 0.0391X + 0.36
Y = 0.0305X + 0.24
RISE TIME
FALL TIME
140
160
180
200
RISE AND FALL TIMES
ns (0.8V
2.0V)
1
2
3
4
5
6
7
8
9
Figure 34. Typical Output Rise Time (0.8 V2.0 V) vs.
Load Capacitance (V
DD
= 3.3 V)
ENVIRONMENTAL CONDITIONS
Thermal Characteristics
The ADSP-21060KS and ADSP-21060LKS are packaged in a
240-lead thermally enhanced MQFP. The top surface of the
package contains a copper slug from which most of the die heat
is dissipated. The slug is flush with the top surface of the pack-
age. Note that the copper slug is internally connected to GND
through the device substrate. The ADSP-21060KB and ADSP-
21060LKB are plastic ball grid arrays. The
JC
for the PBGA
package is 1.7
C/Q.
The ADSP-2106x is specified for a case temperature (T
CASE
).
To ensure that the T
CASE
data sheet specification is not ex-
ceeded, a heatsink and/or an air flow source may be used. A
heatsink should be attached with a thermal adhesive.
T
CASE
=
T
AMB
+
(PD
CA
)
T
CASE
=
Case temperature (measured on top surface of package)
PD =
Power dissipation in W (this value depends upon the
specific application; a method for calculating PD is
shown under Power Dissipation).
CA,
CA
= Values from table below.
Plastic Quad Flatpack Package
JC
= 0.3 C/W
Airflow
(Linear Ft./Min.)
0
100
200
400
600
CA
(
C/W)
10
9
8
7
6
NOTES
This represents thermal resistance at total power of 5 W.
With air flow, no variance is seen in
CA
with power.
CA
at 0 LFM varies with power: at 2W,
CA
= 14
C/W, at 3W
CA
= 11
C/W.
PBGA Package
JC
= 1.7 C/W
Airflow
(Linear Ft./Min.)
0
200
400
CA
(
C/W)
20.7
15.3
12.9
NOTE
With air flow, no variance is seen in
CA
with power.
LOAD CAPACITANCE pF
OUTPUT DELAY OR HOLD
ns
5
1
25
200
50
75
100
125
150
175
4
3
2
1
NOMINAL
Y = 0.0329X 1.65
Figure 35. Typical Output Delay or Hold vs. Load Capaci-
tance (at Maximum Case Temperature) (V
DD
= 3.3 V)
ADSP-21060/ADSP-21060L
43
REV. D
240-LEAD MQFP PIN CONFIGURATIONS
1
240
60
61
120
121
180
181
TOP VIEW
HEAT
SLUG
GND
THE 240LEAD PACKAGE CONTAINS A COPPER HEAT SLUG FLUSH WITH ITS
TOP SURFACE. THE SLUG IS EITHER CONNECTED TO GROUND OR FLOATING.
Pin
Pin
No.
Name
1
TDI
2
TRST
3
VDD
4
TDO
5
TIMEXP
6
EMU
7
ICSA
8
FLAG3
9
FLAG2
10
FLAG1
11
FLAG0
12
GND
13
ADDR0
14
ADDR1
15
VDD
16
ADDR2
17
ADDR3
18
ADDR4
19
GND
20
ADDR5
21
ADDR6
22
ADDR7
23
VDD
24
ADDR8
25
ADDR9
26
ADDR10
27
GND
28
ADDR11
29
ADDR12
30
ADDR13
31
VDD
32
ADDR14
33
ADDR15
34
GND
35
ADDR16
36
ADDR17
37
ADDR18
38
VDD
39
VDD
40
ADDR19
Pin
Pin
No.
Name
121
DATA41
122
DATA40
123
DATA39
124
VDD
125
DATA38
126
DATA37
127
DATA36
128
GND
129
NC
130
DATA35
131
DATA34
132
DATA33
133
VDD
134
VDD
135
GND
136
DATA32
137
DATA31
138
DATA30
139
GND
140
DATA29
141
DATA28
142
DATA27
143
VDD
144
VDD
145
DATA26
146
DATA25
147
DATA24
148
GND
149
DATA23
150
DATA22
151
DATA21
152
VDD
153
DATA20
154
DATA19
155
DATA18
156
GND
157
DATA17
158
DATA16
159
DATA15
160
VDD
Pin
Pin
No.
Name
81
TCLK0
82
TFS0
83
DR0
84
RCLK0
85
RFS0
86
VDD
87
VDD
88
GND
89
ADRCLK
90
REDY
91
HBG
92
CS
93
RD
94
WR
95
GND
96
VDD
97
GND
98
CLKIN
99
ACK
100
DMAG2
101
DMAG1
102
PAGE
103
VDD
104
BR6
105
BR5
106
BR4
107
BR3
108
BR2
109
BR1
110
GND
111
VDD
112
GND
113
DATA47
114
DATA46
115
DATA45
116
VDD
117
DATA44
118
DATA43
119
DATA42
120
GND
Pin Pin
No. Name
201 L2DAT0
202 L2CLK
203 L2ACK
204 NC
205 VDD
206 L3DAT3
207 L3DAT2
208 L3DAT1
209 L3DAT0
210 L3CLK
211 L3ACK
212 GND
213 L4DAT3
214 L4DAT2
215 L4DAT1
216 L4DAT0
217 L4CLK
218 L4ACK
219 VDD
220 GND
221 VDD
222 L5DAT3
223 L5DAT2
224 L5DAT1
225 L5DAT0
226 L5CLK
227 L5ACK
228 GND
229 ID2
230 ID1
231 ID0
232 LBOOT
233 RPBA
234
RESET
235 EBOOT
236
IRQ2
237
IRQ1
238
IRQ0
239 TCK
240 TMS
Pin
Pin
No.
Name
161
DATA14
162
DATA13
163
DATA12
164
GND
165
DATA11
166
DATA10
167
DATA9
168
VDD
169
DATA8
170
DATA7
171
DATA6
172
GND
173
DATA5
174
DATA4
175
DATA3
176
VDD
177
DATA2
178
DATA1
179
DATA0
180
GND
181
GND
182
L0DAT3
183
L0DAT2
184
L0DAT1
185
L0DAT0
186
L0CLK
187
L0ACK
188
VDD
189
L1DAT3
190
L1DAT2
191
L1DAT1
192
L1DAT0
193
L1CLK
194
L1ACK
195
GND
196
GND
197
VDD
198
L2DAT3
199
L2DAT2
200
L2DAT1
Pin
Pin
No.
Name
41
ADDR20
42
ADDR21
43
GND
44
ADDR22
45
ADDR23
46
ADDR24
47
VDD
48
GND
49
VDD
50
ADDR25
51
ADDR26
52
ADDR27
53
GND
54
MS3
55
MS2
56
MS1
57
MS0
58
SW
59
BMS
60
ADDR28
61
GND
62
VDD
63
VDD
64
ADDR29
65
ADDR30
66
ADDR31
67
GND
68
SBTS
69
DMAR2
70
DMAR1
71
HBR
72
DT1
73
TCLK1
74
TFS1
75
DR1
76
RCLK1
77
RFS1
78
GND
79
CPA
80
DT0
44
ADSP-21060/ADSP-21060L
REV. D
PACKAGE DIMENSIONS
Dimensions shown in inches and (mm).
240-Lead MQFP
240
1
181
180
121
120
61
60
GND
HEAT
SLUG
240-LEAD METRIC MQFP
TOP VIEW (PINS DOWN)
INCHES (MILLIMETERS)
1.372 (34.85)
1.362 (34.60) TYP SQ
1.352 (34.35)
1.264 (32.10)
1.260 (32.00) TYP SQ
1.256 (31.90)
1.161 (29.50) TYP SQ
0.030 (0.75)
0.024 (0.60) TYP
0.020 (0.50)
SEATING
PLANE
0.161 (4.10)
MAX
0.003 (0.08)
MAX
0.010 (0.25)
MIN
0.138 (3.50)
0.134 (3.40) TYP
0.130 (3.30)
0.011 (0.27)
0.009 (0.22) TYP
0.007 (0.17)
LEAD WIDTH
LEAD PITCH
0.01969 (0.50)
TYP
THE THERMALLY ENHANCED MQFP PACKAGE CONTAINS A
COPPER HEAT SLUG FLUSH WITH ITS TOP SURFACE; THE
SLUG IS EITHER CONNECTED TO GROUND OR FLOATING.
THE HEAT SLUG DIAMETER IS 24.1 (0.949) mm.
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08)
0.0032 FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
ADSP-21060/ADSP-21060L
45
REV. D
225-Ball Plastic Ball Grid Array (PBGA) Package Pinout
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
Ball #
Name
A01
BMS
D01
ADDR25
G01
ADDR14
K01
ADDR6
N01
EMU
A02
ADDR30
D02
ADDR26
G02
ADDR15
K02
ADDR5
N02
TDO
A03
DMAR2
D03
MS2
G03
ADDR16
K03
ADDR3
N03
IRQ0
A04
DT1
D04
ADDR29
G04
ADDR19
K04
ADDR0
N04
IRQ1
A05
RCLK1
D05
DMAR1
G05
GND
K05
ICSA
N05
ID2
A06
TCLK0
D06
TFS1
G06
VDD
K06
GND
N06
L5DAT1
A07
RCLK0
D07
CPA
G07
VDD
K07
VDD
N07
L4CLK
A08
ADRCLK
D08
HBG
G08
VDD
K08
VDD
N08
L3CLK
A09
CS
D09
DMAG2
G09
VDD
K09
VDD
N09
L3DAT3
A10
CLKIN
D10
BR5
G10
VDD
K10
GND
N10
L2DAT0
A11
PAGE
D11
BR1
G11
GND
K11
GND
N11
L1ACK
A12
BR3
D12
DATA40
G12
DATA22
K12
DATA8
N12
L1DAT3
A13
DATA47
D13
DATA37
G13
DATA25
K13
DATA11
N13
L0DAT3
A14
DATA44
D14
DATA35
G14
DATA24
K14
DATA13
N14
DATA1
A15
DATA42
D15
DATA34
G15
DATA23
K15
DATA14
N15
DATA3
B01
MS0
E01
ADDR21
H01
ADDR12
L01
ADDR2
P01
TRST
B02
SW
E02
ADDR22
H02
ADDR11
L02
ADDR1
P02
TMS
B03
ADDR31
E03
ADDR24
H03
ADDR13
L03
FLAG0
P03
EBOOT
B04
HBR
E04
ADDR27
H04
ADDR10
L04
FLAG3
P04
ID0
B05
DR1
E05
GND
H05
GND
L05
RPBA
P05
L5CLK
B06
DT0
E06
GND
H06
VDD
L06
GND
P06
L5DAT3
B07
DR0
E07
GND
H07
VDD
L07
GND
P07
L4DAT0
B08
REDY
E08
GND
H08
VDD
L08
GND
P08
L4DAT3
B09
RD
E09
GND
H09
VDD
L09
GND
P09
L3DAT2
B10
ACK
E10
GND
H10
VDD
L10
GND
P10
L2CLK
B11
BR6
E11
NC
H11
GND
L11
NC
P11
L2DAT2
B12
BR2
E12
DATA33
H12
DATA18
L12
DATA4
P12
L1DAT0
B13
DATA45
E13
DATA30
H13
DATA19
L13
DATA7
P13
L0ACK
B14
DATA43
E14
DATA32
H14
DATA21
L14
DATA9
P14
L0DAT1
B15
DATA39
E15
DATA31
H15
DATA20
L15
DATA10
P15
DATA0
C01
MS3
F01
ADDR17
J01
ADDR9
M01
FLAG1
R01
TCK
C02
MS1
F02
ADDR18
J02
ADDR8
M02
FLAG2
R02
IRQ2
C03
ADDR28
F03
ADDR20
J03
ADDR7
M03
TIMEXP
R03
RESET
C04
SBTS
F04
ADDR23
J04
ADDR4
M04
TDI
R04
ID1
C05
TCLK1
F05
GND
J05
GND
M05
LBOOT
R05
L5DAT0
C06
RFS1
F06
GND
J06
VDD
M06
L5ACK
R06
L4ACK
C07
TFS0
F07
VDD
J07
VDD
M07
L5DAT2
R07
L4DAT1
C08
RFS0
F08
VDD
J08
VDD
M08
L4DAT2
R08
L3ACK
C09
WR
F09
VDD
J09
VDD
M09
L3DAT0
R09
L3DAT1
C10
DMAG1
F10
GND
J10
VDD
M10
L2DAT3
R10
L2ACK
C11
BR4
F11
GND
J11
GND
M11
L1DAT1
R11
L2DAT1
C12
DATA46
F12
DATA29
J12
DATA12
M12
L0DAT0
R12
L1CLK
C13
DATA41
F13
DATA26
J13
DATA15
M13
DATA2
R13
L1DAT2
C14
DATA38
F14
DATA28
J14
DATA16
M14
DATA5
R14
L0CLK
C15
DATA36
F15
DATA27
J15
DATA17
M15
DATA6
R15
L0DAT2
46
ADSP-21060/ADSP-21060L
REV. D
225-Plastic Ball Grid Array (PBGA) Package Pinout
Bottom View
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
ADRCLK
BMS
ADDR30
DMAR2
DT1
RCLK1
TCLK0
RCLK0
CS
CLKIN
PAGE
BR3
DATA47
DATA44
DATA42
MS0
SW
ADDR31
HBR
DR1
DT0
DR0
REDY
RD
ACK
BR6
BR2
DATA45
DATA43
DATA39
MS3
MS1
ADDR28
SBTS
TCLK1
RFS1
TFS0
RFS0
WR
DMAG1
BR4
DATA46
DATA41
DATA38
DATA36
ADDR25
ADDR26
MS2
ADDR29
DMAR1
TFS1
CPA
HBG
DMAG2
BR5
BR1
DATA40
DATA37
DATA35
DATA34
ADDR21
ADDR22
ADDR24
ADDR27
GND
GND
GND
GND
GND
GND
NC
DATA33
DATA30
DATA32
DATA31
ADDR17
ADDR18
ADDR20
ADDR23
GND
GND
VDD
VDD
VDD
GND
GND
DATA29
DATA26
DATA28
DATA27
ADDR14
ADDR15
ADDR16
ADDR19
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA22
DATA25
DATA24
DATA23
ADDR12
ADDR11
ADDR13
ADDR10
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA18
DATA19
DATA21
DATA20
ADDR9
ADDR8
ADDR7
ADDR4
GND
VDD
VDD
VDD
VDD
VDD
GND
DATA12
DATA15
DATA16
DATA17
ADDR6
ADDR5
ADDR3
ADDR0
ICSA
GND
VDD
VDD
VDD
GND
GND
DATA8
DATA11
DATA13
DATA14
ADDR2
ADDR1
FLAG0
FLAG3
RPBA
GND
GND
GND
GND
GND
NC
DATA4
DATA7
DATA9
DATA10
FLAG1
FLAG2
TIMEXP
TDI
LBOOT
L5ACK
L5DAT2
L4DAT2
L3DAT0
L2DAT3
L1DAT1
L0DAT0
DATA2
DATA5
DATA6
EMU
TDO
IRQ0
IRQ1
ID2
L5DAT1
L4CLK
L3CLK
L3DAT3
L2DAT0
L1ACK
L1DAT3
L0DAT3
DATA1
DATA3
TRST
TMS
EBOOT
ID0
L5CLK
L5DAT3
L4DAT0
L4DAT3
L3DAT2
L2CLK
L2DAT2
L1DAT0
L0ACK
L0DAT1
DATA0
TCK
IRQ2
RESET
ID1
L5DAT0
L4ACK
L4DAT1
L3ACK
L0DAT2
L0CLK
L1DAT2
L1CLK
L2DAT1
L2ACK
L3DAT1
ADSP-21060/ADSP-21060L
47
REV. D
ORDERING GUIDE
Case
Part
Temperature
Instruction
On-Chip
Operating
Package
Number
Range
Rate
SRAM
Voltage
Options
ADSP-21060KS-133
0
C to +85C
33 MHz
4 Mbit
5 V
MQFP
ADSP-21060KS-160
0
C to +85C
40 MHz
4 Mbit
5 V
MQFP
ADSP-21060KB-160
0
C to +85C
40 MHz
4 Mbit
5 V
PBGA
ADSP-21060LKS-133
0
C to +85C
33 MHz
4 Mbit
3.3 V
MQFP
ADSP-21060LKS-160
0
C to +85C
40 MHz
4 Mbit
3.3 V
MQFP
ADSP-21060LKB-160
0
C to +85C
40 MHz
4 Mbit
3.3 V
PBGA
ADSP-21060LAB-160
40
C to +85C
40 MHz
4 Mbit
3.3 V
PBGA
PACKAGE DIMENSIONS
Dimensions shown in inches and (mm).
225-Plastic Ball Grid Array (PBGA)
1
2
3
4
5
6
7
8
9
10
11
12
14
15
13
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
0.050
(1.27)
BSC
0.700
(17.78)
BSC
0.050 (1.27) BSC
0.700 (17.78) BSC
0.913 (23.20)
0.906 (23.00)
0.898 (22.80)
0.913 (23.20)
0.906 (23.00)
0.898 (22.80)
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
TOP VIEW
0.101 (2.57)
0.091 (2.32)
0.081 (2.06)
DETAIL A
SEATING
PLANE
0.051 (1.30)
0.047 (1.20)
0.043 (1.10)
0.006 (0.15) MAX
0.026 (0.65)
0.024 (0.61)
0.022 (0.57)
DETAIL A
0.035 (0.90)
0.030 (0.75)
0.024 (0.60)
BALL DIAMETER
NOTES
1.THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.012 (0.30)
OF ITS IDEAL POSITION RELATIVE TO THE EDGE OF THE PACKAGE.
2.THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.004 (0.10)
OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
C3165d2.55/00 (rev. D) 00167
PRINTED IN U.S.A.