www.docs.chipfind.ru
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
ADSP-2106x SHARC
DSP Microcomputer Family
ADSP-21062/ADSP-21062L
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
2 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
SUMMARY
High Performance Signal Processor for Communica-
tions, Graphics and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units--
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals--A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
SHARC is a registered trademark of Analog Devices, Inc.
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
IOP
REGISTERS
(
MEMORY MAPPED)
CONTROL,
STATUS &
DATA BUFFERS
I/O PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
ADDR
DATA
DATA
DATA
ADDR
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
BLOCK 0
BLOCK 1
JTAG
TEST &
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
DUAL-PORTED SRAM
EXTERNAL
PORT
DATA BUS
MUX
48
32
24
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
MULTIPLIER
DAG1
8 x 4 x 32
32
48
40/32
CORE PROCESSOR
DMA
CONTROLLER
PROGRAM
SEQUENCER
DAG2
8 x 4 x 24
Figure 1. ADSP-21062/ADSP-21062L Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
2
ADSP-21062/ADSP-21062L
REV. C
DMA Controller
10 DMA Channels for Transfers Between ADSP-21062
Internal Memory and External Memory, External
Peripherals, Host Processor, Serial Ports, or Link
Ports
Background DMA Transfers at 40 MHz, in Parallel with
Full-Speed Processor Execution
Host Processor Interface to 16- and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21062 Internal
Memory
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-21062s Plus Host
Six Link Ports for Point-to-Point Connectivity and Array
Multiprocessing
240 Mbytes/s Transfer Rate Over Parallel Bus
240 Mbytes/s Transfer Rate Over Link Ports
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports with Com-
panding Hardware
Independent Transmit and Receive Functions
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4
ADSP-21062/ADSP-21062L FEATURES . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
TARGET BOARD CONNECTOR FOR EZ-ICE
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RECOMMENDED OPERATING CONDITIONS . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Read--Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Write--Bus Master . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous Read/Write--Bus Master . . . . . . . . . . . . . . 22
Synchronous Read/Write--Bus Slave . . . . . . . . . . . . . . . . 24
Multiprocessor Bus Request and Host Bus Request . . . . . 26
Asynchronous Read/Write--Host to ADSP-21062 . . . . . . 28
Three-State Timing--Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Link Ports: 1
CLK Speed Operation . . . . . . . . . . . . . . 33
Link Ports: 2
CLK Speed Operation . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 39
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 40
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 43
225 Ball Plastic Ball Grid Array (PBGA)
Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44
225 Ball Plastic Ball Grid Array (PBGA)
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PACKAGE DIMENSIONS,
225-Ball PBGA
. . . . . . . . . . . 46
240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 47
PACKAGE DIMENSIONS, 240-Lead Metric MQFP . . . 48
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figures
Figure 1. ADSP-21062/ADSP-21062L Block Diagram . . . . 1
Figure 2. ADSP-21062 System . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Shared Memory Multiprocessing System . . . . . . . . 6
Figure 4. ADSP-21062/ADSP-21062L Memory Map . . . . . 7
Figure 5. Target Board Connector For ADSP-2106x
EZ-ICE Emulator (Jumpers in Place) . . . . . . . . . . . . . . . 11
Figure 6. JTAG Scan Path Connections for Multiple
ADSP-2106x Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. JTAG Clocktree for Multiple ADSP-2106x
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12. Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Memory Read--Bus Master . . . . . . . . . . . . . . . . 20
Figure 14. Memory Write--Bus Master . . . . . . . . . . . . . . . 21
Figure 15. Synchronous Read/Write--Bus Master . . . . . . . 23
Figure 16. Synchronous Read/Write--Bus Slave . . . . . . . . . 25
Figure 17. Multiprocessor Bus Request and Host Bus
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18a. Synchronous REDY Timing . . . . . . . . . . . . . . 28
Figure 18b. Asynchronous Read/Write--Host to
ADSP-21062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19a. Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19b. Three-State Timing (Host Transition Cycle) . . 30
Figure 20. DMA Handshake Timing . . . . . . . . . . . . . . . . . 32
Figure 21. Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. External Late Frame Sync . . . . . . . . . . . . . . . . . 38
Figure 24. IEEE 11499.1 JTAG Test Access Port . . . . . . . 39
Figure 25. Output Enable/Disable . . . . . . . . . . . . . . . . . . . 41
Figure 26. Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 41
Figure 28. ADSP-21062 Typical Drive Currents
(V
DD
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29. Typical Output Rise Time (10%90% V
DD
)
vs. Load Capacitance (V
DD
= 5 V) . . . . . . . . . . . . . . . . . . 42
Figure 30. Typical Output Rise Time (0.8 V2.0 V) vs. Load
Capacitance (V
DD
= 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 31. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (V
DD
= 5 V) . . . . . . . . 42
Figure 32. ADSP-21062 Typical Drive Currents
(V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33. Typical Output Rise Time (10%90% V
DD
)
vs. Load Capacitance (V
DD
= 3.3 V) . . . . . . . . . . . . . . . . 42
Figure 34. Typical Output Rise Time (0.8 V2.0 V) vs. Load
Capacitance (V
DD
= 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 35. Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (V
DD
= 3.3 V) . . . . . . . 43
EZ-ICE is a registered trademark of Analog Devices, Inc.
ADSP-21062/ADSP-21062L
3
REV. C
including a 2 Mbit SRAM memory (4 Mbit on the ADSP-21060),
host processor interface, DMA controller, serial ports and
link port and parallel bus connectivity for glueless DSP
multiprocessing.
Figure 1 shows a block diagram of the ADSP-21062, illustrating
the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Table I. ADSP-21062/ADSP-21062L Benchmarks (@ 40 MHz)
1024-Pt. Complex FFT
0.46 ms
18,221 cycles
(Radix 4, with Digit Reverse)
FIR Filter (per Tap)
25 ns
1 cycle
IIR Filter (per Biquad)
100 ns
4 cycles
Divide (y/x)
150 ns
6 cycles
Inverse Square Root (1/
x)
225 ns
9 cycles
DMA Transfer Rate
240 Mbytes/s
S
GENERAL NOTE
This data sheet represents production released specifications for
the ADSP-21062 (5 V) and ADSP-21062L (3.3 V) processors,
for both 33 MHz and 40 MHz speed grades. The product name
"ADSP-21062" is used throughout this data sheet to represent
all devices, except where expressly noted.
GENERAL DESCRIPTION
The ADSP-21062 SHARC--Super Harvard Architecture
Computer--is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21062
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-21062 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21062 has a 25 ns instruction cycle time and operates
at 40 MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-21062.
The ADSP-21062 SHARC
represents a new standard of inte-
gration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
4
ADSP-21062/ADSP-21062L
REV. C
ADSP-21000 FAMILY CORE ARCHITECTURE
The ADSP-21062 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21062 processors
are code- and function-compatible with the ADSP-21020.
Independent, Parallel Computation Units
The arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier opera-
tions. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
3
4
RESET
JTAG
7
ADSP-2106x
BMS
ADDR
31-0
DATA
47-0
CONTROL
ADDRESS
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
ADDR
ACK
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
WE
DATA
DMA DEVICE
(OPTIONAL)
DATA
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
1x CLOCK
LINK
DEVICES
(6 MAXIMUM)
(OPTIONAL)
SERIAL
DEVICE
(OPTIONAL)
CS
HBR
HBG
REDY
RD
WR
PAGE
ADRCLK
ACK
SBTS
SW
BR
1-6
DMAR1-2
DMAG1-2
SERIAL
DEVICE
(OPTIONAL)
CLKIN
EBOOT
LBOOT
IRQ
2-0
FLAG
3-0
TIMEXP
LxCLK
LxACK
LxDAT
3-0
TCLK0
RCLK0
TFS0
RSF0
DT0
DR0
TCLK1
RCLK1
TFS1
RFS1
DT1
DR1
RPBA
ID
2-0
MS
3-0
CPA
CS
Figure 2. ADSP-21062 System
Data Register File
A general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two Operands
The ADSP-21062 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction Cache
The ADSP-21062 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective--only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular Buffers
The ADSP-21062's two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21062 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21062 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21062/ADSP-21062L FEATURES
Augmenting the ADSP-21000 family core, the ADSP-21062
adds the following architectural features:
Dual-Ported On-Chip Memory
The ADSP-21062 contains two megabits of on-chip SRAM,
organized as two blocks of 1 Mbits each, which can be config-
ured for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent ac-
cesses by the core processor and I/O processor or DMA control-
ler. The dual-ported memory and separate on-chip buses allow
two data transfers from the core and one from I/O, all in a single
cycle.
On the ADSP-21062, the memory can be configured as a maxi-
mum of 64K words of 32-bit data, 128K words of 16-bit data,
40K words of 48-bit instructions (or 40-bit data), or combina-
tions of different word sizes up to two megabits. All of the
memory can be accessed as 16-bit, 32-bit or 48-bit words.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit floating-
point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
21062's external port.
ADSP-21062/ADSP-21062L
5
REV. C
include interrupt generation upon completion of DMA trans-
fers and DMA chaining for automatic linked DMA transfers.
Serial Ports
The ADSP-21062 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional
-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
Multiprocessing
The ADSP-21062 offers powerful features tailored to multi-
processor DSP systems. The unified address space (see
Figure 4) allows direct interprocessor accesses of each ADSP-
21062's internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems
containing up to six ADSP-21062s and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus lock
allows indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is 240 Mbytes/s
over the link ports or external port. Broadcast writes allow simulta-
neous transmission of data to all ADSP-21062s and can be used
to implement reflective semaphores.
Link Ports
The ADSP-21062 features six 4-bit link ports that provide addi-
tional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits of data per cycle. Link
port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems.
The link ports can operate independently and simultaneously,
with a maximum data throughput of 240 Mbytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Program Booting
The internal memory of the ADSP-21062 can be booted at
system power-up from either an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the
BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.
32-bit and 16-bit host processors can be used for booting.
Off-Chip Memory and Peripherals Interface
The ADSP-21062's external port provides the processor's inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21062's unified
address space. The separate on-chip buses--for PM addresses,
PM data, DM addresses, DM data, I/O addresses and I/O
data--are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21062
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to DRAM
and peripherals with variable access, hold and disable time
requirements.
Host Processor Interface
The ADSP-21062's host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21062's exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21062's external bus
with the host bus request (
HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21062, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA Controller
The ADSP-21062's on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
DMA transfers can occur between the ADSP-21062's internal
memory and either external memory, external peripherals or a
host processor. DMA transfers can also occur between the
ADSP-21062's internal memory and its serial ports or link
ports. DMA transfers between external memory and external
peripheral devices are another option. External bus packing to
16-, 32-, or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-21062--two
via the link ports, four via the serial ports, and four via the
processor's external port (for either host processor, other
ADSP-21062s, memory or I/O transfers). Four additional
link port DMA channels are shared with serial port 1 and the
external port. Programs can be downloaded to the ADSP-
21062 using DMA transfers. Asynchronous off-chip peripher-
als can control two DMA channels using DMA Request/
Grant lines (
DMAR1-2, DMAG1-2 ). Other DMA features
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