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SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC
Processor
ADSP-21262
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high precision signal processing
applications
The ADSP-21262 SHARC DSP is code compatible with all
other SHARC DSPs
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture--two 32-bit IEEE floating-point/32-bit fixed-
point/40-bit extended precision floating-point computa-
tional units, each with a multiplier, ALU, shifter, and
register file
High bandwidth I/O--A parallel port, SPI port, six serial
ports, digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) which includes the parallel data
acquisition port (PDAP), and three programmable timers,
all under software control through the signal routing unit
(SRU)
On-chip memory--2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
Six independent synchronous serial ports provide a variety
of serial communication protocols including TDM and I
2
S
modes
The ADSP-21262 is available with a 200 MHz core instruction
rate. For complete ordering information, see
Ordering
Guide on Page 44
.
Figure 1. Functional Block Diagram
ADDR
DATA
PX REGI STER
6
JTAG TEST & EMULATION
20
3
SERIAL PORTS (6)
I NP UT
DATA PORTS (8)
PARALLEL DATA
ACQUISITION PORT
TIMERS (3)
SI GNAL
ROUTI NG
UNI T
PRECISI ON CLO CK
GENERATORS (2)
DIGITAL AUDIO INTERFACE
3
16
A D D R ES S/
D A TA BU S / GPIO
C ON TR OL/GP IO
PARALLEL
PORT
IOP
RE GISTERS
(MEMORY MAPPED)
CO NTROL,
S TATUS,
DATA BUFFERS
4
SPI PO RT (1)
DMA CO NTROLLER
22 C H A NN E LS
4
GPIO FLAGS/
IRQ/TIMEXP
I/O PROCESSOR
PROCESSING
ELE MENT
(PEY)
PROCESSING
EL EMENT
(PEX)
TIME R
INSTRUCTION
CACHE
32
48-BIT
DAG1
8
4
32
DAG2
8
4
32
32
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
64
64
CORE P ROCESSO R
PROGRAM
S EQUENCER
ADDR
DATA
SRAM
1 MBIT
ROM
2 MBI T
DUAL PORTED MEMORY
BLOCK 0
SRAM
1 MBI T
ROM
2 MBIT
DUAL PORTED MEMORY
BLO CK 1
S
I OD
(32)
IOA
(18)
32
Rev. A
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May 2004
ADSP-21262
KEY FEATURES
At 200 MHz (5 ns) core instruction rate, the ADSP-21262
operates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed or floating point
data
400 MMACS sustained performance at 200 MHz
Super Harvard Architecture--three independent buses for
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit
block 1) for simultaneous access by core processor and
DMA
4M bits on-chip dual-ported mask-programmable ROM
(2M bits in block 0 and 2M bits in block 1)
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single instruction multiple data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution-- Each processing element executes
the same instruction, but operates on different data
Parallelism in buses and computational units allows: Sin-
gle cycle executions (with or without SIMD) of a multiply
operation; an ALU operation; a dual memory read or
write; and an instruction fetch
Transfers between memory and core at up to four 32-bit
floating- or fixed-point words per cycle, sustained
2.4G Bytes/s bandwidth at 200 MHz core instruction rate.
In addition, 900M Bytes/sec is available via DMA
Accelerated FFT butterfly computation through a multiply
with add and subtract instruction
DMA controller supports:
22 zero-overhead DMA channels for transfers between
ADSP-21262 internal memory and serial ports (12), the
input data port (IDP) (8), SPI-compatible port (1), and the
parallel port (1)
32-bit background DMA transfers at core clock speed, in par-
allel with full-speed processor execution
Asynchronous parallel/external port provides:
Access to asynchronous external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
66M Byte per sec transfer rate for 200 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three
programmable timers and a signal routing unit
Serial ports provide:
Six dual data line serial ports that operate at up to 50 Mbits/s
for a 200 MHz core on each data line -- each has a clock,
frame sync, and two data lines that can be configured as
either a receiver or transmitter pair
Left-justified sample pair and I
2
S support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I
2
S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for telephony interfaces such as
H.100/H.110
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the DSP
core configurable as either eight channels of I
2
S or serial
data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port
Supports receive audio channel data in I
2
S, left-justified
sample pair, or right-justified mode
Signal routing unit provides configurable and flexible
connections between all DAI components, six serial ports,
an input data port, two precision clock generators, three
timers, 10 interrupts, six flag inputs, six flag outputs, and
20 SRU I/O pins (DAI_Px)
Serial peripheral interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-slave mode multimaster support
Open drain outputs
Programmable baud rates, clock polarities, and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
ROM based security features:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
JTAG background telemetry for enhanced emulation
features
IEEE 1149.1 JTAG standard test access port and on-chip
emulation
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages
Lead free packages are also available
ADSP-21262
Rev. A
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May 2004
TABLE OF CONTENTS
General Description ..................................................4
ADSP-21262 Family Core Architecture .......................4
SIMD Computational Engine ................................4
Independent, Parallel Computation Units .................5
Data Register File ................................................5
Single-Cycle Fetch of Instruction and Four Operands ..5
Instruction Cache ...............................................5
Data Address Generators With Zero-Overhead
Hardware Circular Buffer Support .......................5
Flexible Instruction Set ........................................6
ADSP-21262 Memory and I/O Interface Features ..........6
Dual-Ported On-Chip Memory ..............................6
DMA Controller .................................................6
Digital Audio Interface (DAI) ................................6
Serial Ports ........................................................6
Serial Peripheral (Compatible) Interface ...................8
Parallel Port ......................................................8
Timers .............................................................8
ROM Based Security ............................................8
Program Booting ................................................8
Phase-Locked Loop ............................................8
Power Supplies ...................................................8
Target Board JTAG Emulator Connector .....................9
Development Tools ................................................9
Designing an Emulator-Compatible DSP
Board (Target) ................................................. 10
Additional Information ......................................... 10
Pin Function Descriptions ........................................ 11
Address Data Pins as FLAGs .................................. 14
Boot Modes ........................................................ 14
Core Instruction Rate to CLKIN Ratio Modes ............. 14
Address Data Modes ............................................. 14
ADSP-21262 Specifications ....................................... 15
Recommended Operating Conditions ....................... 15
Electrical Characteristics ........................................ 15
Absolute Maximum Ratings ................................... 16
ESD Sensitivity .................................................... 16
Timing Specifications ........................................... 16
Power-up Sequencing ........................................ 18
Clock Input ..................................................... 19
Clock Signals ................................................... 19
Reset ............................................................. 20
Interrupts ........................................................20
Core Timer ......................................................20
Timer PWM_OUT Cycle Timing ..........................21
Timer WDTH_CAP Timing ................................21
DAI Pin to Pin Direct Routing .............................22
Precision Clock Generator (Direct Pin Routing) .......23
Flags ..............................................................24
Memory ReadParallel Port .................................25
Memory Write--Parallel Port ..............................27
Serial Ports ......................................................29
Input Data Port (IDP) ........................................32
Parallel Data Acquisition Port (PDAP) ...................33
SPI Interface--Master ........................................34
SPI Interface--Slave ...........................................35
JTAG Test Access Port and Emulation ...................36
Output Drive Currents ..........................................37
Test Conditions ...................................................37
Capacitive Loading ...............................................37
Environmental Conditions .....................................38
Thermal Characteristics .........................................38
136-Ball BGA Pin Configurations ................................39
144-LQFP Pin Configurations ....................................42
Package Dimensions ................................................ 43
Ordering Guide ......................................................44
REVISION HISTORY
4/04Data Sheet Changed from Rev. 0 to Rev. A
Added notes to AD pins ............................................11
Added V
IHCLKIN
and V
ILCLKIN
specifications .....................15
Changed specifications (t
ALERW
, and t
ALEHZ
) ................25-28
Updated 136-BGA package drawing ............................43
Rev. A
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May 2004
ADSP-21262
GENERAL DESCRIPTION
The ADSP-21262 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices Super Har-
vard Architecture. The ADSP-21262 is source code compatible
with the ADSP-21160 and ADSP-21161 DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. Like other SHARC DSPs,
the ADSP-21262 is a 32-bit/40-bit floating-point processor opti-
mized for high precision signal processing applications with its
dual-ported on-chip SRAM, mask-programmable ROM, multi-
ple internal buses to eliminate I/O bottlenecks, and an
innovative Digital Audio Interface (DAI).
As shown in the functional block diagram
on Page 1
, the ADSP-
21262 uses two computational units to deliver a 5 to 10 times
performance increase over the ADSP-2106x on a range of DSP
algorithms. Fabricated in a state-of-the-art, high speed, CMOS
process, the ADSP-21262 DSP achieves an instruction cycle
time of 5 ns at 200 MHz. With its SIMD computational hard-
ware, the ADSP-21262 can perform 1200 MFLOPS running at
200 MHz.
Table 1
shows performance benchmarks for the ADSP-21262.
The ADSP-21262 continues SHARC's industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2 Mbits dual-ported SRAM memory, 4 Mbits
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and Digital Audio Interface (DAI).
The block diagram of the ADSP-21262
on Page 1
illustrates the
following architectural features:
Two processing elements, each containing an ALU, Multi-
plier, Shifter, and Data Register File
Data Address Generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Three Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse Width Measurement, and
External Event Counter Capabilities
On-chip dual-ported SRAM (2M bits)
On-chip dual-ported mask-programmable ROM (4M bits)
JTAG test access port
The block diagram of the ADSP-21262 IOP
on Page 1
, illus-
trates the following architectural features:
8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals
DMA controller
Six full duplex serial ports
SPI compatible interface
Digital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
timers, and a flexible signal routing unit (SRU)
Figure 2 on Page 5
shows one sample configuration of a SPORT
using the precision clock generator to interface with an I
2
S ADC
and an I
2
S DAC with a much lower jitter clock than the serial
port would generate itself. Many other SRU configurations are
possible.
ADSP-21262 FAMILY CORE ARCHITECTURE
The ADSP-21262 is code compatible at the assembly level with
the ADSP-21266, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC DSPs. The ADSP-21262
shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC family of DSPs, as detailed in the
following sections.
SIMD Computational Engine
The ADSP-21262 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Table 1. ADSP-21262 Benchmarks (at 200 MHz)
Benchmark Algorithm
Speed
(at 200 MHz)
1024 Point Complex FFT (Radix 4, with reversal)
46
s
FIR Filter (per tap)
1
1
Assumes two files in multichannel SIMD mode
2.5 ns
IIR Filter (per biquad)
1
10 ns
Matrix Multiply (pipelined)
[33] [31]
[44] [41]
22.5 ns
40 ns
Divide (y/)
15 ns
Inverse Square Root
22.5 ns
ADSP-21262
Rev. A
|
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May 2004
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21262 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
Figure 1 on Page 1
). With the ADSP-21262's separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
The ADSP-21262 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective--only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21262's two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Figure 2. ADSP-21262 System Sample Configuration
DAI
S PORT5
S PORT4
S PORT3
S PORT2
SPO RT1
S PORT0
SCLK0
SD0A
SFS0
SD0B
SRU
DAI_P 1
DAI _P2
DAI _P3
DAI_P 18
DAI_P 19
DAI _P 20
DAC
(OPTI ONAL)
ADC
(OPTI ONAL)
FS
CLK
S DAT
FS
CLK
S DAT
3
CLOCK
FLAG3 -1
2
2
CLKIN
XTAL
CLK_CFG1 -0
BOO TCFG 1-0
ADDR
PARALLEL
PORT
RAM , ROM
BOOT ROM
I/O DE VICE
OE
DATA
W E
RD
W R
CLKO UT
ALE
AD15 -0
LATCH
RESE T
J TAG
6
ADSP-212 62
A
DDR
E
S
S
DAT
A
CO
NT
R
O
L
CS
FLAG0
P CGB
PCG A
CLK
FS
Rev. A
|
Page 6 of 44
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May 2004
ADSP-21262
Fourier transforms. The two DAGs of the ADSP-21262 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21262 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory--all in a single
instruction.
ADSP-21262 MEMORY AND I/O INTERFACE
FEATURES
The ADSP-21262 adds the following architectural features to
the SIMD SHARC family core.
Dual-Ported On-Chip Memory
The ADSP-21262 contains two megabits of internal SRAM and
four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see
ADSP-21262 Memory Map on Page 7
). Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory, in combination with three separate on-chip
buses, allows two data transfers from the core and one from the
I/O processor, in a single cycle.
The ADSP-21262's SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
DMA Controller
The ADSP-21262's on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21262's internal memory and its
serial ports, the SPI-compatible (Serial Peripheral Interface)
port, the IDP (Input Data Port), Parallel Data Acquisition Port
(PDAP), or the parallel port. Twenty-two channels of DMA are
available on the ADSP-21262--one for the SPI interface, 12 via
the serial ports, eight via the Input Data Port, and one via the
processor's parallel port. Programs can be downloaded to the
ADSP-21262 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Digital Audio Interface (DAI)
The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs 20 DAI pins
(DAI_P[20:1]).
Programs make these connections using the Signal Routing
Unit (SRU, shown in
Figure 1
).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This provides easy use of the
DAI associated peripherals for a much wider variety of applica-
tions by using a larger set of algorithms than is possible with
nonconfigurable signal paths.
The DAI also includes six serial ports, two precision clock gen-
erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the DSP core configurable as either eight channels
of I
2
S or serial data, or as seven channels plus a single 20-bit
wide synchronous parallel data acquisition port. Each data
channel has its own DMA channel that is independent from the
ADSP-21262's serial ports.
For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.
Serial Ports
The ADSP-21262 features six synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices
AD183x family of audio codecs, DACs, or ADCs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has its own dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of serial data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/s for a 200 MHz core. Serial port data can be automat-
ically transferred to and from on-chip memory via dedicated
DMA channels. Each of the serial ports can work in conjunction
with another serial port to provide TDM support. One SPORT
provides two transmit signals while the other SPORT provides
the two receive signals. The frame sync and clock are shared.
ADSP-21262
Rev. A
|
Page 7 of 44
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May 2004
Figure 3. ADSP-21262 Memory Map
EXTERNAL MEMORY
SPACE
0x0020 0000
0x3FFF FFFF
ADDRESS
RESERVED
EXTERNAL DMA
ADDRESS SPACE1, 4
0x00FF FFFF
0x0100 0000
0x02FF FFFF
0x0300 0000
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BLOCK 0 ROM (2 Mbit)
0x0006 4000 - 0x0007 7FFF
0x0008 0000
0x0005 8000
0x000B 0000
0x0004 4000 - 0x0005 7FFF
0x000C 0000
0x0008 8000 - 0x000A FFFF
0x0000 0000 - 0x0003 FFFF
0x0004 0000
ADDRESS
0
x
0011 0000 - 0x0015 FFFF
0
x
0016 0000
0x0018 FFFF
0
x
0019 0000 - 0x001D FFFF
IOP REGISTERS
BLOCK 0 SRAM (1Mbit)
INTERNAL MEMORY
SPACE
0
x
0010 0000
1EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE BY THE
CORE. DMA MUST BE USED TO READ OR WRITE TO THIS
MEMORY USING THE SPI OR PARALLEL PORT.
2BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE
(0x000A 0000 - 0x000A AAAA).
3BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE
(0x000E 0000 - 0x000E AAAA).
4USE THE EXTERNAL ADDRESSES LISTED HERE WITH THE
PARALLEL PORT DMA REGISTERS. THE PARALLEL PORT
GENERATES ADDRESS WITHIN THE
RANGE 0x0000 0000-0x00FF FFFF.
0x0006 0000
0
x
0018 0000
0x0010 FFFF
0x000C 7FFF
0x0004 3FFF
0x0006 3FFF
LONG WORD
ADDRESS
SPACE
NORMAL WORD
ADDRESS
SPACE
SHORT WORD
ADDRESS
SPACE
0x0008 7FFF
BLOCK 1 SRAM (1 Mbit)
BLOCK 0 SRAM (1 Mbit)
BLOCK 0 SRAM (1 Mbit)
BLOCK 1 SRAM (1 Mbit)
BLOCK 1 SRAM (1 Mbit)
RESERVED
BLOCK 1 ROM (2 Mbit)
BLOCK 0 ROM (2 Mbit) 2
RESERVED
BLOCK 1 ROM (2 Mbit)3
BLOCK 0 ROM (2 Mbit)
BLOCK 1 ROM (2 Mbit)
0x0007 8000
0x000F 0000
0x0007 FFFF
0x001E 0000
0x0005 FFFF
0x000B FFFF
0x000F FFFF
0x000C 8000 - 0x000E FFFF
0x0017 FFFF
0x001F FFFF
Rev. A
|
Page 8 of 44
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May 2004
ADSP-21262
Serial ports operate in four modes:
Standard DSP serial mode
Multichannel (TDM) mode
I
2
S mode
Left-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received--one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I
2
S protocols (I
2
S is an industry standard interface com-
monly used by audio codecs, ADCs and DACs), with two data
pins, allowing four left-justified Sample Pair or I
2
S channels
(using two stereo devices) per serial port, with a maximum of up
to 24 audio channels. The serial ports permit little-endian or
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the left-justified sample pair and I
2
S
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional
-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) is an industry standard syn-
chronous serial link, enabling the ADSP-21262 SPI-compatible
port to communicate with other SPI-compatible devices. SPI is
an interface consisting of two data pins, one device select pin,
and one clock pin. It is a full-duplex synchronous serial inter-
face, supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21262 SPI compatible peripheral imple-
mentation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21262 SPI
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
Parallel Port
The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15-0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, for a clock rate of 200 MHz, this is equiv-
alent to 66M Bytes/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the
parallel port.
Timers
The ADSP-21262 has a total of four timers: a core timer able to
generate periodic software interrupts and three general-purpose
timers that can generate periodic interrupts and be indepen-
dently set to operate in one of three modes:
Pulse Waveform Generation mode
Pulse Width Count/Capture mode
External Event Watchdog mode
The core timer can be configured to use FLAG3 as a Timer
Expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general-purpose timers independently.
ROM Based Security
The ADSP-21262 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter-
nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
Program Booting
The internal memory of the ADSP-21262 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1-0) pins. Selection of
the boot source is controlled via the SPI as either a master or
slave device, or it can immediately begin executing from ROM.
Phase-Locked Loop
The ADSP-21262 uses an on-chip Phase-Locked Loop (PLL) to
generate the internal clock for the core. On power-up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power Supplies
The ADSP-21262 has separate power supply connections for the
internal (V
DDINT
), external (V
DDEXT
), and analog (A
VDD
/A
VSS
)
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply (A
VDD
) powers the ADSP-21262's
clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
ADSP-21262
Rev. A
|
Page 9 of 44
|
May 2004
the A
VDD
pin. Place the filter as close as possible to the pin. For
an example circuit, see
Figure 4
. To prevent noise coupling, use
a wide trace for the analog ground (A
VSS
) signal and install a
decoupling capacitor as close as possible to the pin. Note that
the A
VSS
and A
VDD
pins specified in
Figure 4
are inputs to the
SHARC and not the analog ground plane on the board.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21262
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor's JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices' SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user's guide.
DEVELOPMENT TOOLS
The ADSP-21262 is supported with a complete set of
CROSSCORE
TM
software and hardware development tools,
including Analog Devices emulators and VisualDSP++
TM
devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21262.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer's development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:
View mixed C/C++ and assembly code (interleaved source
and object information)
Insert breakpoints
Set conditional breakpoints on registers, memory,
and stacks
Trace instruction execution
Perform linear or statistical profiling of program execution
Fill, dump, and graphically plot the contents of memory
Perform source level debugging
Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
Control how the development tools process inputs and
generate outputs
Maintain a one-to-one correspondence with the tool's
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices' technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica-
tions. Download components from the Web and drop them into
Figure 4. Analog Power (A
VDD
) Filter Circuit
V
DDINT
A
VDD
A
VSS
0.01 F
0.1 F
10
Rev. A
|
Page 10 of 44
|
May 2004
ADSP-21262
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with the drag
of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi-
nition File (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD (TARGET)
The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-
circuit emulation is assured by the use of the processor's JTAG
interface--the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys-
tem timing.
To use these emulators, the target board must include a header
that connects the DSP's JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (
www.analog.com
)--
use site search on "EE-68." This document is updated regularly
to keep pace with improvements to emulator support.
ADDITIONAL INFORMATION
This data sheet provides a general overview of the ADSP-21262
architecture and functionality. For detailed information on the
ADSP-2126x family core architecture and instruction set, refer
to the ADSP-2126x DSP Core Manual and the ADSP-21160
SHARC DSP Instruction Set Reference.
ADSP-21262
Rev. A
|
Page 11 of 44
|
May 2004
PIN FUNCTION DESCRIPTIONS
ADSP-21262 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
V
DDEXT
or GND, except for the following:
DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI,
and AD15-0 (NOTE: These pins have pull-up resistors.)
The following symbols appear in the Type column of
Table 2
:
A = Asynchronous, G = Ground, I = Input, O = Output, P =
Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) =
Open Drain, and T = Three-State.
Table 2. Pin Descriptions
Pin
Type
State During and
After Reset
Function
AD15-0
I/O/T
Three-state with
pull-up enabled
Parallel Port Address/Data. The ADSP-21262 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 k
internal pull-up resistor. See
Address
Data Modes on Page 14
for details of the AD pin operation.
For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A23-8; ALE is used in conjunction with an external latch to
retain the values of the A23-8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15-0; ALE is used in conjunction with an external latch to retain the
values of the A15-0. To use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port. When used as an input, the IDP Channel
0 can use these pins for parallel input data.
RD
O
Output only, driven
high
1
Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or
16-bit data from an external memory device. When AD15-0 are flags, this pin remains
deasserted.
WR
O
Output only, driven
high
1
Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or
16-bit data to an external memory device. When AD15-0 are flags, this pin remains
deasserted.
ALE
O
Output only, driven
low
1
Parallel Port Address Latch Enable. ALE is asserted whenever the DSP drives a new
address on the parallel port address pin. On reset, ALE is active high. However, it can
be reconfigured using software to be active low. When AD15-0 are flags, this pin
remains deasserted.
FLAG3-0
I/O/A
Three-state
Flag Pins. Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an
SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When Bit
16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When Bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When Bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When Bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP, which
indicates that the system timer has expired.
Rev. A
|
Page 12 of 44
|
May 2004
ADSP-21262
DAI_P20-1
I/O/T
Three-state with
programmable
pull-up
Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin's output enable. The configuration
registers of these peripherals then determine the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the serial ports, input data port, precision clock gener-
ators, and timer to the DAI_P20-1 pins. These pins have internal 22.5 k
pull-up
resistors which are enabled on reset. These pull-ups can be disabled in the
DAI_PIN_PULLUP register.
SPICLK
I/O
Three-state with
pull-up enabled
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of
baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that
is active during data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK
is used to shift out and shift in the data driven on the MISO and MOSI lines. The data
is always shifted out on one clock edge and sampled on the opposite edge of the
clock. Clock polarity and clock phase relative to data are programmable into the
SPICTL control register and define the transfer format. SPICLK has a 22.5 k
internal
pull-up resistor.
SPIDS
I
Input only
Serial Peripheral Interface Slave Device Select. An active low signal used to select
the DSP as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multimaster mode the DSP's
SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that
an error has occurred, as some other device is also trying to be the master device. If
asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to V
DDEXT
on the master device. For ADSP-21262 to ADSP-
21262 SPI interaction, any of the master ADSP-21262's flag pins can be used to drive
the SPIDS signal on the ADSP-21262 SPI slave device.
MOSI
I/O (O/D)
Three-state with
pull-up enabled
SPI Master Out Slave In. If the ADSP-21262 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21262
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21262 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI
has a 22.5 k
internal pull-up resistor.
MISO
I/O (O/D)
Three-state with
pull-up enabled
SPI Master In Slave Out. If the ADSP-21262 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21262 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-
mitting output data. In an ADSP-21262 SPI interconnection, the data is shifted out
from the MISO output pin of the slave and shifted into the MISO input pin of the
master. MISO has a 22.5 k
internal pull-up resistor. MISO can be configured as O/D
by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI slaves, the DSP's MISO pin may be disabled by setting
(=1) Bit 5 (DMISO) of the SPICTL register.
BOOTCFG1-0
I
Input only
Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins
must be valid before reset is asserted. See
Table 4 on Page 14
for a description of the
boot modes.
Table 2. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
ADSP-21262
Rev. A
|
Page 13 of 44
|
May 2004
CLKIN
I
Input only
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21262 clock input.
It configures the ADSP-21262 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21262 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock
input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted, changed,
or operated below the specified frequency.
XTAL
O
Output only
2
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
CLKCFG1-0
I
Input only
Core/CLKIN Ratio Control. These pins set the start up clock frequency. See
Table 5
on Page 14
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
RSTOUT/CLKOUT
O
Output only
Reset Out/Local Clock Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can be
switched between the PLL output clock and reset out by setting Bit 12 of the PMCTL
register. The default is reset out.
RESET
I/A
Input only
Processor Reset. Resets the ADSP-21262 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
TCK
I
Input only
3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21262.
TMS
I/S
Three-state with
pull-up enabled
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k
internal pull-up resistor.
TDI
I/S
Three-state with
pull-up enabled
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k
internal pull-up resistor.
TDO
O
Three-state
4
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Three-state with
pull-up enabled
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21262. TRST has a
22.5 k
internal pull-up resistor.
EMU
O (O/D)
Three-state with
pull-up enabled
Emulation Status. Must be connected to the ADSP-21262 Analog Devices DSP Tools
product line of JTAG emulators target board connector only. EMU has a 22.5 k
internal pull-up resistor.
V
DDINT
P
Core Power Supply. Nominally +1.2 V dc and supplies the DSP's core processor
(13 pins on the BGA package, 32 pins on the LQFP package).
V
DDEXT
P
I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the
LQFP package).
A
VDD
P
Analog Power Supply. Nominally +1.2 V dc and supplies the DSP's internal PLL
(clock generator). This pin has the same specifications as V
DDINT
, except that added
filtering circuitry is required.
For more information, see Power Supplies on Page 8.
A
VSS
G
Analog Power Supply Return.
GND
G
Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
1
RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.
2
Output only is a three-state driver with its output path always enabled.
3
Input only is a three-state driver with both output paths.
4
Three-state is a three-state driver.
Table 2. Pin Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
Rev. A
|
Page 14 of 44
|
May 2004
ADSP-21262
ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port.
BOOT MODES
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
ADDRESS DATA MODES
The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23-A8 when asserted, fol-
lowed by address bits A7-A0 and data bits D7-D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15-A0 when asserted, followed by data bits D15-D0 when
deasserted.
Table 3. AD[15:0] to Flag Pin Mapping
AD Pin
Flag Pin
AD0
FLAG8
AD1
FLAG9
AD2
FLAG10
AD3
FLAG11
AD4
FLAG12
AD5
FLAG13
AD6
FLAG14
AD7
FLAG15
AD8
FLAG0
AD9
FLAG1
AD10
FLAG2
AD11
FLAG3
AD12
FLAG4
AD13
FLAG5
AD14
FLAG6
AD15
FLAG7
Table 4. Boot Mode Selection
BOOTCFG1-0
Booting Mode
00
SPI Slave Boot
01
SPI Master Boot
10
Parallel Port boot via EPROM
11
Internal Boot Mode (ROM code only)
Table 5. Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1-0
Core to CLKIN Ratio
00
3:1
01
16:1
10
8:1
11
Reserved
Table 6. Address/Data Mode Selection
EP Data
Mode
ALE
AD7-0
Function
AD15-8
Function
8-bit
Asserted
A15-8
A23-16
8-bit
Deasserted
D7-0
A7-0
16-bit
Asserted
A7-0
A15-8
16-bit
Deasserted
D7-0
D15-8
ADSP-21262
Rev. A
|
Page 15 of 44
|
May 2004
ADSP-21262 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Parameter
1
1
Specifications subject to change without notice.
K Grade
Min
Max
Unit
V
DDINT
Internal (Core) Supply Voltage
1.14
1.26
V
A
VDD
Analog (PLL) Supply Voltage
1.14
1.26
V
V
DDEXT
External (I/O) Supply Voltage
3.13
3.47
V
V
IH
High Level Input Voltage
2
, @ V
DDEXT
= max
2
Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
2.0
V
DDEXT
+ 0.5
V
V
IL
Low Level Input Voltage
2
@ V
DDEXT
= min
0.5
+0.8
V
V
IH_CLKIN
High Level Input Voltage
3
, @ V
DDEXT
= max
3
Applies to input pin CLKIN.
1.74
V
DDEXT
+ 0.5
V
V
IL_CLKIN
Low Level Input Voltage, @ V
DDEXT
= min
0.5
+1.28
V
T
AMB
Ambient Operating Temperature
4,
5
4
See
Thermal Characteristics on Page 38
for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. 216) for further information.
0
+70
C
Parameter
1
Test Conditions
Min
Max
Unit
V
OH
High Level Output Voltage
2
@ V
DDEXT
= min, I
OH
= 1.0 mA
3
2.4
V
V
OL
Low Level Output Voltage
2
@ V
DDEXT
= min, I
OL
= 1.0 mA
3
0.4
V
I
IH
High Level Input Current
4, 5
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
10
A
I
IL
Low Level Input Current
4
@ V
DDEXT
= max, V
IN
= 0 V
10
A
I
ILPU
Low Level Input Current Pull-Up
5
@ V
DDEXT
= max, V
IN
= 0 V
200
A
I
OZH
Three-State Leakage Current
6,
7,
8
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
10
A
I
OZL
Three-State Leakage Current
6
@ V
DDEXT
= max, V
IN
= 0 V
10
A
I
OZLPU
Three-State Leakage Current Pull-Up
7
@ V
DDEXT
= max, V
IN
= 0 V
200
A
I
DD-INTYP
Supply Current (Internal)
9, 10, 11
t
CCLK
= 5.0 ns, V
DDINT
= 1.2 V, T
AMB
= +25
C
500
mA
AI
DD
Supply Current (Analog)
12
A
VDD
= max
10
mA
C
IN
Input Capacitance
13,
14
f
IN
= 1 MHz, T
CASE
= 25C, V
IN
= 1.2 V
4.7
pF
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.
3
See
Output Drive Currents on Page 37
for typical drive current capabilities.
4
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 k
internal pull-ups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3-0.
7
Applies to three-statable pins with 22.5 k
pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI.
8
Applies to open-drain output pins: EMU, MISO, MOSI.
9
Typical internal current data reflects nominal operating conditions.
10
See Engineer-to-Engineer Note (No. 216) for further information.
11
Characterized, but not tested.
12
Characterized, but not tested.
13
Applies to all signal pins.
14
Guaranteed, but not tested.
Rev. A
|
Page 16 of 44
|
May 2004
ADSP-21262
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
TIMING SPECIFICATIONS
The ADSP-21262's internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP's internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The ADSP-21262's internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP's internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (
Table 7
and
Table 8
).
Figure 5
shows Core to CLKIN ratios of 3:1, 8:1, and 16:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2126x SHARC DSP Core Manual.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See
Figure 30 on Page 37
under Test conditions for voltage ref-
erence levels.
Parameter
Rating
Internal (Core) Supply Voltage (V
DDINT
)
1
0.3 V to +1.4 V
Analog (PLL) Supply Voltage (A
VDD
)
1
0.3 V to +1.4 V
External (I/O) Supply Voltage (V
DDEXT
)
1
0.3 V to +3.8 V
Input Voltage0.5 V to V
DDEXT
1
+ 0.5 V
Output Voltage Swing0.5 V to V
DDEXT
1
+ 0.5 V
Load Capacitance
1
200 pF
Storage Temperature Range
1
65
C to +150
C
Junction Temperature under Bias
125
C
1
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21262 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Table 7. ADSP-21262 CLKOUT and CCLK Clock
Generation Operation
Timing
Requirements
Description
Calculation
CLKIN Input
Clock
1/t
CK
CCLK
Core Clock
1/t
CCLK
Table 8. Clock Periods
Timing
Requirements
Description
1
t
CK
CLKIN Clock Period
t
CCLK
(Processor) Core Clock Period
t
SCLK
Serial Port Clock Period = (t
CCLK
) SR
t
SPICLK
SPI Clock Period = (t
CCLK
) SPIR
1
where:
SR = serial port-to-core clock ratio (wide range, determined by
SPORT CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by
SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
ADSP-21262
Rev. A
|
Page 17 of 44
|
May 2004
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timingrequirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
Figure 5. Core Clock and System Clock Relationship to CLKIN
CLKIN
CCLK
(CORE CLOCK)
PLLICLK
XTAL
XTAL
OSC
PLL
3:1, 8:1,
16:1
CLKOUT
CLK-CFG [1:0]
Rev. A
|
Page 18 of 44
|
May 2004
ADSP-21262
Power-Up Sequencing
The timing requirements for DSP startup are given in
Table 9
.
Table 9. Power-Up Sequencing Timing Requirements (DSP Startup)
Parameter
Min
Max
Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
on
0
ns
t
IVDDEVDD
V
DDINT
on Before V
DDEXT
50
200
ms
t
CLKVDD
CLKIN Valid After V
DDINT
/V
DDEXT
valid
1
0
200
ms
t
CLKRST
CLKIN Valid Before RESET Deasserted
10
2
s
t
PLLRST
PLL Control Setup Before RESET Deasserted
20
3
s
Switching Characteristic
t
CORERST
DSP Core Reset Deasserted After RESET Deasserted
4096t
CK
4,
5
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4096 cycle count depends on t
SRST
specification in
Table 11
. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 6. Power-Up Sequencing
C LK IN
R ES E T
t
R S T V D D
R ST OU T*
V DDEX T
V DDINT
t
PL L R S T
t
C L K R S T
t
C L K V D D
t
IV D D E V D D
C LK _ C FG 1 -0
t
C O R E R S T
*M U LTIP LE X ED W ITH C LK O U T
ADSP-21262
Rev. A
|
Page 19 of 44
|
May 2004
Clock Input
Clock Signals
The ADSP-21262 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21262 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
Figure 8
shows
the component connections used for a crystal operating in fun-
damental mode. Note that the clock rate is achieved using a
12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Table 10. Clock Input
Parameter
200 MHz
Unit
Min
Max
Timing Requirements
t
CK
CLKIN Period
15
1
160
2
ns
t
CKL
CLKIN Width Low
6
1
80
2
ns
t
CKH
CLKIN Width High
6
1
80
2
ns
t
CKRF
CLKIN Rise/Fall (0.4 V 2.0 V)
3
ns
t
CCLK
CCLK Period
3
5
10
ns
1
Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
Figure 7. Clock Input
CLKIN
t
CK
t
CKH
t
CKL
Figure 8. 200 MHz Operation with a 12.5 MHz Fundamental Mode
Crystal
CLKIN
XTAL
C1
C2
X1
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
1M
Rev. A
|
Page 20 of 44
|
May 2004
ADSP-21262
Reset
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts. Also applies to DAI_P[20:1] pins
when configured as interrupts.
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 11. Reset
Parameter
Min
Max
Unit
Timing Requirements
t
WRST
RESET Pulse Width Low
1
1
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100
s while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
4t
CK
ns
t
SRST
RESET Setup Before CLKIN Low
8
ns
Figure 9. Reset
CLKIN
RESET
t
WRST
t
SRST
Table 12. Interrupts
Parameter
Min
Max
Unit
Timing Requirement
t
IPW
IRQx Pulse Width
2 t
CCLK
+ 2
ns
Figure 10. Interrupts
DAI_P20-1
(FLAG2-0)
(IRQ2-0)
t
IPW
Table 13. Core Timer
Parameter
Min
Max
Unit
Switching Characteristic
t
WCTIM
CTIMER Pulse Width
4 t
CCLK
1
ns
Figure 11. Core Timer
FLAG3
(CTIMER)
t
WCTIM
ADSP-21262
Rev. A
|
Page 21 of 44
|
May 2004
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer[2:0] in
PWM_OUT (pulse width modulation) mode. Timer signals are
routed to the DAI_P[20:1] pins through the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P[20:1] pins.
Timer WDTH_CAP Timing
The following timing specification applies to Timer[2:0] in
WDTH_CAP (pulse width count and capture) mode. Timer sig-
nals are routed to the DAI_P[20:1] pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P[20:1] pins.
Table 14. Timer[2:0] PWM_OUT Timing
Parameter
Min
Max
Unit
Switching Characteristic
t
PWMO
Timer[2:0] Pulse Width Output
2 t
CCLK
1
2(2
31
1) t
CCLK
ns
Figure 12. Timer[2:0] PWM_OUT Timing
DAI_P[20:1]
(TIMER[2:0])
t
PWMO
Table 15. Timer[2:0] Width Capture Timing
Parameter
Min
Max
Unit
Timing Requirement
t
PWI
Timer[2:0] Pulse Width
2 t
CCLK
2(2
31
1) t
CCLK
ns
Figure 13. Timer[2:0] Width Capture Timing
DAI_P[20:1]
(TIMER[2:0])
t
PWI
Rev. A
|
Page 22 of 44
|
May 2004
ADSP-21262
DAI Pin to Pin Direct Routing
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 16. DAI Pin to Pin Routing
Parameter
Min
Max
Unit
Timing Requirement
t
DPIO
Delay DAI Pin Input Valid to DAI Output Valid
1.5
10
ns
Figure 14. DAI Pin to Pin Direct Routing
DAI_Pn
t
DPIO
DAI_Pm
ADSP-21262
Rev. A
|
Page 23 of 44
|
May 2004
Precision Clock Generator (Direct Pin Routing)
This timing is only valid when the SRU is configured such that
the Precision Clock Generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG's
inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is no timing data available. All timing param-
eters and switching characteristics apply to external DAI pins
(DAI_P07 DAI_P20).
Table 17. Precision Clock Generator (Direct Pin Routing)
Parameter
Min
Max
Unit
Timing Requirements
t
PCGIW
Input Clock Period
20
ns
t
STRIG
PCG Trigger Setup Before Falling Edge of PCG Input Clock
2
ns
t
HTRIG
PCG Trigger Hold After Falling Edge of PCG Input Clock
2
ns
Switching Characteristics
t
DPCGIO
PCG Output Clock and Frame Sync Active Edge Delay After PCG Input
Clock
2.5
10
ns
t
DTRIG
PCG Output Clock and Frame Sync Delay After PCG Trigger
2.5 + 2.5 t
PCGOW
10 + 2.5 t
PCGOW
ns
t
PCGOW
Output Clock Period
40
ns
Figure 15. Precision Clock Generator (Direct Pin Routing)
DAI_Pn
PCG_TRIGx_I
t
STRIG
DAI_Pm
PCG_EXTx_I
(CLKIN)
DAI_Py
PCG_CLKx_O
DAI_Pz
PCG_FSx_O
t
HTRIG
t
DPCGIO
t
DTRIG
t
PCGIW
t
PCGOW
Rev. A
|
Page 24 of 44
|
May 2004
ADSP-21262
Flags
The timing specifications provided below apply to the
FLAG[3:0] and DAI_P[20:1] pins, the parallel port, and the
serial peripheral interface (SPI). See
Table 2 on Page 11
for
more information on flag use.
Table 18. Flags
Parameter
Min
Max
Unit
Timing Requirement
t
FIPW
FLAG[3:0] IN Pulse Width
2 t
CCLK
+ 3
ns
Switching Characteristic
t
FOPW
FLAG[3:0] OUT Pulse Width
2 t
CCLK
1
ns
Figure 16. Flags
DAI_P[20:1]
(FLAG3-0IN)
(AD[15:0])
DAI_P[20:1]
(FLAG3-0OUT)
(AD[15:0])
t
FOPW
t
FIPW
ADSP-21262
Rev. A
|
Page 25 of 44
|
May 2004
Memory Read--Parallel Port
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) when the
ADSP-21262 is accessing external memory space.
Table 19. 8-Bit Memory Read Cycle
Parameter
Min
Max
Unit
Timing Requirements
t
DRS
Address/Data [7:0] Setup Before RD High
3.3
ns
t
DRH
Address/Data [7:0] Hold After RD High
0
ns
t
DAD
Address [15:8] to Data Valid
D + 0.5 t
CCLK
3.5
ns
Switching Characteristics
t
ALEW
ALE Pulse Width
2 t
CCLK
2
ns
t
ALERW
ALE Deasserted to Read/Write Asserted
1 t
CCLK
0.5
ns
t
ADAS
Address/Data [15:0] Setup Before ALE Deasserted
1
2.5 t
CCLK
2.0
ns
t
ADAH
Address/Data [15:0] Hold After ALE Deasserted
1
0.5 t
CCLK
0.8
ns
t
ALEHZ
ALE
Deasserted
1
to Address/Data[7:0] In High Z
0.5 t
CCLK
0.8
0.5 t
CCLK
+ 2.0
ns
t
RW
RD Pulse Width
D 2
ns
t
ADRH
Address/Data [15:8] Hold After RD High
0.5 t
CCLK
1 + H
ns
D = (Data Cycle Duration) t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 17. Read Cycle for 8-Bit Memory Timing
VALID DATA
AD[15:8]
VALID ADDRESS
VALID ADDRESS
t
ADAS
VALID ADDRESS
AD[7:0]
t
ALEW
ALE
RD
t
RW
WR
t
ADAH
t
ADRH
t
ALEHZ
t
DRS
t
DRH
t
DAD
t
ALERW
Rev. A
|
Page 26 of 44
|
May 2004
ADSP-21262
Table 20. 16-Bit Memory Read Cycle
Parameter
Min
Max
Unit
Timing Requirements
t
DRS
Address/Data [15:0] Setup Before RD High
3.3
ns
t
DRH
Address/Data [15:0] Hold After RD High
0
ns
Switching Characteristics
ns
t
ALEW
ALE Pulse Width
2 t
CCLK
2
ns
t
ALERW
ALE Deasserted to Read/Write Asserted
1 t
CCLK
0.5
ns
t
ADAS
Address/Data [15:0] Setup Before ALE Deasserted
1
2.5 t
CCLK
2.0
ns
t
ADAH
Address/Data [15:0] Hold After ALE Deasserted
1
0.5 t
CCLK
0.8
ns
t
ALEHZ
ALE Deasserted
1
to Address/Data[15:0] In High Z
0.5 t
CCLK
0.8
0.5t
CCLK
+ 2.0
ns
t
RW
RD Pulse Width
D 2
ns
D = (Data Cycle Duration) t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 18. Read Cycle for 16-Bit Memory Timing
VALID ADDRESS
VALID DATA
t
ADAS
t
ADAH
AD[15:0]
t
ALEHZ
t
DRS
t
DRH
t
ALEW
ALE
RD
t
RW
WR
t
ALERW
ADSP-21262
Rev. A
|
Page 27 of 44
|
May 2004
Memory Write--Parallel Port
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) when the
ADSP-21262 is accessing external memory space.
Table 21. 8-Bit Memory Write Cycle
Parameter
Min
Max
Unit
Switching Characteristics
t
ALEW
ALE Pulse Width
2 t
CCLK
2
ns
t
ALERW
ALE Deasserted to Read/Write Asserted
1 t
CCLK
0.5
ns
t
ADAS
Address/Data [15:0] Setup Before ALE Deasserted
1
2.5 t
CCLK
2.0
ns
t
ADAH
Address/Data [15:0] Hold After ALE Deasserted
1
0.5 t
CCLK
0.8
ns
t
WW
WR Pulse Width
D 2
ns
t
ADWL
Address/Data [15:8] to WR Low
0.5 t
CCLK
1.5
ns
t
ADWH
Address/Data [15:8] Hold After WR High
0.5 t
CCLK
1 + H
ns
t
ALEHZ
ALE Deasserted
1
to Address/Data[15:0] In High Z
0.5 t
CCLK
0.8
0.5t
CCLK
+ 2.0
ns
t
DWS
Address/Data [7:0] Setup Before WR High
D
ns
t
DWH
Address/Data [7:0] Hold After WR High
0.5 t
CCLK
1.5 + H
ns
t
DAWH
Address/Data to WR High
D
ns
D = (Data Cycle Duration) t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 19. Write Cycle for 8-Bit Memory Timing
AD[15:8
]
VALID ADDRESS
VALID ADDRESS
t
ADAS
AD[7:0]
t
ALEW
ALE
RD
t
WW
WR
t
ADAH
t
ADWH
t
ADWL
t
ALEHZ
VALID DATA
t
DWS
t
DWH
VALID ADDRESS
t
DAWH
t
ALERW
Rev. A
|
Page 28 of 44
|
May 2004
ADSP-21262
Table 22. 16-Bit Memory Write Cycle
Parameter
Min
Max
Unit
Switching Characteristics
t
ALEW
ALE Pulse Width
2 t
CCLK
2
ns
t
ALERW
ALE Deasserted to Read/Write Asserted
1 t
CCLK
0.5
ns
t
ADAS
Address/Data [15:0] Setup Before ALE Deasserted
1
2.5 t
CCLK
2.0
ns
t
ADAH
Address/Data [15:0] Hold After ALE Deasserted
1
0.5 t
CCLK
0.8
ns
t
WW
WR Pulse Width
D 2
ns
t
ALEHZ
ALE Deasserted
1
to Address/Data[15:0] In High Z
0.5 t
CCLK
0.8
0.5t
CCLK
+ 2.0
ns
t
DWS
Address/Data [15:0] Setup Before WR High
D
ns
t
DWH
Address/Data [15:0] Hold After WR High
0.5 t
CCLK
1.5 + H
ns
D = (Data Cycle Duration) t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 20. Write Cycle for 16-Bit Memory Timing
VALID ADDRESS
VALID DATA
t
ADAS
AD[15:0]
t
ALEW
ALE
WR
t
WW
RD
t
ADAH
t
DWH
t
DWS
t
ALEHZ
t
ALERW
ADSP-21262
Rev. A
|
Page 29 of 44
|
May 2004
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P[20:1] pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P[20:1] pins.
Table 23. Serial Ports--External Clock
Parameter
Min
Max
Unit
Timing Requirements
t
SFSE
FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
2.5
ns
t
HFSE
FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)
1
2.5
ns
t
SDRE
Receive Data Setup Before Receive SCLK
1
2.5
ns
t
HDRE
Receive Data Hold After SCLK
1
2.5
ns
t
SCLKW
SCLK Width
7
ns
t
SCLK
SCLK Period
20
ns
Switching Characteristics
t
DFSE
FS Delay After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)
2
7
ns
t
HOFSE
FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode)2
2
ns
t
DDTE
Transmit Data Delay After Transmit SCLK
2
7
ns
t
HDTE
Transmit Data Hold After Transmit SCLK
2
2
ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 24. Serial Ports--Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
t
SFSI
FS Setup Before SCLK (Externally Generated FS in Either Transmit or
Receive Mode)
1
6
ns
t
HFSI
FS Hold After SCLK (Externally Generated FS in Either Transmit or Receive
Mode)
1
1.5
ns
t
SDRI
Receive Data Setup Before SCLK
1
6
ns
t
HDRI
Receive Data Hold After SCLK
1
1.5
ns
Switching Characteristics
t
DFSI
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
2
3
ns
t
HOFSI
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
2
1.0
ns
t
DFSI
FS Delay After SCLK (Internally Generated FS in Receive or Mode)
2
3
ns
t
HOFSI
FS Hold After SCLK (Internally Generated FS in Receive Mode)
2
1.0
ns
t
DDTI
Transmit Data Delay After SCLK
2
3
ns
t
HDTI
Transmit Data Hold After SCLK
2
1.0
ns
t
SCLKIW
Transmit or Receive SCLK Width
0.5t
SCLK
2
0.5t
SCLK
+ 2
ns
1
Referenced to the sample edge.
2
Referenced to drive edge.
Rev. A
|
Page 30 of 44
|
May 2004
ADSP-21262
Table 25. Serial Ports--Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
t
DDTEN
Data Enable from External Transmit SCLK
1
2
ns
t
DDTTE
Data Disable from External Transmit SCLK
1
7
ns
t
DDTIN
Data Enable from Internal Transmit SCLK
1
1
ns
1
Referenced to drive edge.
Table 26. Serial Ports--External Late Frame Sync
Parameter
Min
Max
Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External Transmit FS or External Receive FS with
MCE = 1, MFD = 0
1
7
ns
t
DDTENFS
Data Enable for MCE = 1, MFD = 0
1
0.5
ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
Figure 21. External Late Frame Sync
1
1
This figure reflects changes made to support left-justified sample pair mode.
DRIVE
SAMPLE
DRIVE
DIA_P[20:0]
(SCLK)
DIA_P[20:0]
(FS)
DIA_P[20:0]
(DATA CHANNEL A/B)
DRIVE
SAMPLE
DRIVE
LATE EXTERNAL TRANSMIT FS
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
1ST BIT
2ND BIT
DIA_P[20:0]
(SCLK)
DIA_P[20:0]
(FS)
1ST BIT
2ND BIT
t
HFSE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
DIA_P[20:0]
(DATA CHANNEL A/B)
NOTE
SERIAL PORT SIGNALS (SCLK, FS,
DATA CHANNEL A/B
) ARE ROUTED TO THE DAI_P[20:1] PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
t
HFSE/I
ADSP-21262
Rev. A
|
Page 31 of 44
|
May 2004
Figure 22. Serial Ports
DRIVE EDGE
DAI_P[20:1]
SCLK (INT)
DRIVE EDGE
DRIVE EDGE
SCLK
DAI_P[20:1]
SCLK (EXT)
t
DDTTE
t
DDTEN
t
DDTIN
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DRIVE EDGE
SAMPLE EDGE
DATA RECEIVE-- INTERNAL CLOCK
DATA RECEIVE-- EXTERNAL CLOCK
DRIVE EDGE
SAMPLE EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DAI_P[20:1]
(DATA CHANNEL A/B)
t
DDTI
DRIVE EDGE
SAMPLE EDGE
DATA TRANSMIT -- INTERNAL CLOCK
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
HDTI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTE
DRIVE EDGE
SAMPLE EDGE
DATA TRANSMIT -- EXTERNAL CLOCK
t
SFSE
t
HFSE
t
DFSE
t
HOFSE
t
SCLKW
t
HDTE
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DAI_P[20:1]
(DATA CHANNEL A/B)
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
DAI_P[20:1]
(DATA CHANNEL A/B)
Rev. A
|
Page 32 of 44
|
May 2004
ADSP-21262
Input Data Port (IDP)
The timing requirements for the IDP are given in
Table 27
. IDP
Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins
using the SRU. Therefore, the timing specifications provided
below are valid at the DAI_P[20:1] pins.
Table 27. Input Data Port
Parameter
Min
Max
Unit
Timing Requirements
t
SISFS
FS Setup Before SCLK Rising Edge
1
2.5
ns
t
SIHFS
FS Hold After SCLK Rising Edge
1
2.5
ns
t
SISD
SData Setup Before SCLK Rising Edge
1
2.5
ns
t
SIHD
SData Hold After SCLK Rising Edge
1
2.5
ns
t
IDPCLKW
Clock Width
7
ns
t
IDPCLK
Clock Period
20
ns
1
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the Precision Clock Generators (PCG) or SPORTs. PCG's input can be either
CLKIN or any of the DAI pins.
Figure 23. IDP Master Timing
DAI_P[20:1]
(SCLK)
DAI_P[20:1]
(FS)
SAMPLE EDGE
t
SISD
t
SIHD
t
SISFS
t
SIHFS
t
IDPCLKW
DAI_P[20:1]
(SDATA)
ADSP-21262
Rev. A
|
Page 33 of 44
|
May 2004
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 28
. PDAP is the parallel mode operation of Channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2126x Peripherals Manual. Note that the
most significant 16 bits of external PDAP data can be provided
through either the parallel port AD[15:0] or the DAI_P[20:5]
pins. The remaining 4 bits can only be sourced through
DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins
or at the AD[15:0] pins.
Table 28. Parallel Data Acquisition Port (PDAP)
Parameter
Min
Max
Unit
Timing Requirements
t
SPCLKEN
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge
1
2.5
ns
t
HPCLKEN
PDAP_CLKEN Hold After PDAP_CLK Sample Edge
1
2.5
ns
t
PDSD
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge
1
2.5
ns
t
PDHD
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge
1
2.5
ns
t
PDCLKW
Clock Width
7
ns
t
PDCLK
Clock Period
20
ns
Switching Characteristics
t
PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word
2 t
CCLK
ns
t
PDSTRB
PDAP Strobe Pulse Width
1 t
CCLK
1
ns
1
Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.
Figure 24. PDAP Timing
DAI_P[20:1]
(PDAP_CLK)
SAMPLE EDGE
t
PDSD
t
PDHD
t
SPCLKEN
t
HPCLKEN
t
PDCLKW
DATA
DAI_P[20:1]
(PDAP_CLKEN)
t
PDSTRB
t
PDHLDD
DAI_P[20:1]
(PDAP_STROBE)
t
PDCLK
Rev. A
|
Page 34 of 44
|
May 2004
ADSP-21262
SPI Interface--Master
Table 29. SPI Interface Protocol -- Master Switching and Timing Specifications
Parameter
Min
Max
Unit
Switching Characteristics
t
SPICLKM
Serial Clock Cycle
8 t
CCLK
ns
t
SPICHM
Serial Clock High Period
4 t
CCLK
2
ns
t
SPICLM
Serial Clock Low Period
4 t
CCLK
2
ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time)
3
ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
10
ns
t
SDSCIM
FLAG3-0 OUT (SPI device select) Low to First SPICLK Edge
4 t
CCLK
2
ns
t
HDSM
Last SPICLK Edge to FLAG3-0 OUT High
4 t
CCLK
1
ns
t
SPITDM
Sequential Transfer Delay
4 t
CCLK
1
ns
Timing Requirements
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time)
5
ns
t
HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid
2
ns
Figure 25. SPI Master Timing
LSB
VALID
MSB
VALID
t
S S P I D M
t
H S P I D M
t
HDSPIDM
LSB
MSB
t
H S P I D M
t
D D S P I D M
MOSI
(OUTPUT)
MISO
(INPUT)
FLAG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t
S P I C H M
t
S P I C L M
t
S P I C L M
t
S P I C L K M
t
S P I C H M
t
H D S M
t
S P I T D M
t
H D S P I D M
LSB
VALID
LSB
MSB
MSB
VALID
t
H S P I D M
t
D D S P I D M
MOSI
(OUTPUT)
MISO
(INPUT)
t
S S P I D M
CPHASE = 1
CPHASE = 0
t
S D S C I M
t
S S P I D M
ADSP-21262
Rev. A
|
Page 35 of 44
|
May 2004
SPI Interface--Slave
Table 30. SPI Interface Protocol--Slave Switching and Timing Specifications
Parameter
Min
Max
Unit
Switching Characteristics
t
DSOE
SPIDS Assertion to Data Out Active
0
5
ns
t
DSDHI
SPIDS Deassertion to Data High Impedance
0
5
ns
t
DDSPIDS
SPICLK Edge to Data Out Valid (Data Out Delay Time)
7.5
ns
t
HDSPIDS
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
2 t
CCLK
2
ns
t
DSOV
SPIDS Assertion to Data Out Valid (CPHASE = 0)
5 t
CCLK
+ 2
ns
Timing Requirements
t
SPICLKS
Serial Clock Cycle
4 t
CCLK
ns
t
SPICHS
Serial Clock High Period
2 t
CCLK
2
ns
t
SPICLS
Serial Clock Low Period
2 t
CCLK
2
ns
t
SDSCO
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
2 t
CCLK
+ 1
2 t
CCLK
+ 1
ns
ns
t
HDS
Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0
2 t
CCLK
ns
t
SSPIDS
Data Input Valid to SPICLK Edge (Data Input Setup Time)
2
ns
t
HSPIDS
SPICLK Last Sampling Edge to Data Input Not Valid
2
ns
t
SDPPW
SPIDS Deassertion Pulse Width (CPHASE = 0)
2 t
CCLK
ns
Figure 26. SPI Slave Timing
t
H S P I D S
t
D D S P I D S
t
D S D H I
LSB
MSB
MSB VALID
t
D S O E
t
D D S P I D S
t
H D S P I D S
MISO
(OUTPUT)
MOSI
(INPUT)
t
S S P I D S
SPIDS
(INPUT)
SPICLK
(CP = 0)
(INPUT)
SPICLK
(CP = 1)
(INPUT)
t
S D S C O
t
S P IC H S
t
S P I C L S
t
S P I C L S
t
S P I C L K S
t
H D S
t
S P I C H S
t
S S P I D S
t
H S P I D S
t
D S D H I
LSB VALID
MSB
MSB VALID
t
D S O E
t
D D S P I D S
MISO
(OUTPUT)
MOSI
(INPUT)
t
S S P I D S
LSB VALID
LSB
CPHASE = 1
CPHASE = 0
t
S D P P W
t
D S O V
t
H D S P I D S
Rev. A
|
Page 36 of 44
|
May 2004
ADSP-21262
JTAG Test Access Port and Emulation
Table 31. JTAG Test Access Port and Emulation
Parameter
Min
Max Unit
Timing Requirements
t
TCK
TCK Period
20
ns
t
STAP
TDI, TMS Setup Before TCK High
5
ns
t
HTAP
TDI, TMS Hold After TCK High
6
ns
t
SSYS
System Inputs Setup Before TCK High
1
7
ns
t
HSYS
System Inputs Hold After TCK High
1
8
ns
t
TRSTW
TRST Pulse Width
4t
CK
ns
Switching Characteristics
t
DTDO
TDO Delay from TCK Low
7
ns
t
DSYS
System Outputs Delay After TCK Low
2
10
ns
1
System Inputs = AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0
2
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15-0, RD, WR, FLAG3-0, CLKOUT, EMU, ALE.
Figure 27. IEEE 11499.1 JTAG Test Access Port
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
STAP
t
TCK
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS
ADSP-21262
Rev. A
|
Page 37 of 44
|
May 2004
OUTPUT DRIVE CURRENTS
Figure 28
shows typical I-V characteristics for the output driv-
ers of the ADSP-21262. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 10 on Page 19
through
Table 31 on Page 36
. These include
output disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in
Figure 30
. All delays (in nanoseconds) are mea-
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
Figure 29
).
Figure 33
shows graphically
how output delays and holds vary with load capacitance. The
graphs of
Figure 31
,
Figure 32
, and
Figure 33
may not be linear
outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20% 80%, V =
Min) vs. Load Capacitance.
Figure 28. ADSP-21262 Typical Drive
Figure 29. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 30. Voltage Reference Levels for AC Measurements
SWEEP (VDDEXT) VOLTAGE (V)
-20
0
3.5
0.5
1
1.5
2
2.5
3
0
-40
-30
20
40
-10
S
O
U
R
C
E
(
V
D
D
E
X
T
)
C
U
R
R
E
N
T
(
m
A
)
VOL
3.11V, 70 C
3.3V, 25 C
3.47V, 0 C
VOH
30
10
3.11V, 70 C
3.3V, 25 C
3.47V, 0 C
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
1.5V
Figure 31. Typical Output Rise/Fall Time
(20%-80%, V
DDEXT
= Max)
Figure 32. Typical Output Rise/Fall Time
(20%-80%, V
DDEXT
= Min)
LOAD CAPACITANCE (pF)
8.0
0
0
120
40
100
12.0
4.0
2.0
10.0
6.0
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
y = 0.0904x + 1.9426
y = 0.0722x + 1.4042
80
60
20
RISE
FALL
LOAD CAPACITANCE (pF)
12
0
120
20
40
60
80
100
10
8
6
4
R
I
S
E
A
N
D
F
A
L
L
T
I
M
E
S
(
n
s
)
2
0
y = 0.0915x + 2.2207
y = 0.0728x +1.6336
RISE
FALL
Rev. A
|
Page 38 of 44
|
May 2004
ADSP-21262
ENVIRONMENTAL CONDITIONS
The ADSP-21262 processor is rated for performance over the
commercial temperature range, T
AMB
= 0C to 70C.
THERMAL CHARACTERISTICS
Table 32
and
Table 33
airflow measurements comply with
JEDEC standards JESD51-2 and JESD51-6 and the junction-to-
board measurement complies with JESD51-8. The junction-to-
case measurement complies with MIL-STD-883. All measure-
ments use a 2S2P JEDEC test board.
To determine the Junction Temperature of the device while on
the application PCB, use:
where:
T
J
= Junction temperature
C
T
CASE
= Case temperature (
C) measured at the top center of the
package
JT
= Junction-to-Top (of package) characterization parameter
is the Typical value from
Table 32
and
Table 33
.
P
D
= Power dissipation (see EE Note #216)
Values of
JA
are provided for package comparison and PCB
design considerations.
JA
can be used for a first order approxi-
mation of T
J
by the equation:
where:
T
A
= Ambient Temperature
C
Values of
JC
are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of
JB
are provided for package comparison and PCB
design considerations.
Figure 33. Typical Output Delay or Hold vs. Load Capacitance
(at Ambient Temperature)
LOAD CAPACITANCE (pF)
7
0
120
20
40
60
80
100
5
6
4
O
U
T
P
U
T
D
E
L
A
Y
O
R
H
O
L
D
(
n
s
)
3
-4
y = 0.0904x - 2.712
2
0
1
-1
-2
-3
T
J
T
CASE
JT
P
D
(
)
+
=
T
J
T
A
JA
P
D
(
)
+
=
Table 32. Thermal Characteristics for 136-Ball BGA
1
1
The thermal characteristics values provided in this table are modeled values.
Parameter
Condition
Typical
Unit
JA
Airflow = 0 m/s
28.2
C/W
JMA
Airflow = 1 m/s
24.4
C/W
JMA
Airflow = 2 m/s
23.3
C/W
JB
20.1
C/W
JC
7.0
C/W
JT
Airflow = 0 m/s
0.1
C/W
JMT
Airflow = 1 m/s
0.3
C/W
JMT
Airflow = 2 m/s
0.4
C/W
Table 33. Thermal Characteristics for 144-Lead LQFP
1
1
The thermal characteristics values provided in this table are modeled values.
Parameter
Condition
Typical
Unit
JA
Airflow = 0 m/s
32.5
C/W
JMA
Airflow = 1 m/s
28.9
C/W
JMA
Airflow = 2 m/s
27.8
C/W
JC
7.8
C/W
JT
Airflow = 0 m/s
0.5
C/W
JMT
Airflow = 1 m/s
0.8
C/W
JMT
Airflow = 2 m/s
1.0
C/W
ADSP-21262
Rev. A
|
Page 39 of 44
|
May 2004
136-BALL BGA PIN CONFIGURATIONS
The following table and shows the ADSP-21262's pin names
and their default function after reset (in parentheses).
Figure 34
on Page 41
shows the BGA package pin assignments.
Table 34. 136-Ball BGA Pin Assignments
Pin Name
BGA Pin
No.
Pin Name
BGA Pin
No.
Pin Name
BGA Pin
No.
Pin Name
BGA Pin
No.
CLKCFG0
A01
CLKCFG1
B01
BOOTCFG1
C01
V
DDINT
D01
XTAL
A02
GND
B02
BOOTCFG0
C02
GND
D02
TMS
A03
V
DDEXT
B03
GND
C03
GND
D04
TCK
A04
CLKIN
B04
GND
C12
GND
D05
TDI
A05
TRST
B05
GND
C13
GND
D06
CLKOUT
A06
A
VSS
B06
V
DDINT
C14
GND
D09
TDO
A07
A
VDD
B07
GND
D10
EMU
A08
V
DDEXT
B08
GND
D11
MOSI
A09
SPICLK
B09
GND
D13
MISO
A10
RESET
B10
V
DDINT
D14
SPIDS
A11
V
DDINT
B11
V
DDINT
A12
GND
B12
GND
A13
GND
B13
GND
A14
GND
B14
V
DDINT
E01
FLAG1
F01
AD7
G01
AD6
H01
GND
E02
FLAG0
F02
V
DDINT
G02
V
DDEXT
H02
GND
E04
GND
F04
V
DDEXT
G13
DAI_P18 (SD5B)
H13
GND
E05
GND
F05
DAI_P19 (SCLK45)
G14
DAI_P17 (SD5A)
H14
GND
E06
GND
F06
GND
E09
GND
F09
GND
E10
GND
F10
GND
E11
GND
F11
GND
E13
FLAG2
F13
FLAG3
E14
DAI_P20 (SFS45)
F14
Rev. A
|
Page 40 of 44
|
May 2004
ADSP-21262
AD5
J01
AD3
K01
AD2
L01
AD0
M01
AD4
J02
V
DDINT
K02
AD1
L02
WR
M02
GND
J04
GND
K04
GND
L04
GND
M03
GND
J05
GND
K05
GND
L05
GND
M12
GND
J06
GND
K06
GND
L06
DAI_P12 (SD3B)
M13
GND
J09
GND
K09
GND
L09
DAI_P13 (SCLK23)
M14
GND
J10
GND
K10
GND
L10
GND
J11
GND
K11
GND
L11
V
DDINT
J13
GND
K13
GND
L13
DAI_P16 (SD4B)
J14
DAI_P15 (SD4A)
K14
DAI_P14 (SFS23)
L14
AD15
N01
AD14
P01
ALE
N02
AD13
P02
RD
N03
AD12
P03
V
DDINT
N04
AD11
P04
V
DDEXT
N05
AD10
P05
AD8
N06
AD9
P06
V
DDINT
N07
DAI_P1 (SD0A)
P07
DAI_P2 (SD0B)
N08
DAI_P3 (SCLK0)
P08
V
DDEXT
N09
DAI_P5 (SD1A)
P09
DAI_P4 (SFS0)
N10
DAI_P6 (SD1B)
P10
V
DDINT
N11
DAI_P7 (SCLK1)
P11
V
DDINT
N12
DAI_P8 (SFS1)
P12
GND
N13
DAI_P9 (SD2A)
P13
DAI_P10 SD2B)
N14
DAI_P11 (SD3A)
P14
Table 34. 136-Ball BGA Pin Assignments (Continued)
Pin Name
BGA Pin
No.
Pin Name
BGA Pin
No.
Pin Name
BGA Pin
No.
Pin Name
BGA Pin
No.
ADSP-21262
Rev. A
|
Page 41 of 44
|
May 2004
Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary)
A
VSS
V
DDINT
V
DDEXT
I/O SIGNALS
A
VDD
GND*
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE
THERMAL PATHWAYS TO YOUR PRINTED
CIRCUIT BOARD'S GROUND PLANE.
KEY
1
2
3
4
5
6
7
8
9
10
11
12
14 13
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Rev. A
|
Page 42 of 44
|
May 2004
ADSP-21262
144-LEAD LQFP PIN CONFIGURATIONS
The following table shows the ADSP-21262's pin names and
their default function after reset (in parentheses).
Table 35. 144-Lead LQFP Pin Assignments
Pin Name
LQFP
Pin No.
Pin Name
LQFP
Pin No.
Pin Name
LQFP
Pin No.
Pin Name
LQFP
Pin No.
V
DDINT
1
V
DDINT
37
V
DDEXT
73
GND
109
CLKCFG0
2
GND
38
GND
74
V
DDINT
110
CLKCFG1
3
RD
39
V
DDINT
75
GND
111
BOOTCFG0
4
ALE
40
GND
76 V
DDINT
112
BOOTCFG1
5
AD15
41
DAI_P10 (SD2B)
77
GND
113
GND
6
AD14
42
DAI_P11 (SD3A)
78
V
DDINT
114
V
DDEXT
7
AD13
43
DAI_P12 (SD3B)
79
GND
115
GND
8
GND
44 DAI_P13
(SCLK23)
80
V
DDEXT
116
V
DDINT
9
V
DDEXT
45
DAI_P14 (SFS23)
81
GND
117
GND
10
AD12
46
DAI_P15 (SD4A)
82
V
DDINT
118
V
DDINT
11
V
DDINT
47
V
DDINT
83
GND
119
GND
12
GND
48
GND
84
V
DDINT
120
V
DDINT
13
AD11
49
GND
85
RESET
121
GND
14
AD10
50
DAI_P16 (SD4B)
86
SPIDS
122
FLAG0
15
AD9
51
DAI_P17 (SD5A)
87
GND
123
FLAG1
16
AD8
52
DAI_P18 (SD5B)
88
V
DDINT
124
AD7
17
DAI_P1 (SD0A) 53
DAI_P19 (SCLK45)
89
SPICLK
125
GND
18 V
DDINT
54
V
DDINT
90
MISO
126
V
DDINT
19
GND
55 GND
91
MOSI
127
GND
20
DAI_P2 (SD0B) 56
GND
92
GND
128
V
DDEXT
21
DAI_P3 (SCLK0) 57
V
DDEXT
93
V
DDINT
129
GND
22
GND
58
DAI_P20 (SFS45)
94
V
DDEXT
130
V
DDINT
23
V
DDEXT
59
GND
95
A
VDD
131
AD6
24
V
DDINT
60
V
DDINT
96
A
VSS
132
AD5
25
GND
61
FLAG2
97
GND
133
AD4
26
DAI_P4 (SFS0)
62
FLAG3
98
CLKOUT
134
V
DDINT
27
DAI_P5 (SD1A) 63
V
DDINT
99
EMU
135
GND
28
DAI_P6 (SD1B) 64
GND
100
TDO
136
AD3
29
DAI_P7 (SCLK1) 65
V
DDINT
101
TDI
137
AD2
30
V
DDINT
66
GND
102
TRST
138
V
DDEXT
31
GND
67
V
DDINT
103
TCK
139
GND
32
V
DDINT
68
GND
104
TMS
140
AD1
33
GND
69 V
DDINT
105
GND
141
AD0
34
DAI_P8 (SFS1)
70
GND
106
CLKIN
142
WR
35
DAI_P9 (SD2A) 71
V
DDINT
107
XTAL
143
V
DDINT
36
V
DDINT
72
V
DDINT
108
V
DDEXT
144
ADSP-21262
Rev. A
|
Page 43 of 44
|
May 2004
PACKAGE DIMENSIONS
The ADSP-21262 is available in a 136-ball BGA package and a
144-lead LQFP package shown in
Figure 35
and
Figure 36
.
Figure 35. 136-Ball BGA (BC-136)
SEATING
PLANE
1.31
1.21
1.10
0.25
MIN
DETAIL A
0.50
0.46
0.40
(BALL
DIAMETER)
DETAIL A
1.70
MAX
1. DIMENSIONS ARE IN MILIMETERS (MM).
2. THE ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE
TO THE PACKAGE EDGES.
3. THE ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 MM
OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
4. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR
THE BALL DIAMETER.
5. CENTER DIMENSIONS ARE NOMINAL.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
10 9 8 7 6 5 4 3 2 1
13
14
11
12
0.80
BSC
TYP
10.40 BSC SQ
PIN A1 INDICATOR
BOTTOM VIEW
TOP VIEW
12.00 BSC SQ
0.12 MAX (BALL
COPLANARITY)
0.80
BSC
TYP
0.80
BSC
TYP
Rev. A
|
Page 44 of 44
|
May 2004
ADSP-21262
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0444204/04(A)
ORDERING GUIDE
Figure 36. 144-Lead LQFP (ST-144)
Part Number
Ambient Temperature
Range
Instruction
Rate
On-Chip
SRAM
ROM
Operating Voltage Package
1
1
BC indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package.
ADSP-21262SKBC-200
0
C to +70
C
200 MHz
2 Mbit
4 Mbit
1.2 INT/3.3 EXT V
136-Lead BGA
ADSP-21262SKBCZ200
2
2
Z = Pb-free part. For more information about lead-free package offerings, please visit www.analog.com.
0
C to +70
C
200 MHz
2 Mbit
4 Mbit
1.2 INT/3.3 EXT V
136-Lead BGA
ADSP-21262SKSTZ200
2
0
C to +70
C
200 MHz
2 Mbit
4 Mbit
1.2 INT/3.3 EXT V
144-Lead LQFP
SEATING
PLANE
1.60 MAX
0.15
0.05
0.08 MAX (LEAD
COPLANARITY)
1.45
1.40
1.35
0.27
0.22
0.17
TYP
0.50
BSC
TYP
(LEAD
PITCH)
1
3 6
37
73
72
108
144
109
TOP VIEW (PINS DOWN)
22.00 BSC SQ
20.00 BSC SQ
DETAIL A
DETAIL A
PIN 1 INDICATOR
0.75
0.60 TYP
0.45
1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY
WITH JEDEC STANDARD MS-026-BFB.
2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08
OF ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
3. CENTER DIMENSIONS ARE NOMINAL.
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