ADSP-21267 SHARC® Processor Preliminary Data Sheet (REV. PrA)

Preliminary Technical Data

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC

Processor

ADSP-21267

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
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SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for high performance audio processing

Code compatible with all other SHARC DSPs
The ADSP-21267 processes high performance audio while

enabling low system costs

Audio decoders and post processor-algorithms support.

Non-volatile memory can be configured to contain a com-
bination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,
Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES
Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.
See www.analog.com/SHARC for a complete list

Single-Instruction Multiple-Data (SIMD) computational archi-

tecture--two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating point computational
units, each with a multiplier, ALU, shifter, and register file

High bandwidth I/O --a parallel port, an SPI port, four serial

ports, a digital audio interface (DAI) and JTAG test port

DAI incorporates two precision clock generators (PCG), and

an input data port (IDP) that includes a parallel data acqui-
sition port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)

On-chip memory--1M Bit of on-chip SRAM and a dedicated

3M Bits of on-chip mask-programmable ROM

The ADSP-21267 is available with a 150 MHz core instruction

rate. For complete ordering information, see

Ordering

Guide on page 43

Figure 1. FUNCTIONAL BLOCK DIAGRAM

ADDR

DATA

PX REGIS TER

JTAG TES T & EMULATIO N

2 0

SERIAL P ORTS (6)

INPUT

DATA P ORTS (8)

P ARALLEL DATA

ACQUIS ITION PO RT

TI ME RS (3)

SIG NAL

ROUTING

UNIT

PRE CI SION CLOCK

G ENERATO RS (2)

DIGITAL AUDIO INTERFACE

A D D RE SS/

D A TA B U S/ GP IO

CON T R OL/G PIO

PARALLEL

PORT

I OP

REGIS TERS

(MEMO RY MAP PED)

CONTROL,
STATUS, &

DAT A BUFFERS

S PI PORT (1 )

DMA CONTROLLER

2 2 C HA N N ELS

GPIO FLAG S/

IRQ /TIMEXP

I/O PROCESSOR

PRO CE SSI NG

ELEMENT

(PEY )

P ROCE SSI NG

ELEME NT

(PE X)

TIMER

INSTRUCTION

CACHE

32 X 48 -BIT

DAG1

8X4 X3 2

DAG 2

8X 4X3 2

PM ADDRE SS BUS

DM ADDRESS BUS

P M DATA BUS

DM DATA BUS

6 4

CORE P ROCE SSO R

PROG RAM

SEQ UE NCE R

ADDR

DATA

S RAM
0 .5 MBI T

ROM
1 .5 MBIT

DUAL PORTED MEMORY

BLOCK 0

DUAL P ORT ED ME MORY

BLOCK 1

IO D
(32)

IOA
(1 8)

S RAM
0 .5 MBIT

RO M
1 .5 MBI T

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ADSP-21267

PRELIMINARY TECHNICAL DATA

KEY FEATURES

At 150 MHz (6.65 ns) core instruction rate, the ADSP-21267

operates at 900 MFLOPS performance whether operating
on fixed or floating point data
300 MMACS sustained performance at 150 MHz

Code compatibility--At assembly level, uses the same

instruction set as other SHARC DSPs

Super Harvard Architecture--three independent buses for

dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O

1M Bit on-chip dual-ported SRAM (0.5M Bit in block 0 and

0.5M Bit in block 1) for simultaneous access by core proces-
sor and DMA

3M Bits on-chip dual-ported mask-programmable ROM (1.5M

Bits in block 0 and 1.5M Bits in block 1)

Dual Data Address Generators (DAGs) with modulo and bit-

reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:
Two computational processing elements
Concurrent execution-- Each processing element executes

the same instruction, but operates on different data

DMA Controller supports:

18 zero-overhead DMA channels for transfers between

ADSP-21267 internal memory and the four serial ports,
the input data port (IDP) , SPI-compatible port, and the
parallel port

32-bit background DMA transfers at core clock speed, in

parallel with full-speed processor execution

Asynchronous parallel/external port provides:

Access to asynchronous external memory
16 multiplexed address/data lines that can support 24-bit

address external address range with 8-bit data or 16-bit
address external address range with 16-bit data

50 Mbyte per sec transfer rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK

Digital Audio Interface (DAI) includes four serial ports, two

precision clock generators, an input data port/parallel data
acquisition port, three timers and a signal routing unit

Serial Ports provide:

Four dual data line serial ports that operate at 37.5M Bits/s

on each data line --each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair

Left-justified Sample Pair and I

S Support, programmable

direction for up to 16 simultaneous receive or transmit
channels using two I

S compatible stereo devices per

serial port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony inter-
faces such as H.100/H.110

Up to 4 full-duplex TDM streams, each with 128 channels

per frame

Companding selection on a per channel basis in TDM mode

Input Data Port provides an additional input path to the DSP

core configurable as either eight channels of I

S or serial

data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port
Supports receive audio channel data in I

S, Left-justified

sample pair, or right-justified mode

Signal Routing Unit (SRU) provides configurable and flexible

connections between all DAI components, four serial
ports, three timers, 10 interrupts, six flag inputs, six flag
outputs, two precision clock generators, an input data
port/parallel data acquisition port, and 20 SRU I/O pins
(DAI_Px)

Serial Peripheral Interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-Slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
ROM Based Security features:

JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit

access under program control to sensitive code

PLL has a wide variety of software and hardware multi-

plier/divider ratios

JTAG background telemetry for enhanced emulation

features

IEEE 1149.1 JTAG standard test access port and on-chip

emulation

Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages

Also available in lead-free packages

ADSP-21267

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PRELIMINARY TECHNICAL DATA

GENERAL DESCRIPTION

The ADSP-21267 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices' Super Har-
vard Architecture. The ADSP-21267 is source code compatible
with the ADSP-2136x, and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. Like other SHARC DSPs,
the ADSP-21267 is a 32-bit/40-bit floating-point processor opti-
mized for high performance audio applications with its dual-
ported on-chip SRAM, mask-programmable ROM, multiple
internal buses to eliminate I/O bottlenecks, and an innovative
Digital Audio Interface (DAI).

As shown in the Functional Block Diagram on page 1, the
ADSP-21267 uses two computational units to deliver a signifi-
cant performance increase over previous SHARC processors on
a range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the ADSP-21267 DSP achieves an
instruction cycle time of 6.6 ns at 150 MHz. With its SIMD
computational hardware, the ADSP-21267 can perform 900
MFLOPS running at 150 MHz.

Table 1

shows performance benchmarks for the ADSP-21267.

The ADSP-21267 continues SHARC's industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 1M bit dual-ported SRAM memory, 3M bits
dual-ported ROM, an I/O processor that supports 18 DMA
channels, four serial ports, an SPI interface, an external parallel
bus, and Digital Audio Interface (DAI).

The block diagram of the ADSP-21267

on page 1

, illustrates the

following architectural features:

· Two processing elements, each containing an ALU, Multi-

plier, Shifter and Data Register File

· Data Address Generators (DAG1, DAG2)

· Program sequencer with instruction cache

· PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-
cessor cycle

· Three Programmable Interval Timers with PWM Genera-

tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities

· On-Chip dual-ported SRAM (1 Mbit)

· On-Chip dual-ported, mask-programmable ROM

(3 Mbits)

· JTAG test access port

· 8- or 16-bit Parallel port that supports interfaces to off-chip

memory peripherals

· DMA controller

· Four full-duplex serial ports

· SPI-compatible interface

· Digital Audio Interface that includes two precision clock

generators (PCG), an input data port (IDP), four serial
ports, eight serial interfaces, a 20-bit synchronous parallel
input port, 10 interrupts, six flag outputs, six flag inputs,
three timers, and a flexible signal routing unit (SRU)

Figure 2 on page 4

shows one sample configuration of a SPORT

using the precision clock generator to interface with an I

S ADC

and an I

S DAC with a much lower jitter clock than the serial

port would generate itself. Many other SRU configurations are
possible.

ADSP-21267 FAMILY CORE ARCHITECTURE

The ADSP-21267 is code compatible at the assembly level with
the ADSP-2136x, ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-21267 shares architec-
tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.

SIMD Computational Engine

The ADSP-21267 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive audio algorithms.

Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Table 1. ADSP-21267 Benchmarks (at 150 MHz)

Benchmark Algorithm

Speed
(at 150 MHz)

1024 Point Complex FFT (Radix 4, with
reversal)

61.3 µ

FIR Filter (per tap)

Assumes two files in multichannel SIMD mode.

3.3 ns

IIR Filter (per biquad)

13.3 ns

Matrix Multiply (pipelined)
[3x3] x [3x1]
[4x4] x [4x1]

30 ns
53.3 ns

Divide (y/x)

20 ns

Inverse Square Root

30 ns

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ADSP-21267

PRELIMINARY TECHNICAL DATA

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multi-function instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.

Data Register File

A general purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21267 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see the

Figure 1 on page 1

). With the ADSP-21267's separate

program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.

Instruction Cache

TheADSP-21267 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective--only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates and FFT butterfly
processing.

Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support

The ADSP-21267's two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital

Figure 2. ADSP-21267 System Sample Configuration

DAI

SP ORT 3

SP ORT2

S PORT1

SPO RT0

S CLK0

S D0A

S FS0

S D0B

SRU

DAI_P1

DAI_ P2
DAI_ P3

DAI_P 18

DAI _P 19

DAI_ P2 0

DAC

(OP TIONAL)

ADC

(OPTI ONAL)

CLK

S DAT

CLK

S DAT

CLOCK

CLKIN
X TAL

CLK_CFG1-0

BOOTCFG1 -0

FLG3 -1

ADDR

PARALLEL

PORT

RAM , ROM

BOO T ROM
I /O DEVI CE

DATA

CLKOUT

ALE

AD1 5-0

LATCH

RES ET

JTAG

ADSP-21267

ADD

FLG 0

PCGB

P CG A

CLK

F S

ADSP-21267

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PRELIMINARY TECHNICAL DATA

signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21267 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wrap-around, reduce
overhead, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21267 can conditionally execute a multiply, an add, and a sub-
tract in both processing elements while branching and fetching
up to four 32-bit values from memory; all in a single instruction.

ADSP-21267 MEMORY AND I/O INTERFACE
FEATURES

The ADSP-21267 adds the following architectural features to
the SIMD SHARC family core:

Dual-Ported On-Chip Memory

The ADSP-21267 contains one megabit of internal SRAM and
three megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see

ADSP-21267 Memory Map on page 6

). Each

memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory, in combination with three separate on-chip
buses, allow two data transfers from the core and one from the
I/O processor, in a single cycle.

On the ADSP-21267, the SRAM can be configured as a maxi-
mum of 32K words of 32-bit data, 64K words of 16-bit data, 21K
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to one megabit. All of the memory can
be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.

DMA Controller

The ADSP-21267's on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21267's internal memory and its
serial ports, the SPI-compatible (serial peripheral interface)
port, the IDP (input data port/parallel data acquisition port) or

the parallel port. Eighteen channels of DMA are available on the
ADSP-21267 -- one for the SPI interface, eight via the serial
ports, eight via the Input Data Port and one via the processor's
parallel port. Programs can be downloaded to the ADSP-21267
using DMA transfers. Other DMA features include interrupt
generation upon completion of DMA transfers, and DMA
chaining for automatic linked DMA transfers.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs DAI pins
(DAI_P[20:1]).

Programs make these connections using the Signal Routing
Unit (SRU, shown in the block diagram on

page 1

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with non-
configurable signal paths.

The DAI also includes 4 serial ports, 2 precision clock genera-
tors (PCG), an input data port (IDP), 6 flag outputs and 6 flag
inputs, and 3 timers. The IDP provides an additional input path
to the ADSP-21267 core, configurable as either eight channels
of I

S or serial data or as seven channels plus a single 20-bit wide

synchronous parallel data acquisition port Each data channel
has its own DMA channel that is independent from the ADSP-
21267's serial ports.

For complete information on using the DAI, see the ADSP-
2126x SHARC DSP Peripherals Manual.

Serial Ports

The ADSP-21267 features four full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has its own dedicated DMA channel.

Serial ports are enabled via 8 programmable and simultaneous
receive or transmit pins that support up to 16 transmit or 16
receive channels of audio data when all four SPORTS are
enabled, or four full duplex TDM streams of 128 channels per
frame.

The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of 37.5
Mbits/s for a 150 MHz core. Serial port data can be automati-
cally transferred to and from on-chip memory via a dedicated
DMA. Each of the serial ports can work in conjunction with
another serial port to provide TDM support. One SPORT pro-
vides two transmit signals while the other SPORT provides the
two receive signals. The frame sync and clock are shared.

Serial ports operate in four modes:

· Standard DSP serial mode

· Multichannel (TDM) mode

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ADSP-21267

PRELIMINARY TECHNICAL DATA

· I

S mode

· Left-justified sample pair mode

Left-justified Sample Pair Mode is a mode where in each Frame
Sync cycle two samples of data are transmitted/received -- one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.

Each of the serial ports supports the Left-justified Sample Pair
and I

S protocols (I

S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four Left-justified Sample Pair or I

S channels (using two stereo

devices) per serial port, with a maximum of up to 16 audio
channels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to

32 bits. For the Left-justified Sample Pair and I

S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional

-law or A-law companding selection on a per

channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.

Serial Peripheral (Compatible) Interface

Serial Peripheral Interface (SPI) is an industry standard syn-
chronous serial link, enabling the ADSP-21267 SPI-compatible
port to communicate with other SPI-compatible devices. SPI is
an interface consisting of two data pins, one device select pin,
and one clock pin. It is a full-duplex synchronous serial inter-
face, supporting both master and slave modes. The SPI port can
operate in a multi-master environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or

Figure 3. ADSP-21267 Memory Map

RESERVED

0x0004 2000 - 0x0005 7FFF

BLOCK 0 ROM (1.5 mbit)

0x0005 8000 - 0x0002 FFFF

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0.5 Mbit)

0x0004 0000 - 0x0004 1FFF

RESERVED

0x0005 3000 - 0x0005 FFFF

BLOCK 1 SRAM (0.5 Mbit)

0x0006 0000 - 0x0006 1FFF

BLOCK 1 ROM (1.5 mbit)

0x0007 8000 - 0x0007 DFFF

RESERVED

0x0007 E000 - 0x0007 FFFF

RESERVED

0x0006 2000 - 0x0007 7FFF

LONG WORD

ADDRESSING

RESERVED

0x0008 4000 - 0x000A FFFF

BLOCK 0 ROM (1.5 mbit)

0x000B 0000 - 0x000B BFFF

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0.5 Mbit)

0x0008 0000 - 0x0008 3FFF

RESERVED

0x000B C000 - 0x000B FFFF

BLOCK 1 SRAM (0.5 Mbit)

0x000C 0000 - 0x000C 3FFF

BLOCK 1 ROM (1.5 mbit)

0x000F 0000 - 0x000F BFFF

RESERVED

0x000F C000 - 0x000F FFFF

RESERVED

0x000C 4000 - 0x000E FFFF

NORMAL WORD

ADDRESSING

RESERVED

0x0010 8000 - 0x0015 FFFF

BLOCK 0 ROM (1.5 mbit)

0x0016 0000 - 0x0017 7FFF

IOP REGISTERS

0x0000 0000 - 0x0003 FFFF

BLOCK 0 SRAM (0.5 Mbit)

0x0010 0000 - 0x0010 7FFF

RESERVED

0x0017 8FFF - 0x0017 FFFF

BLOCK 1 SRAM (0.5 Mbit)

0x0018 0000 - 0x0018 7FFF

BLOCK 1 ROM (1.5 mbit)

0x001E 0000 - 0x001F 7FFF

RESERVED

0x0018 8000 - 0x001D FFFF

SHORT WORD

ADDRESSING

RESERVED

0x0020 0000 - 0x00FF FFFF

EXTERNAL DMA

ADDRESS SPACE1

0x0100 0000 - 0x02FF FFFF

RESERVED

0x0300 0000 - 0x3FFF FFFF

EXTERNAL MEMORY

SPACE

1EXTERNAL MEMORY IS NOT DIRECTLY ACCESSIBLE
BY THE CORE. DMA MUST BE USED TO READ OR WRITE
TO THIS MEMORY USING THE SPI OR PARALLEL PORT.
2BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE

(0x000A 0000 - 0x000A AAAA).

3BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE

(0x000E 0000 - 0x000E AAA).

INTERNAL MEMORY

SPACE

RESERVED

0x000

ADSP-21267

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PRELIMINARY TECHNICAL DATA

slave device. The ADSP-21267 SPI-compatible peripheral
implementation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21267 SPI-
compatible port uses open drain drivers to support a multi-mas-
ter configuration and to avoid data contention.

Parallel Port

The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15-0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, for a clock rate of 150 MHz, this is equiv-
alent to 50 Mbytes/sec.

DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the parallel
port.

Timers

The ADSP-21267 has a total of four timers: a core timer able to
generate periodic software interrupts and three general purpose
timers that can that can generate periodic interrupts and be
independently set to operate in one of three modes:

· Pulse Waveform Generation mode

· Pulse Width Count/Capture mode

· External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer
Expired output signal, and each general purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general purpose timers independently.

ROM Based Security

The ADSP-21267 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter-
nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.

Program Booting

The internal memory of the ADSP-21267 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1-0) pins. Selection of
the boot source is controlled via the SPI as either a master or
slave device, or it can immediately begin executing from ROM.

Phased Locked Loop

The ADSP-21267 uses an on-chip Phase Locked Loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.

Power Supplies

The ADSP-21267 has separate power supply connections for the
internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

)

power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.

Note that the analog supply (A

VDD

) powers the ADSP-21267's

clock generator PLL. To produce a stable clock, you should pro-
vide an external circuit to filter the power input to the A

VDD

pin.

Place the filter as close as possible to the pin. For an example cir-
cuit, see

Figure 4

. To prevent noise coupling, use a wide trace

for the analog ground (A

VSS

) signal and install a decoupling

capacitor as close as possible to the pin. Note that the A

VSS

and

VDD

pins specified in

Figure 4

are inputs to the SHARC and not

the analog ground plane on the board.

TARGET BOARD JTAG EMULATOR CONNECTOR

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21267 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.

For complete information on Analog Devices' SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user's guide.

DEVELOPMENT TOOLS

The ADSP-21267 is supported by a complete automotive refer-
ence design and development board as well as by a complete
home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and
post processing algorithms that are factory programmed into

Figure 4. Analog Power (A

VDD

) Filter Circuit

DDINT

VDD

VSS

0.01 F

0.1 F

Rev. PrA

Page 8 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

the ROM of the ADSP-21267. SIMD optimized libraries con-
sume less processing resources, which results in more available
processing power for custom proprietary features.

The non-volatile memory of the ADSP-21267 can be configured
to contain a combination of PCM 96 KHz, Dolby Digital, Dolby
Digital EX2, Dolby Pro Logic IIx, DTS 5.1, DTS Matrix 6.1, DTS
Discrete 6.1, DTS Neo:6, and MPEG2 2 channel.

Multiple S/PDIF and analog I/Os are provided to maximize end
system flexibility.

The ADSP-21267 is supported with a complete set of
CROSSCORETM software and hardware development tools,
including Analog Devices emulators and VisualDSP++TM devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21267.

The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.

The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer's development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

· View mixed C/C++ and assembly code (interleaved source

and object information)

· Insert breakpoints

· Set conditional breakpoints on registers, memory,

and stacks

· Trace instruction execution

· Perform linear or statistical profiling of program execution

· Fill, dump, and graphically plot the contents of memory

· Perform source level debugging

· Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

· Control how the development tools process inputs and

generate outputs

· Maintain a one-to-one correspondence with the tool's

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices technology for creating, using, and reusing soft-
ware components (independent modules of substantial
functionality) to quickly and reliably assemble software applica-
tions. Download components from the Web and drop them into
the application. Publish component archives from within Visu-
alDSP++. VCSE supports component implementation in
C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with the drag
of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with existing Linker Definition
File (LDF), allowing the developer to move between the graphi-
cal and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

ADSP-21267

Rev. PrA

Page 9 of 44

January 2004

PRELIMINARY TECHNICAL DATA

DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD (TARGET)

The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-
circuit emulation is assured by the use of the processor's JTAG
interface--the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys-
tem timing.

To use these emulators, the target board must include a header
that connects the DSP's JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices TAG Emulation Technical
Reference on the Analog Devices website (www.analog.com).
Use site search on "EE-68." This document is updated regularly
to keep pace with improvements to emulator support.

ADDITIONAL INFORMATION

This data sheet provides a general overview of the ADSP-21267
architecture and functionality. For detailed information on the
ADSP-2126x Family core architecture and instruction set, refer
to the ADSP-2126x DSP Core Manual and the ADSP-21160
SHARC DSP Instruction Set Reference.

Rev. PrA

Page 10 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

PIN FUNCTION DESCRIPTIONS

ADSP-21267 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to

DDEXT

or GND, except for the following:

· DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI

and AD15-0 (NOTE: These pins have internal pull-up
resistors.)

The following symbols appear in the Type column of

Table 2

A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State.

Table 2. Pin Descriptions

Pin Type

State

During

After Reset

Function

AD15-0

I/O/T

Three-state with
pull-up enabled

Parallel Port Address/Data. The ADSP-21267 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 K

internal pull-up resistor. See

Address

Data Modes on page 13

for details of the AD pin operation:

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the
upper 16 external address bits, A23-8; ALE is used in conjunction with an external
latch to retain the values of the A23-8.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A15-0; ALE is used in conjunction with an external latch to retain the
values of the A15-0.
To use these pins as flags (FLAG15-0) set (=1) bit 20 of the SYSCTL register and
disable the parallel port. See

Table 3 on page 13

for a list of how the AD15-0 pins

map to the flag pins. When used as an input, the IDP Channel0 can use these pins
for parallel input data.

Output only, driven
high

Parallel Port Read Enable. RD is asserted low whenever the DSP reads 8-bit or 16-
bit data from an external memory device. When AD15-0 are flags, this pin remains
deasserted.

Output only, driven
high

Parallel Port Write Enable. WR is asserted low whenever the DSP writes 8-bit or
16-bit data to an external memory device. When AD15-0 are flags, this pin remains
deasserted.

ALE

Output only, driven
low

Parallel Port Address Latch enable. ALE is asserted whenever the DSP drives a
new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD15-0 are flags, this
pin remains deasserted.

FLAG3-0

I/O/A

Three-state

Flag Pins. Each FLAG pin is configured via control bits as either an input or output.
As an input, it can be tested as a condition. As an output, it can be used to signal
external peripherals. These pins can be used as an SPI interface slave select output
during SPI mastering. These pins are also multiplexed with the IRQx and the TIMEXP
signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to
an SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When
bit 16 is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which
indicates that the system timer has expired.

ADSP-21267

Rev. PrA

Page 11 of 44

January 2004

PRELIMINARY TECHNICAL DATA

DAI_P20-1

I/O/T

Three-state with
programmable pull-
up

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral
inputs or outputs connected to the pin and to the pin's output enable. The config-
uration registers of these peripherals then determines the exact behavior of the pin.
Any input or output signal present in the SRU may be routed to any of these pins.
The SRU provides the connection from the Serial ports, Input data port, precision
clock generators and timers to the DAI_P20-1 pins These pins have internal 22.5 K

pull-up resistors which are enabled on reset. These pull-ups can be disabled in the
DAI_PIN_PULLUP register.

SPICLK

I/O

Three-state with
pull-up enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of
baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that
is active during data transfers, only for the length of the transferred word. Slave
devices ignore the serial clock if the slave select input is driven inactive (HIGH).
SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines.
The data is always shifted out on one clock edge and sampled on the opposite edge
of the clock. Clock polarity and clock phase relative to data are programmable into
the SPICTL control register and define the transfer format. SPICLK has a 22.5 K

internal pull-up resistor.

SPIDS

Input only

Serial Peripheral Interface Slave Device Select. An active low signal used to select
the DSP as an SPI slave device. This input signal behaves like a chip select, and is
provided by the master device for the slave devices. In multi-master mode the DSPs
SPIDS signal can be driven by a slave device to signal to the DSP (as SPI master) that
an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multi-master
error. For a single-master, multiple-slave configuration where flag pins are used, this
pin must be tied or pulled high to V

DDEXT

on the master device. For ADSP-21267 to

ADSP-21267 SPI interaction, any of the master ADSP-21267's flag pins can be used
to drive the SPIDS signal on the ADSP-21267 SPI slave device.

MOSI

I/O (O/D)

Three-state with
pull-up enabled

SPI Master Out Slave In. If the ADSP-21267 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21267
is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving
input data. In an ADSP-21267 SPI interconnection, the data is shifted out from the
MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s).
MOSI has a 22.5 K

internal pull-up resistor.

MISO

I/O (O/D)

Three-state with
pull-up enabled

SPI Master In Slave Out. If the ADSP-21267 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21267 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, trans-
mitting output data. In an ADSP-21267 SPI interconnection, the data is shifted out
from the MISO output pin of the slave and shifted into the MISO input pin of the
master. MISO has a 22.5K

internal pull-up resistor. MISO can be configured as O/D

by setting the OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable
broadcast transmission to multiple SPI-slaves, the DSP's MISO pin may be disabled
by setting (=1) bit 5 (DMISO) of the SPICTL register.

BOOTCFG1-0

Input only

Boot Configuration Select. Selects the boot mode for the DSP. The BOOTCFG pins
must be valid before reset is asserted. See

Table 4 on page 13

for a description of

the boot modes.

Table 2. Pin Descriptions (Continued)

Pin Type

State

During

After Reset

Function

Rev. PrA

Page 12 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

CLKIN

Input only

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21267 clock input.
It configures the ADSP-21267 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables
the internal clock generator. Connecting the external clock to CLKIN while leaving
XTAL unconnected configures the ADSP-21267 to use the external clock source
such as an external clock oscillator. The core is clocked either by the PLL output or
this clock input depending on the CLKCFG1-0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.

XTAL

Output only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.

CLKCFG1-0

Input only

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See

Table 5

on page 13

for a description of the clock configuration modes.

Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT/CLKOUT

Output only

Reset Out/Local Clock Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting bit 12 of the
PMCTL register. The default is reset out.

RESET

I/A

Input only

Processor Reset. Resets the ADSP-21267 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.

TCK

Input only

Test Clock (JTAG). Provides a clock for JTAG boundary scan. must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21267.

TMS

I/S

Three-state with
pull-up enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a
22.5 k

internal pull-up resistor.

TDI

I/S

Three-state with
pull-up enabled

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k

internal pull-up resistor.

TDO

Three-state

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A

Three-state with
pull-up enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21267. TRST has
a 22.5 k

internal pull-up resistor.

EMU

O (O/D)

Three-state with
pull-up enabled

Emulation Status. Must be connected to the ADSP-21267 Analog Devices DSP
Tools product line of JTAG emulators target board connector only. EMU has a
22.5 k

internal pullup resistor.

DDINT

Core Power Supply. Nominally +1.2 V dc and supplies the DSP's core processor (13
pins on the BGA package, 32 pins on the LQFP package).

DDEXT

I/O Power Supply. Nominally +3.3 V dc. (6 pins on the BGA package, 10 pins on the
LQFP package).

VDD

Analog Power Supply. Nominally +1.2 V dc and supplies the DSP's internal PLL
(clock generator). This pin has the same specifications as V

DDINT

, except that added

filtering circuitry is required.

For more information, see Power Supplies on page 7.

VSS

Analog Power Supply Return.

GND

Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).

RD, WR, and ALE are continuously driven by the DSP and won't be three-stated.

Output only is a three-state driver with its output path always enabled.

Input only is three-state driver with both output path.

Three-state is three-state driver.

Table 2. Pin Descriptions (Continued)

Pin Type

State

During

After Reset

Function

ADSP-21267

Rev. PrA

Page 13 of 44

January 2004

PRELIMINARY TECHNICAL DATA

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAG15-0) set (=1) bit 20 of the
SYSCTL register and disable the parallel port.

Boot Modes

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

ADDRESS DATA MODES

The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23-A8 when asserted, fol-
lowed by address bits A7-A0 and data bits D7-D0 when

deasserted. For 16-bit data transfers, ALE latches address bits
A15-A0 when asserted, followed by data bits D15-D0 when
deasserted.

Table 3. AD[15:0] to FLAG Pin Mapping

AD Pin

Flag Pin

AD0

FLAG8

AD1

FLAG9

AD2

FLAG10

AD3

FLAG11

AD4

FLAG12

AD5

FLAG13

AD6

FLAG14

AD7

FLAG15

AD8

FLAG0

AD9

FLAG1

AD10

FLAG2

AD11

FLAG3

AD12

FLAG4

AD13

FLAG5

AD14

FLAG6

AD15

FLAG7

Table 4. Boot Mode Selection

BOOTCFG1-0

Booting Mode

SPI Slave Boot

SPI Master Boot

Parallel Port boot via EPROM

Internal Boot Mode (ROM code only)

Table 5. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG1-0

Core to CLKIN Ratio

3:1

16:1

8:1

Reserved

Table 6. Address/ Data Mode Selection

EP Data
Mode

ALE

AD7-0
Function

AD15-8
Function

8-bit

Asserted

A15-8

A23-16

8-bit

Deasserted

D7-0

A7-0

16-bit

Asserted

A7-0

A15-8

16-bit

Deasserted

D7-0

D15-8

Rev. PrA

Page 14 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

ADSP-21267 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

K Grade

Min

Max

Unit

DDINT

Internal (Core) Supply Voltage

1.14

1.26

VDD

Analog (PLL) Supply Voltage

1.14

1.26

DDEXT

External (I/O) Supply Voltage

3.13

3.47

High Level Input Voltage

, @ V

DDEXT

= max

2.0

DDEXT

+0.5

Low Level Input Voltage

@ V

DDEXT

= min

-0.5

0.8

AMB

Ambient Operating Temperature

3 4

+70

Specifications subject to change without notice.

Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKIN, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

See

Thermal Characteristics on page 37

for information on thermal specifications.

See Engineer-to-Engineer Note (No. 216) for further information.

Parameter

Test Conditions

Min

Max

Unit

High Level Output Voltage

@ V

DDEXT

= min, I

= -1.0 mA

2.4

Low Level Output Voltage

@ V

DDEXT

= min, I

= 1.0 mA

0.4

High Level Input Current

4, 5

@ V

DDEXT

= max, V

= V

DDEXT

max

µA

Low Level Input Current

@ V

DDEXT

= max, V

= 0 V

µA

ILPU

Low Level Input Current Pull-Up

@ V

DDEXT

= max, V

= 0 V

200

µA

OZH

Three-State Leakage Current

@ V

DDEXT

= max, V

= V

DDEXT

max

µA

OZL

Three-State Leakage Current

@ V

DDEXT

= max, V

= 0 V

µA

OZLPU

Three-State Leakage Current Pull-Up

@ V

DDEXT

= max, V

= 0 V

200

µA

DD-INTYP

Supply Current (Internal)

9, 10, 11

CCLK

= 5.0 ns, V

DDINT

= 1.2V, T

AMB

= +25

500

Supply Current (Analog)

VDD

= max

Input Capacitance

13,

=1 MHz, T

CASE

=25°C, V

=1.2V

4.7

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See

Output Drive Currents on page 36

for typical drive current capabilities.

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 K

internal pull-ups: TRST, TMS, TDI.

Applies to three-statable pins: FLAG3-0.

Applies to three-statable pins with 22.5 kK

pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI.

Applies to open-drain output pins: EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note (No. 216) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

ADSP-21267

Rev. PrA

Page 15 of 44

January 2004

PRELIMINARY TECHNICAL DATA

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

The ADSP-21267's internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP's internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).

The ADSP-21267's internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP's internal clock (the clock
source for the parallel port logic and I/O pads).

Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (

Table 7

Internal (Core) Supply Voltage (V

DDINT

)

-0.3 V to +1.4 V

Analog (PLL) Supply Voltage (A

VDD

)

-0.3 V to +1.4 V

External (I/O) Supply Voltage (V

DDEXT

)

-0.3 V to +3.8 V

Input Voltage

-0.5 V to V

DDEXT

+ 0.5 V

Output Voltage Swing

-0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance

200 pF

Storage Temperature Range

-65

C to +150

Junction Temperature under Bias

125

Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions greater than those indicated
in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21267 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges.
Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.

Table 7. ADSP-21267 CLKOUT and CCLK Clock Generation Operation

Timing Requirements

Description

Calculation

CLKIN Input

Clock

1/t

CCLK

Core Clock

1/t

CCLK

Timing Requirements

Description

CLKIN Clock Period

CCLK

(Processor) Core Clock Period

SCLK

Serial Port Clock Period = (t

CCLK

) x SR

SPICLK

SPI Clock Period = (t

CCLK

) x SPIR

where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT CLKDIV)

SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock

Rev. PrA

Page 16 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Figure 5

shows Core to CLKIN ratios of 3:1, 8:1 and 16:1 with

external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the ADSP-
2126x SHARC DSP Core Manual.

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.

See

Figure 30 on page 36

under Test Conditions for voltage ref-

erence levels.

Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

Note the following definitions of various clock periods that are a
function of CLKIN and the appropriate ratio control.

Figure 5. Core Clock and System Clock Relationship to CLKIN

CLKIN

CCLK
(CORE CLOCK)

PLLILCLK

XTAL

OSC

PLL

3:1, 8:1,

16:1

CLKOUT

CLK-CFG [1:0]

ADSP-21267

Rev. PrA

Page 17 of 44

January 2004

PRELIMINARY TECHNICAL DATA

Power up Sequencing

The timing requirements for DSP startup are given in

Table 8

Table 8. Power Up Sequencing Timing Requirements (DSP Startup)

Parameter

Min

Max

Unit

Timing Requirements

RSTVDD

RESET low before V

DDINT

DDEXT

IVDDEVDD

DDINT

on before V

DDEXT

-50

200

CLKVDD

CLKIN valid after V

DDINT

DDEXT

valid

200

CLKRST

CLKIN valid before RESET deasserted

µs

PLLRST

PLL control setup before RESET deasserted

µs

WRST

Subsequent RESET low pulse width

Switching Characteristic

CORERST

DSP core reset deasserted after RESET deasserted

4096t

4,5

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in

Table 10

. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Figure 6. Power Up Sequencing

C LK IN

R ES E T

R S T V D D

R ST OU T*

V DDEX T

V DDINT

PL L R S T

C L K R S T

C L K V D D

IV D D E V D D

C LK _ C FG 1 -0

C O R E R S T

*M U LTIP LE X ED W ITH C LK O U T

Rev. PrA

Page 18 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Clock Input

Clock Signals

The ADSP-21267 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21267 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.

Figure 8

shows

the component connections used for a crystal operating in fun-

Reset

Table 9. Clock Input

Parameter

150 MHz

200 MHz

Unit

Min

Max

Min

Max

Timing Requirements

CLKIN Period

160

CKL

CLKIN Width Low

7.5

CKH

CLKIN Width High

7.5

CKRF

CLKIN Rise/Fall (0.4V-2.0V)

CCLK

CCLK Period

6.66

Applies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.

Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

Figure 7. Clock Input

CLKIN

CKH

CKL

Figure 8. 150 MHz or 200 MHz Operation (Fundamental Mode Crystal)

CLKIN

XTAL

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

Table 10. Reset

Parameter

Min

Max

Unit

Timing Requirements

WRST

RESET Pulse Width Low

Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100

s while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

SRST

RESET Setup Before CLKIN Low

Figure 9. Reset

CLKIN

RESET

WRST

SRST

Rev. PrA

Page 20 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Timer PWM_OUT Cycle Timing

The following timing specification applies to Timer[2:0] in
PWM_OUT (pulse width modulation) mode. Timer signals are
routed to the DAI_P[20:1] pins through the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P[20:1] pins.

Timer WDTH_CAP Timing

The following timing specification applies to Timer[2:0] in
WDTH_CAP (pulse width count and capture) mode. Timer sig-
nals are routed to the DAI_P[20:1] pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P[20:1] pins.

Table 13. Timer[2:0] PWM_OUT Timing

Parameter

Min

Max

Unit

Switching Characteristic

PWMO

Timer[2:0] Pulse Width Output

2 t

CCLK

2(2

1) t

CCLK

Figure 12. Timer[2:0] PWM_OUT Timing

DAI_P[20:1]

(TIMER[2:0])

PWMO

Table 14. Timer[2:0] Width Capture Timing

Parameter

Min

Max

Unit

Timing Requirement

PWI

Timer[2:0] Pulse Width

2 t

CCLK

2(2

1) t

CCLK

Figure 13. Timer[2:0] Width Capture Timing

DAI_P[20:1]

(TIMER[2:0])

PWI

Rev. PrA

Page 22 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that
the Precision Clock Generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG's

inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is not timing data available. All Timing
Parameters and Switching Characteristics apply to external DAI
pins (DAI_P07 DAI_P20).

Table 16. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

PCGIW

Input Clock Pulse Width

STRIG

PCG Trigger Setup Before Falling Edge of PCG Input Clock

HTRIG

PCG Trigger Hold After Falling Edge of PCG Input Clock

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG Input
Clock Falling Edge

2.5

DTRIG

PCG Output Clock and Frame Sync Delay After PCG Trigger

2.5 + 2.5 x t

PCGOW

10 + 2.5 x t

PCGOW

Output Clock Pulse Width

Figure 15. Precision Clock Generator (Direct Pin Routing)

DAI_Pn

PCG_TRIGx_I

STRIG

DAI_Pm

PCG_EXTx_I

(CLKIN)

DAI_Py

PCG_CLKx_O

DAI_Pz

PCG_FSx_O

HTRIG

DPCGIO

DTRIG

PCGOW

PCGIW

Rev. PrA

Page 24 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Memory ReadParallel Port

Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the ADSP-21267
is accessing external memory space.

Table 18. 8-Bit Memory Read Cycle

Parameter

Min

Max

Unit

Timing Requirements

DRS

Address/Data [7:0] Setup Before RD High

3.3

DRH

Address/Data [7:0] Hold After RD High

DAD

Address [15:8] to Data Valid

D + 0.5 x t

CCLK

3.5

Switching Characteristics

ALEW

ALE Pulse Width

2 x t

CCLK

ALERW

ALE Deasserted to Read/Write Asserted

1 x t

CCLK

ADAS

Address/Data [15:0] Setup Before ALE Deasserted

2.5 x t

CCLK

2.0

ADAH

Address/Data [15:0] Hold After ALE Deasserted

0.5 x t

CCLK

0.8

ALEHZ

ALE

Deasserted

to Address/Data[7:0] In High Z

0.5 x t

CCLK

0.8

0.5 x t

CCLK

+ 3.0

RD Pulse Width

D 2

ADRH

Address/Data [15:8] Hold After RD High

0.5 x t

CCLK

1 + H

D = (Data Cycle Duration) x t

CCLK

H= t

CCLK

(if a hold cycle is specified, else H = 0)

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

Figure 17. Read Cycle For 8-bit Memory Timing

VALID DATA

AD[15:8

]

VALID ADDRESS

ADAS

VALID ADDRESS

AD[7:0]

ALEW

ALE

ADAH

ADRH

ALEHZ

DRS

DRH

DAD

ALERW

Rev. PrA

Page 26 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Memory Write--Parallel Port

Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21267 is accessing external memory space.

Table 20. 8-bit Memory Write Cycle

Parameter

Min

Max

Unit

Switching Characteristics:

ALEW

ALE Pulse Width

2 x t

CCLK

ALERW

ALE Deasserted to Read/Write Asserted

1 x t

CCLK

ADAS

Address/Data [15:0] Setup Before ALE Deasserted

2.5 x t

CCLK

2.0

ADAH

Address/data [15:0] Hold After ALE Deasserted

0.5 x t

CCLK

0.8

WR Pulse Width

D - 2

ADWL

Address/Data [15:8] to WR Low

0.5 x t

CCLK

1.5

ADWH

Address/Data [15:8] hold after WR High

0.5 x t

CCLK

1 + H

ALEHZ

ALE Deasserted

to Address/Data[15:0] In High Z

0.5 x t

CCLK

0.8

0.5t

CCLK

+ 3.0

DWS

Address/Data [7:0] Setup Before WR High

DWH

Address/Data [7:0] Hold After WR High

0.5 x t

CCLK

1.5 + H

DAWH

Address/Data to WR High

D = (Data Cycle Duration) x t

CCLK

H = t

CCLK

(if a hold cycle is specified, else H = 0)

On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.

Figure 19. Write Cycle For 8-bit Memory Timing

AD[15:8

]

VALID ADDRESS

ADAS

AD[7:0]

ALEW

ALE

ADAH

ADWH

ADWL

ALEHZ

VALID DATA

DWS

DWH

VALID ADDRESS

DAWH

ALERW

Rev. PrA

Page 28 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Serial Ports

To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P[20:1] pins using the SRU. Therefore, the timing specifi-
cations provided below are valid at the DAI_P[20:1] pins.

Table 22. Serial Ports--External Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSE

FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)

2.5

HFSE

FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)

2.5

SDRE

Receive Data Setup Before Receive SCLK

2.5

HDRE

Receive Data Hold After SCLK

2.5

SCLKW

SCLK Width

SCLK

SCLK Period

Switching Characteristics

DFSE

FS Delay After SCLK
(Internally Generated FS in Ether Transmit or Receive Mode)

HOFSE

FS Hold After SCLK
(Internally Generated FS in Either Transmit or Receive Mode

) 2

DDTE

Transmit Data Delay After Transmit SCLK

HDTE

Transmit Data Hold After Transmit SCLK

Referenced to sample edge.

Referenced to drive edge.

Table 23. Serial Ports--Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

SFSI

FS Setup Before SCLK
(Externally Generated FS in Either Transmit or Receive Mode)

HFSI

FS Hold After SCLK
(Externally Generated FS in Either Transmit or Receive Mode)

1.5

SDRI

Receive Data Setup Before SCLK

HDRI

Receive Data Hold After SCLK

1.5

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

-1.0

DFSI

FS Delay After SCLK (Internally Generated FS in Receive or Mode)

HOFSI

FS Hold After SCLK (Internally Generated FS in Receive Mode)

-1.0

DDTI

Transmit Data Delay After SCLK

HDTI

Transmit Data Hold After SCLK

-1.0

SCLKIW

Transmit or Receive SCLK Width

0.5t

SCLK

0.5t

SCLK

+ 2

Referenced to the sample edge.

Referenced to drive edge.

ADSP-21267

Rev. PrA

Page 29 of 44

January 2004

PRELIMINARY TECHNICAL DATA

Table 24. Serial Ports--Enable and Three-State

Parameter

Min

Max

Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK

DDTTE

Data Disable from External Transmit SCLK

DDTIN

Data Enable from Internal Transmit SCLK

-1

Referenced to drive edge.

Table 25. Serial Ports--External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0

DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

The t

DDTLFSE

and t

DDTENFS

parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 21. External Late Frame Sync

This figure reflects changes made to support Left-justified Sample Pair mode.

DRIVE

SAMPLE

DRIVE

DIA_P[20:0]

(SCLK)

DIA_P[20:0]

(FS)

DIA_P[20:0]

(DXA/DXB)

DRIVE

SAMPLE

DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

1ST BIT

2ND BIT

DIA_P[20:0]

(SCLK)

DIA_P[20:0]

(FS)

1ST BIT

2ND BIT

HFSE/I

SFSE/I

DDTE/I

DDTENFS

DDTLFSE

HDTE/I

HFSE/I

SFSE/I

DDTE/I

DDTENFS

DDTLFSE

HDTE/I

DIA_P[20:0]

(DXA/DXB)

NOTE
SERIAL PORT SIGNALS (SCLK, FS, DXA,/DXB) ARE ROUTED TO THE DAI_P[20:1] PINS USING THE SRU.
THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.

Rev. PrA

Page 30 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Figure 22. Serial Ports

DRIVE EDGE

SCLK

DDTTE

DDTEN

DDTIN

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DRIVE EDGE

SAMPLE EDGE

DATA RECEIVE-- INTERNAL CLOCK

DATA RECEIVE-- EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

SDRI

HDRI

SFSI

HFSI

DFSI

HOFSI

SCLKIW

SDRE

HDRE

SFSE

HFSE

DFSE

SCLKW

HOFSE

DAI_P[20:1]

(DXA/DXB)

DDTI

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT -- INTERNAL CLOCK

SFSI

HFSI

DFSI

HOFSI

SCLKIW

HDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTE

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT -- EXTERNAL CLOCK

SFSE

HFSE

DFSE

HOFSE

SCLKW

HDTE

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DAI_P[20:1]

(SCLK)

DAI_P[20:1]

(FS)

DAI_P[20:1]

(DXA/DXB)

DAI_P[20:1]

SCLK (INT)

DAI_P[20:1]
SCLK (EXT)

DAI_P[20:1]

DXA/DXB

DAI_P[20:1]

DXA/DXB

Rev. PrA

Page 32 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 27

. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2126x Hardware Reference Manual. Note

that the most significant 16 bits of external PDAP data can be
provided through either the parallel port AD[15:0] or the
DAI_P[20:5] pins. The remaining 4 bits can only be sourced
through DAI_P[4:1]. The timing below is valid at the
DAI_P[20:1] pins or at the AD[15:0] pins.

Table 27. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

2.5

HPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

2.5

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

2.5

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

2.5

PDCLKW

Clock Width

PDCLK

Clock Period

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

2 x t

CCLK

PDSTRB

PDAP Strobe Pulse Width

1 x t

CCLK

Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 24. PDAP Timing

DAI_P[20:1]

(PDAP_CLK)

SAMPLE EDGE

PDSD

PDHD

SPCLKEN

HPCLKEN

PDCLKW

DATA

DAI_P[20:1]

(PDAP_CLKEN)

PDSTRB

PDHLDD

DAI_P[20:1]

(PDAP_STROBE)

ADSP-21267

Rev. PrA

Page 33 of 44

January 2004

PRELIMINARY TECHNICAL DATA

SPI Interface--Master

Table 28. SPI Interface Protocol -- Master Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

SSPIDM

Data input valid to SPICLK edge (data input set-up time)

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid

Switching Characteristics

SPICLKM

Serial Clock Cycle

8 x t

CCLK

SPICHM

SeriaL Clock High Period

4 x t

CCLK

SPICLM

SeriaL Clock Low Period

4 x t

CCLK

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time)

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SDSCIM

FLAG3-0 OUT (SPI Device Select) Low to First SPICLK Edge

4 x t

CCLK

HDSM

Last SPICLK Edge to FLAG3-0 OUT High

4 x t

CCLK

SPITDM

Sequential Transfer Delay

4 x t

CCLK

Figure 25. SPI Master Timing

LSB

VALID

MSB

VALID

S S P I D M

H S P I D M

HDSPIDM

LSB

MSB

H S P I D M

D D S P I D M

MOSI

(OUTPUT)

MISO

(INPUT)

FLG3-0

(OUTPUT)

SPICLK
(CP = 0)

(OUTPUT)

SPICLK
(CP = 1)

(OUTPUT)

S P I C H M

S P IC LM

S P IC LK M

S P I C H M

H D S M

S P I T D M

H D S P I D M

LSB

VALID

LSB

MSB

VALID

H S P ID M

D D S P I D M

MOSI

(OUTPUT)

MISO

(INPUT)

S S P I D M

CPHASE = 1

CPHASE = 0

S D S C I M

S S P ID M

Rev. PrA

Page 34 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

SPI Interface--Slave

Table 29. SPI Interface Protocol --Slave Switching and Timing Specifications

Parameter

Min

Max

Unit

Timing Requirements

SPICLKS

Serial Clock Cycle

4 x t

CCLK

SPICHS

Serial Clock High Period

2 x t

CCLK

SPICLS

Serial Clock Low Period

2 x t

CCLK

SDSCO

SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1

2 x t

CCLK

+ 1

2 x t

CCLK

+ 1

ns
ns

HDS

Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0

2 x t

CCLK

SSPIDS

Data Input Valid to SPICLK Edge (Data Input Set-up Time)

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid

SDPPW

SPIDS Deassertion Pulse Width (CPHASE=0)

2 x t

CCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active

DSDHI

SPIDS Deassertion to Data High Impedance

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

7.5

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

2 x t

CCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE=0)

5 x t

CCLK

+ 2

Figure 26. SPI Slave Timing

H S P I D S

D D S P I D S

D S D H I

LSB

MSB

MSB VALID

D S O E

D D S P I D S

H D S P I D S

MISO

(OUTPUT)

MOSI

(INPUT)

S S P I D S

SPIDS

(INPUT)

SPICLK
(CP = 0)
(INPUT)

SPICLK
(CP = 1)
(INPUT)

S D S C O

S P IC H S

S P I C L S

S P I C L K S

H D S

S P I C H S

S S P I D S

H S P I D S

D S D H I

LSB VALID

MSB

MSB VALID

D S O E

D D S P I D S

MISO

(OUTPUT)

MOSI

(INPUT)

S S P I D S

LSB VALID

LSB

CPHASE = 1

CPHASE = 0

S D P P W

D S O V

H D S P I D S

Rev. PrA

Page 36 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

OUTPUT DRIVE CURRENTS

Figure 28

shows typical I-V characteristics for the output driv-

ers of the ADSP-21267. The curves represent the current drive
capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear

Table 9

on page 18

through

Table 30 on page 35

. These include output

disable time, output enable time, and capacitive loading.

Timing is measured on signals when they cross the 1.5 V level as
described in

Figure 30 on page 36

. All delays (in nanoseconds)

are measured between the point that the first signal reaches
1.5 V and the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:
12 pF on all pins (see

Figure 29

Figure 32

shows graphically

how output delays and holds vary with load capacitance (Note
that this graph or derating does not apply to output disable
delays. The graphs of

Figure 31

Figure 32

and

Figure 33

may

not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20%-80%,
V=Min) vs. Load Capacitance.

Figure 28. ADSP-21267 Typical Drive

Figure 29. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 30. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE - V

-20

3.5

0.5

1.5

2.5

-40

-30

-10

(
V

)

VOL TBD

VOH TBD

1.5V

30pF

OUTPUT

PIN

INPUT

OUTPUT 1.5V

1.5V

Figure 31. Typical Output Rise Time

(20%-80%, V

DDEXT

= Max)

Figure 32. Typical Output Rise/Fall Time

(20%-80%, V

DDEXT

= Min)

LOAD CAPACITANCE - PF

8.0

120

100

12.0

4.0

2.0

10.0

6.0

I
S

I
M

TBD

LOAD CAPACITANCE - pF

120

100

I
S

I
M

TBD

ADSP-21267

Rev. PrA

Page 37 of 44

January 2004

PRELIMINARY TECHNICAL DATA

ENVIRONMENTAL CONDITIONS

The ADSP-21267 processor is rated for performance over the
commercial temperature range, T

AMB

= 0°C to 70°C.

THERMAL CHARACTERISTICS

The ADSP-21267 is offered in 144-lead LQFP and 136-ball BGA
packages

Table 31

and

Table 32

airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6 and the junction-to-
board measurement complies with JESD51-8. The junction-to-
case measurement complies with MIL- STD-883. All measure-
ments use a 2S2P JEDEC test board.

To determine the Junction Temperature of the device while on
the application PCB, use:

Where:

= Junction temperature

CASE

= Case temperature (

C) measured at the top center of the

package

= Junction-to-Top (of package) characterization parameter

= Typical value from the tables below

= Power dissipation see EE Note #216

Values of

are provided for package comparison and PCB

design considerations.

can be used for a 1

order approxima-

tion of T

by the equation:

Where:

= Ambient Temperature

Values of

are provided for package comparison and PCB

design considerations when an external heatsink is required.

Values of

are provided for package comparison and PCB

design considerations.

Figure 33. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

LOAD CAPACITANCE - pF

120

100

-4

-1

-2

-3

TBD

CASE

(

)

(

)

Table 31. Thermal Characteristics for 136 Ball BGA

Parameter

Condition

Typical

Unit

Airflow = 0 m/s

28.2

°C/W

JMA

Airflow = 1 m/s

24.4

°C/W

JMA

Airflow = 2 m/s

23.3

°C/W

20.1

°C/W

7.0

°C/W

Airflow = 0 m/s

0.1

°C/W

JMT

Airflow = 1 m/s

0.3

°C/W

JMT

Airflow = 2 m/s

0.4

°C/W

Table 32. Thermal Characteristics for 144 Lead LQFP

Parameter

Typical

Unit

Airflow = 0 m/s

32.5

°C/W

JMA

Airflow = 1 m/s

28.9

°C/W

JMA

Airflow = 2 m/s

27.8

°C/W

7.8

°C/W

Airflow = 0 m/s

0.5

°C/W

JMT

Airflow = 1 m/s

0.8

°C/W

JMT

Airflow = 2 m/s

1.0

°C/W

Rev. PrA

Page 38 of 44

January 2004

ADSP-21267

PRELIMINARY TECHNICAL DATA

136-BALL BGA PIN CONFIGURATIONS

The following table shows the ADSP-21267's pin names and
their default function after reset (in parenthesis).

Table 33. 136-ball BGA Pin Assignments

Pin Name

BGA
Pin#

Pin Name

BGA
Pin#

Pin Name

BGA
Pin#

Pin Name

BGA
Pin#

CLKCFG0

A01

CLKCFG1

B01

BOOTCFG1

C01

DDINT

D01

XTAL

A02

GND

B02

BOOTCFG0

C02

GND

D02

TMS

A03

DDEXT

B03

GND

C03

GND

D04

TCK

A04

CLKIN

B04

GND

C12

GND

D05

TDI

A05

TRST

B05

GND

C13

GND

D06

CLKOUT

A06

VSS

B06

DDINT

C14

GND

D09

TDO

A07

VDD

B07

GND

D10

EMU

A08

DDEXT

B08

GND

D11

MOSI

A09

SPICLK

B09

GND

D13

MISO

A10

RESET

B10

DDINT

D14

SPIDS

A11

DDINT

B11

DDINT

A12

GND

B12

GND

A13

GND

B13

GND

A14

GND

B14

DDINT

E01

FLAG1

F01

AD7

G01

AD6

H01

GND

E02

FLAG0

F02

DDINT

G02

DDEXT

H02

GND

E04

GND

F04

DDEXT

G13

DAI_P18 (SD5B)

H13

GND

E05

GND

F05

DAI_P19 (SCLK45)

G14

DAI_P17 (SD5A)

H14

GND

E06

GND

F06

GND

E09

GND

F09

GND

E10

GND

F10

GND

E11

GND

F11

GND

E13

FLAG2

F13

FLAG3

E14

DAI_P20 (SFS45)

F14

ADSP-21267

Rev. PrA

Page 41 of 44

January 2004

PRELIMINARY TECHNICAL DATA

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-21267's pin names and
their default function after reset (in parenthesis).

Table 34. 144-Lead LQFP Pin Assignments

Pin Name

LQFP
Pin #

Pin Name

LQFP
Pin #

Pin Name

LQFP
Pin #

Pin Name

LQFP
Pin #

DDINT

DDEXT

GND

109

CLKCFG0

GND

DDINT

110

CLKCFG1

DDINT

GND

111

BOOTCFG0

ALE

GND

76 V

DDINT

112

BOOTCFG1

AD15

DAI_P10 (SD2B)

GND

113

GND

AD14

DAI_P11 (SD3A)

DDINT

114

DDEXT

AD13

DAI_P12 (SD3B)

GND

115

GND

44 DAI_P13

(SCLK23)

DDEXT

116

DDINT

DDEXT

DAI_P14 (SFS23)

GND

117

GND

AD12

DAI_P15 (SD4A)

DDINT

118

DDINT

GND

119

GND

DDINT

120

DDINT

AD11

GND

RESET

121

GND

AD10

DAI_P16 (SD4B)

SPIDS

122

FLAG0

AD9

DAI_P17 (SD5A)

GND

123

FLAG1

AD8

DAI_P18 (SD5B)

DDINT

124

AD7

DAI_P1 (SD0A) 53

DAI_P19 (SCLK45)

SPICLK

125

GND

18 V

DDINT

MISO

126

DDINT

GND

55 GND

MOSI

127

GND

DAI_P2 (SD0B) 56

GND

128

DDEXT

DAI_P3 (SCLK0) 57

DDEXT

DDINT

129

GND

DAI_P20 (SFS45)

DDEXT

130

DDINT

DDEXT

GND

VDD

131

AD6

DDINT

VSS

132

AD5

GND

FLAG2

GND

133

AD4

DAI_P4 (SFS0)

FLAG3

CLKOUT

134

DDINT

DAI_P5 (SD1A) 63

DDINT

EMU

135

GND

DAI_P6 (SD1B) 64

GND

100

TDO

136

AD3

DAI_P7 (SCLK1) 65

DDINT

101

TDI

137

AD2

DDINT

GND

102

TRST

138

DDEXT

GND

DDINT

103

TCK

139

GND

DDINT

GND

104

TMS

140

AD1

GND

69 V

DDINT

105

GND

141

AD0

DAI_P8 (SFS1)

GND

106

CLKIN

142

DAI_P9 (SD2A) 71

DDINT

107

XTAL

143

DDINT

108

DDEXT

144

ADSP-21267

Rev. PrA

Page 43 of 44

January 2004

PRELIMINARY TECHNICAL DATA

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and
combinations to run on the ADSP-21267 DSP. These products
are sold as part of a chip set, bundled with necessary application
software under special part numbers. For a complete list, visit
our web site at www.analog.com\SHARC.

These product also may contain 3rd party IPs that may require
users to have authorization from the respective IP holders to
receive them. Royalty for use of the 3rd party IPs may also be
payable by users.

Figure 36. 144-lead LQFP (ST-144)

SEATING

PLANE

1.60 MAX

0.15
0.05

0.08 MAX (LEAD

COPLANARITY)

1.45
1.40
1.35

0.27
0.22
0.17

TYP

0.50
BSC
TYP
(LEAD
PITCH)

3 6

108

144

109

TOP VIEW (PINS DOWN)

22.00 BSC SQ

20.00 BSC SQ

DETAIL A

PIN 1 INDICATOR

0.75
0.60 TYP
0.45

1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY

WITH JEDEC STANDARD MS-026-BFB.

2. ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08

OF ITS IDEAL POSITION, WHEN MEASURED IN THE
LATERAL DIRECTION.

3. CENTER DIMENSIONS ARE NOMINAL.

NOTES:

Part Number

1,2,3

Ambient Temper-
ature Range

Instruction Rate On-Chip

SRAM

ROM

Operating Voltage Package

ADSP-21267SKSTZ-X

C to +70

150 MHz

1 Mbit

3 Mbit

1.2 INT/3.3 EXT V

144-Lead LQFP

ADSP-21267SKBCZ-X

C to +70

150 MHz

1 Mbit

3 Mbit

1.2 INT/3.3 EXT V

136-Lead BGA

K indicates commercial grade temperature (0

C to +70

C).

B indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package.

Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-21267

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-21267