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Preliminary Technical Data

SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.

SHARC

Processor

ADSP-21364

Rev. PrB

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781.329.4700

www.analog.com

Fax:781.326.8703

SUMMARY

High performance 32-bit/40-bit floating point processor

optimized for professional audio processing

At 333 MHz/2 GFLOPs, with unique audio centric peripherals

such as the Digital Audio Interface that includes a high-
precision 8-channel asynchronous sample rate converter
among others, the ADSP-21364 SHARC processor is ideal
for applications that require industry leading equalization,
reverberation and other effects processing

Single-Instruction Multiple-Data (SIMD) computational

architecture
Two 32-bit IEEE floating-point/32-bit fixed-point/40-bit
extended precision floating-point computational units,
each with a multiplier, ALU, shifter, and register file

On-chip memory--3M bit of on-chip SRAM and a dedicated

4M bit of on-chip mask-programmable ROM

Code compatible with all other members of the SHARC family
The ADSP-21364 is available with a 333 MHz core instruction

rate and unique audio centric peripherals such as the Digi-
tal Audio Interface, S/PDIF transceiver, serial ports, 8-
channel asynchronous sample rate converter, precision
clock generators and more. For complete ordering infor-
mation, see

Ordering Guide on Page 52

Figure 1. Functional Block Diagram Processor Core

ADDR

DATA

IOD

ADDR

DATA

IOA

ADDR

DATA

IOA

SRAM

1M BIT

ROM

2M BIT

SRAM

0.5M BIT

BLOCK 0

BLOCK 1

BLOCK 2

BLOCK 3

ADDR

DATA

IOA

IOP REGISTERS

(MEMORY MAPPED)

SEE "ADSP-21364 MEMORY

AND I/O INTERFACE FEATURES"

SECTION FOR DETAILS

I/O PROCESSOR

AND PERIPHERALS

JTAG TEST & EMULATION

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

PX REGISTER

PROCESSING

ELEMENT

(PEY)

PROCESSING

ELEMENT

(PEX)

TIMER

INSTRUCTION

CACHE

32 X 48-BIT

DAG1

8X4X32

DAG2

8X4X32

CORE PROCESSOR

PROGRAM

SEQUENCER

SRAM

1M BIT

ROM

2M BIT

SIGNAL

ROUTING

UNIT

SRAM

0.5M BIT

4 BLOCKS OF ON-CHIP MEMORY

IOD

IOA

IOD

SPI

SPORTS

IDP

PCG

TIMERS

SRC

SPDIF

Rev. PrB

Page 2 of 52

September 2004

ADSP-21364

Preliminary Technical Data

KEY FEATURES PROCESSOR CORE

At 333 MHz (3.0 ns) core instruction rate, the ADSP-21364

performs 2 GFLOPS/666 MMACS

3M bit on-chip single-ported SRAM (1M Bit in blocks 0 and 1,

and 0.50M Bit in blocks 2 and 3) for simultaneous access by
core processor and DMA

4M bit on-chip single-ported mask-programmable ROM (2M

bit in block 0 and 2M bit in block 1)
Dual Data Address Generators (DAGs) with modulo and
bit-reverse addressing

Zero-overhead looping with single-cycle loop setup, provid-

ing efficient program sequencing

Single Instruction Multiple Data (SIMD) architecture

provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at

the assembly level

Parallelism in busses and computational units allows sin-

gle cycle execution (with or without SIMD) of a multiply
or ALU operation, a dual memory read or write, and an
instruction fetch

Transfers between memory and core at a sustained 5.4

Gbytes/s bandwidth at 333 MHz core instruction rate

INPUT/OUTPUT FEATURES

DMA Controller supports:
25 DMA channels for transfers between ADSP-21364 internal

memory a variety of peripherals

32-bit DMA transfers at core clock speed, in parallel with full-

speed processor execution

Asynchronous parallel port provides access to asynchronous

external memory

16 multiplexed address/data lines support 24-bit address

external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55 Mbyte per sec transfer rate

External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two Pre-

cision Clock Generators, an Input Data Port, three timers,
eight-channel asynchronous sample rate converter, and a
Signal routing unit

Six dual data line serial ports that operate at up to 50M bit/s

on each data line--each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair

Left-justified Sample Pair and I

S Support, programmable

direction for up to 24 simultaneous receive or transmit
channels using two I

S compatible stereo devices per serial

port

TDM support for telecommunications interfaces including

128 TDM channel support for newer telephony interfaces
such as H.100/H.110

Up to 12 TDM stream support, each with 128 channels per

frame

Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the

SHARC core, configurable as eight channels of serial data
or seven channels of serial data and a single channel of up
to 20-bit wide parallel data

Signal routing unit provides configurable and flexible con-

nections between all DAI componentssix serial ports, two
precision clock generators, an input data port with a data
acquisition port, one SPI port, eight channels of asynchro-
nous sample rate converters, three timers, 10 interrupts,
six flag inputs, six flag outputs, and 20 SRU I/O pins
(DAI_Px)

Two Serial Peripheral Interfaces (SPI): primary on dedicated

pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master-Slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases

3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line

DEDICATED AUDIO COMPONENTS

S/PDIF Compatible Digital Audio receiver/transmitter

supports:
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left justified, I

S or right justified serial data input with 16,

18, 20 or 24 bit word widths (transmitter)
Two channel mode and Single Channel Double Frequency
(SCDF) mode

Sample Rate Converter (SRC) Contains a Serial Input Port, De-

emphasis Filter providing up to -140db SNR performance,
Sample Rate Converter (SRC) and Serial Output Port
Supports Left Justified, I

S, TDM and Right Justified 24, 20,

18 and 16 bit serial formats (input)

Pulse Width Modulation provides:

16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode

PLL has a wide variety of software and hardware multi-

plier/divider ratios

Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball Mini-BGA and 144-lead LQFP Packages

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 3 of 52

September 2004

GENERAL DESCRIPTION

The ADSP-21364 SHARC processor is a member of the SIMD
SHARC family of DSPs that feature Analog Devices' Super Har-
vard Architecture. The ADSP-21364 is source code compatible
with the ADSP-2126x, and ADSP-2116x DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. The ADSP-21364 is a 32-
bit/40-bit floating point processor optimized for professional
audio applications with a large on-chip SRAM, multiple internal
buses to eliminate I/O bottlenecks, and an innovative Digital
Audio Interface (DAI).

As shown in the functional block diagram

on Page 1

, the

ADSP-21364 uses two computational units to deliver a signifi-
cant performance increase over previous SHARC processors on
a range of signal processing algorithms. Fabricated in a state-of-
the-art, high speed, CMOS process, the ADSP-21364 processor
achieves an instruction cycle time of 3.0 ns at 333 MHz. With its
SIMD computational hardware, the ADSP-21364 can perform 2
GFLOPS running at 333 MHz.

Table 1

shows performance benchmarks for the ADSP-21364.

The ADSP-21364 continues SHARC's industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features.

The block diagram of the ADSP-21364

on Page 1

, illustrates the

following architectural features:

· Two processing elements, each of which comprises an

ALU, Multiplier, Shifter and Data Register File

· Data Address Generators (DAG1, DAG2)

· Program sequencer with instruction cache

· PM and DM buses capable of supporting four 32-bit data

transfers between memory and the core at every core pro-
cessor cycle

· Three Programmable Interval Timers with PWM Genera-

tion, PWM Capture/Pulse width Measurement, and
External Event Counter Capabilities

· On-Chip SRAM (3M bit)

· On-Chip mask-programmable ROM (4M bit)

· 8- or 16-bit Parallel port that supports interfaces to off-chip

memory peripherals

· JTAG test access port

The block diagram of the ADSP-21364

on Page 6

, illustrates the

following architectural features:

· DMA controller

· Six full duplex serial ports

· Two SPI-compatible interface ports--primary on dedi-

cated pins secondary on DAI pins

· Digital Audio Interface that includes two precision clock

generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, six serial ports, eight serial interfaces, a 20-
bit parallel input port, 10 interrupts, six flag outputs, six
flag inputs, three timers, and a flexible signal routing unit
(SRU)

Figure 2 on Page 4

shows one sample configuration of a SPORT

using the precision clock generators to interface with an I

ADC and an I

S DAC with a much lower jitter clock than the

serial port would generate itself. Many other SRU configura-
tions are possible.

ADSP-21364 FAMILY CORE ARCHITECTURE

The ADSP-21364 is code compatible at the assembly level with
the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC DSPs. The ADSP-21364
shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC processors, as detailed in the fol-
lowing sections.

SIMD Computational Engine

The ADSP-21364 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.

Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.

Table 1. ADSP-21364 Benchmarks (at 333 MHz)

Benchmark Algorithm

Speed
(at 333 MHz)

1024 Point Complex FFT (Radix 4, with reversal) 27.9

µs

FIR Filter (per tap)

Assumes two files in multichannel SIMD mode

1.5 ns

IIR Filter (per biquad)

6.0 ns

Matrix Multiply (pipelined)
[3x3] × [3x1]
[4x4] × [4x1]

13.5 ns
23.9 ns

Divide (y/×)

10.5 ns

Inverse Square Root

16.3 ns

Rev. PrB

Page 4 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Independent, Parallel Computation Units

Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.

Data Register File

A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0R15 and in PEY as S0S15.

Single-Cycle Fetch of Instruction and Four Operands

The ADSP-21364 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see

Figure 1 on Page 1

). With the ADSP-21364's separate pro-

gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.

Instruction Cache

The ADSP-21364 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective--only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.

Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support

The ADSP-21364's two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital

Figure 2. ADSP-21364 System Sample Configuration

DAI

SPI

IDP

SRC

SPDI F

SPORT0-5

SCLK0

SD0A

SFS0

SD0B

SRU

DAI_P1

DAI_P2
DAI_P3

DAI_P18

DAI _P19

DAI_P20

DAC

(OPTI ONAL)

ADC

(OPTI ONAL)

CLK

SDAT

CLK

SDAT

CLOCK

FLAG3-1

CLKIN
XTAL

CLK_CFG1-0

BOOTCFG1-0

ADDR

PARALLEL

PORT

RAM, ROM

BOO T ROM
I /O DEVI CE

DATA

CLKOUT

ALE

AD15-0

LATCH

RESET

JTAG

ADSP-21364

AD
DRE

FLAG0

PCG B

PCGA

CLK

TIMERS

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 5 of 52

September 2004

signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs of the ADSP-21364 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.

Flexible Instruction Set

The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-21364 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory--all in a single
instruction.

ADSP-21364 MEMORY AND I/O INTERFACE
FEATURES

The ADSP-21364 adds the following architectural features to
the SIMD SHARC family core.

On-Chip Memory

The ADSP-21364 contains three megabits of internal SRAM.
Each block can be configured for different combinations of code
and data storage (see

Table 2 on Page 5

). Each memory block

supports single-cycle, independent accesses by the core proces-
sor and I/O processor. The ADSP-21364 memory architecture,
in combination with its separate on-chip buses, allow two data
transfers from the core and one from the I/O processor, in a sin-
gle cycle.

The ADSP-21364's, SRAM can be configured as a maximum of
96K words of 32-bit data, 192K words of 16-bit data, 64K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to three megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.

Table 2. ADSP-21364 Internal Memory Space

IOP Registers 0x0000 0000 0003 FFFF

Long Word (64 bits)

Extended Precision Normal or
Instruction Word (48 bits)

Normal Word (32 bits)

Short Word (16 bits)

BLOCK 0 ROM
0x0004 0000 0x0004 7FFF

BLOCK 0 ROM
0x0008 00000x0008 AAAA

BLOCK 0 ROM
0x0008 0000 0x0008 FFFF

BLOCK 0 ROM
0x0010 00000x0011 FFFF

Reserved
0x0004 80000x0004 BFFF

Reserved
0x0009 00000x0009 7FFF

Reserved
0x0012 00000x0012 FFFF

BLOCK 0 RAM
0x0004 C0000x0004 FFFF

BLOCK 0 RAM
0x0009 00000x0009 5555

BLOCK 0 RAM
0x0009 80000x0009 FFFF

BLOCK 0 RAM
0x0013 00000x0013 FFFF

BLOCK 1 ROM
0x0005 00000x0005 7FFF

BLOCK 1 ROM
0x000A 00000x000A AAAA

BLOCK 1 ROM
0x000A 0000 0x000A FFFF

BLOCK 1 ROM
0x0014 00000x0015 FFFF

Reserved
0x0005 80000x0005 BFFF

Reserved
0x000B 00000x000B 7FFF

Reserved
0x0016 00000x0016 FFFF

BLOCK 1 RAM
0x0005 C0000x0005 FFFF

BLOCK 1 RAM
0x000B 00000x000B 5555

BLOCK 1 RAM
0x000B 80000x000B FFFF

BLOCK 1 RAM
0x0017 00000x0017 FFFF

BLOCK 2 RAM
0x0006 00000x0006 1FFF

BLOCK 2 RAM
0x000C 00000x000C 2AAA

BLOCK 2 RAM
0x000C 00000x000C 3FFF

BLOCK 2 RAM
0x0018 00000x0018 7FFF

Reserved
0x0006 20000x0006 FFFF

Reserved
0x000C 4000 0x000D FFFF

Reserved
0x0018 80000x001B FFFF

BLOCK 3 RAM
0x0007 00000x0007 1FFF

BLOCK 3 RAM
0x000E 00000x000E 2AAA

BLOCK 3 RAM
0x000E 00000x000E 3FFF

BLOCK 3 RAM
0x001C 00000x001C 7FFF

Reserved
0x0007 20000x0007 FFFF

Reserved
0x000E 40000x000F FFFF

Reserved
0x001C 80000x001F FFFF

Reserved
0x0020 00000xFFFF FFFF

Rev. PrB

Page 6 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.

DMA Controller

The ADSP-21364's on-chip DMA controller allows data trans-
fers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta-
neously executing its program instructions. DMA transfers can
occur between the ADSP-21364's internal memory and its serial
ports, the SPI-compatible (Serial Peripheral Interface) ports, the
IDP (Input Data Port), the Parallel Data Acquisition Port
(PDAP), or the parallel port. Twenty-five channels of DMA are
available on the ADSP-21364--two for the SPI interface, two for
memory-to-memory transfers, twelve via the serial ports, eight
via the Input Data Port, and one via the processor's parallel
port. Programs can be downloaded to the ADSP-21364 using
DMA transfers. Other DMA features include interrupt genera-
tion upon completion of DMA transfers, and DMA chaining for
automatic linked DMA transfers.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the SHARCs DAI pins
(DAI_P201).

Programs make these connections using the Signal Routing
Unit (SRU, shown in

Figure 3

The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.

The DAI also includes six serial ports, two precision clock gen-
erators (PCGs), eight channels of asynchronous sample rate
converters, an input data port (IDP), an SPI port, six flag out-
puts and six flag inputs, and three timers. The IDP provides an
additional input path to the ADSP-21364 core, configurable as
either eight channels of I

S serial data or as seven channels plus

a single 20-bit wide synchronous parallel data acquisition port.
Each data channel has its own DMA channel that is indepen-
dent from the ADSP-21364's serial ports.

For complete information on using the DAI, see the ADSP-
2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-21364 features six synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices'
AD183x family of audio codecs, ADCs, and DACs. The serial
ports are made up of two data lines, a clock and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has a dedicated DMA channel.

Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.

The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.

Serial ports operate in four modes:

· Standard DSP serial mode

· Multichannel (TDM) mode

· I

S mode

· Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received--one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.

Figure 3. ADSP-21364 I/O Processor and Peripherals Block Diagram

1 6

P RECI SIO N CLOCK

GENERATORS (2)

S PI P ORT (1 )

S ERIAL PORTS (6 )

INPUT

DATA P ORTS (8 )

TI ME RS (3)

DMA CONTROLLER

IOP

GI
S

(
M

Y
M

TR
O

L,
S

TA
T

&
D

FFE

I/O PROCESSOR

P ARALLEL PO RT

GPI O FLAGS/I RQ/TIMEXP

I
G

I
N

G
U

NI
T

A D D RE SS /D AT A B U S/ G P IO

CO N T R O L /G PIO

DIGITAL AUDIO INTERFACE

2 5 C H A N NE LS

TO PROCES SOR BUSS ES AND

SYS TE M ME MO RY

IO ADDRE SS

BUS (18 )

PW M (1 6)

IO DATA
BUS (32 )

SPI PORT (1)

SRC (8 CHANNELS)

SPDIF (RX/ TX )

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 7 of 52

September 2004

Each of the serial ports supports the left-justified sample pair
and I

S protocols (I

S is an industry standard interface com-

monly used by audio codecs, ADCs and DACs such as the
Analog Devices AD183x family), with two data pins, allowing
four left-justified sample pair or I

S channels (using two stereo

devices) per serial port, with a maximum of up to 24 I

S chan-

nels. The serial ports permit little-endian or big-endian
transmission formats and word lengths selectable from 3 bits to
32 bits. For the left-justified sample pair and I

S modes, data-

word lengths are selectable between 8 bits and 32 bits. Serial
ports offer selectable synchronization and transmit modes as
well as optional µ-law or A-law companding selection on a per
channel basis. Serial port clocks and frame syncs can be inter-
nally or externally generated.

Parallel Port

The Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD150) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is 55M bytes/sec.

DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the parallel
port.

Serial Peripheral (Compatible) Interface

The ADSP-21364 SHARC processor contains two Serial Periph-
eral Interface ports (SPIs). The SPI is an industry standard
synchronous serial link, enabling the ADSP-21364 SPI compati-
ble port to communicate with other SPI compatible devices. The
SPI consists of two data pins, one device select pin, and one
clock pin. It is a full-duplex synchronous serial interface, sup-
porting both master and slave modes. The SPI port can operate
in a multimaster environment by interfacing with up to four
other SPI compatible devices, either acting as a master or slave
device. The ADSP-21364 SPI compatible peripheral implemen-
tation also features programmable baud rate and clock phase
and polarities. The ADSP-21364 SPI compatible port uses open
drain drivers to support a multimaster configuration and to
avoid data contention.

The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz Stereo
Asynchronous Sample Rate Converter providing up to 140dB
SNR. The SRC block is used to perform synchronous or asyn-
chronous sample rate conversion across independent stereo
channels, without using internal processor resources. The four
SRC blocks can also be configured to operate together to con-
vert multichannel audio data without phase mismatches.
Finally, the SRC is used to clean up audio data from jittery clock
sources such as the S/PDIF receiver.

S/PDIF Compatible Digital Audio Receiver/Transmitter
and Synchronous/Asynchronous Sample Rate Converter

The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left justified, I

S or right justified with word

widths of 16, 18, 20, or 24 bits.

The serial data, clock, and frame sync inputs to the S/PDIF
transmitter are routed through the Signal Routing Unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.

Pulse Width Modulation

The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
two outputs in paired mode or independent signals in non-
paired mode (applicable to a single group of four PWM
waveforms).

The entire PWM module has four groups of four PWM outputs
each. Therefore this module generates 16 PWM outputs in total.
Each PWM group produces two pairs of PWM signals on the
four PWM outputs.

The PWM generator is capable of operating in two distinct
modes while generating center-aligned PWM waveforms: single
update mode, or double update mode. In single update mode
the duty cycle values are programmable only once per PWM
period. This results in PWM patterns that are symmetrical
around the mid-point of the PWM period. In double update
mode, a second updating of the PWM registers is implemented
at the mid-point of the PWM period. In this mode, it is possible
to produce asymmetrical PWM patterns that produce lower
harmonic distortion in three-phase PWM inverters.

Rev. PrB

Page 8 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Timers

The ADSP-21364 has a total of four timers: a core timer able to
generate periodic software interrupts and three general purpose
timers that can generate periodic interrupts and be indepen-
dently set to operate in one of three modes:

· Pulse Waveform Generation mode

· Pulse Width Count /Capture mode

· External Event Watchdog mode

The core timer can be configured to use FLAG3 as a Timer
Expired signal, and each general-purpose timer has one bidirec-
tional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general purpose timers independently.

Program Booting

The internal memory of the ADSP-21364 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG10) pins (see

Table 6 on

Page 14

). Selection of the boot source is controlled via the SPI as

either a master or slave device.

Phase-Locked Loop

The ADSP-21364 uses an on-chip Phase-Locked Loop (PLL) to
generate the internal clock for the core. On power up, the
CLKCFG10 pins are used to select ratios of 32:1, 16:1, and 6:1
(see

Table 7 on Page 14

). After booting, numerous other ratios

can be selected via software control. The ratios are made up of
software configurable numerator values from 1 to 32 and soft-
ware configurable divisor values of 1, 2, 4, 8, and 16.

Power Supplies

The ADSP-21364 has separate power supply connections for the
internal (V

DDINT

), external (V

DDEXT

), and analog (A

VDD

VSS

)

power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.

Note that the analog supply (A

VDD

) powers the ADSP-21364's

clock generator PLL. To produce a stable clock, programs
should provide an external circuit to filter the power input to
the A

VDD

pin. Place the filter as close as possible to the pin. For

an example circuit, see

Figure 4

. To prevent noise coupling, use

a wide trace for the analog ground (A

VSS

) signal and install a

decoupling capacitor as close as possible to the pin. Note that
the A

VSS

and A

VDD

pins specified in

Figure 4

are inputs to the

processor and not the analog ground plane on the board.

Target Board JTAG Emulator Connector

Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21364 pro-
cessor to monitor and control the target board processor during
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-
sor stacks. The processor's JTAG interface ensures that the
emulator will not affect target system loading or timing.

For complete information on Analog Devices' SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate "Emulator Hardware User's Guide".

DEVELOPMENT TOOLS

The ADSP-21364 is supported with a complete set of
CROSSCORE® software and hardware development tools,
including Analog Devices emulators and VisualDSP++® devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21364.

The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.

The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer's development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to non intrusively poll
the processor as it is running the program. This feature, unique
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.

Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:

· View mixed C/C++ and assembly code (interleaved source

and object information)

· Insert breakpoints

Figure 4. Analog Power (A

VDD

) Filter Circuit

DDINT

VDD

VSS

0.01 F

0.1 F

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 9 of 52

September 2004

· Set conditional breakpoints on registers, memory,

and stacks

· Trace instruction execution

· Perform linear or statistical profiling of program execution

· Fill, dump, and graphically plot the contents of memory

· Perform source level debugging

· Create custom debugger windows

The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:

· Control how the development tools process inputs and

generate outputs

· Maintain a one-to-one correspondence with the tool's

command line switches

The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.

Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.

VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices' technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica-
tions. Download components from the Web and drop them into
the application. Publish component archives from within Visu-
alDSP++. VCSE supports component implementation in
C/C++ or assembly language.

Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi-
nition File (LDF), allowing the developer to move between the
graphical and textual environments.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.

Designing an Emulator-Compatible DSP Board (Target)

The Analog Devices family of emulators are tools that every
developer needs to test and debug hardware and software sys-
tems. Analog Devices has supplied an IEEE 1149.1 JTAG Test
Access Port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor's JTAG inter-
face--the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com-
mands, but once an operation has been completed by the
emulator, the processor system is set running at full speed with
no impact on system timing.

To use these emulators, the target board must include a header
that connects the processor's JTAG port to the emulator.

For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website (

www.analog.com

)--

use site search on "EE-68." This document is updated regularly
to keep pace with improvements to emulator support.

Evaluation Kit

Analog Devices offers a range of EZ-KIT Lite evaluation plat-
forms to use as a cost effective method to learn more about
developing or prototyping applications with Analog Devices
processors, platforms, and software tools. Each EZ-KIT Lite
includes an evaluation board along with an evaluation suite of
the VisualDSP++ development and debugging environment
with the C/C++ compiler, assembler, and linker. Also included
are sample application programs, power supply, and a USB
cable. All evaluation versions of the software tools are limited
for use only with the EZ-KIT Lite product.

The USB controller on the EZ-KIT Lite board connects the
board to the USB port of the user's PC, enabling the Visu-
alDSP++ evaluation suite to emulate the on-board processor in-
circuit. This permits the customer to download, execute, and
debug programs for the EZ-KIT Lite system. It also allows in-
circuit programming of the on-board Flash device to store user-
specific boot code, enabling the board to run as a standalone
unit without being connected to the PC.

With a full version of VisualDSP++ installed (sold separately),
engineers can develop software for the EZ-KIT Lite or any cus-
tom defined system. Connecting one of Analog Devices JTAG
emulators to the EZ-KIT Lite board enables high-speed, non-
intrusive emulation.

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 11 of 52

September 2004

PIN FUNCTION DESCRIPTIONS

ADSP-21364 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS and TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST). Tie or pull unused inputs to

DDEXT

or GND, except for the following:

· DAI_Px, SPICLK, MISO, MOSI, EMU, TMS, TRST, TDI,

and AD150 (NOTE: These pins have pullup resistors.)

The following symbols appear in the Type column of

Table 3

A = Asynchronous, G = Ground, I = Input, O = Output,
P = Power Supply, S = Synchronous, (A/D) = Active Drive,
(O/D) = Open Drain, and T = Three-State, (pd) = pulldown
resistor, (pu) = pullup resistor. .

Table 3. Pin Descriptions

Pin Type

State

During

After Reset

Function

AD150

I/O/T
(pu)

Three-state with
pullup enabled

Parallel Port Address/Data. The ADSP-21364 parallel port and its corresponding
DMA unit output addresses and data for peripherals on these multiplexed pins. The
multiplex state is determined by the ALE pin. The parallel port can operate in either
8-bit or 16-bit mode. Each AD pin has a 22.5 k

internal pullup resistor. See

Address

Data Modes on Page 14

for details of the AD pin operation.

For 8-bit mode: ALE is automatically asserted whenever a change occurs in the upper
16 external address bits, A238; ALE is used in conjunction with an external latch to
retain the values of the A238.
For 16-bit mode: ALE is automatically asserted whenever a change occurs in the
address bits, A150; ALE is used in conjunction with an external latch to retain the
values of the A150. To use these pins as flags (FLAGS150) or PWMs (PWM150), 1)
set (=1) bit 20 of the SYSCTL register to disable the parallel port, 2) set (=1) bits 2225
of the SYSCTL register to enable FLAGS in groups of four (bit 22 for FLAGS30, bit 23
for FLAGS74 etc.) or, set (=1) bits 2629 of the SYSCTL register to enable PWMs in
groups of four (bit 26 for PWM03, bit 27 for PWM47, and so on). When used as an
input, the IDP Channel0 can use these pins for parallel input data.

O
(pu)

Three-state, driven
high

Parallel Port Read Enable. RD is asserted low whenever the processor reads 8-bit or
16-bit data from an external memory device. When AD150 are flags, this pin remains
deasserted. RD has a 22.5 k

internal pullup resistor.

O
(pu)

Three-state, driven
high

Parallel Port Write Enable. WR is asserted low whenever the processor writes 8-bit or
16-bit data to an external memory device. When AD150 are flags, this pin remains
deasserted. WR has a 22.5 k

internal pullup resistor.

ALE

O
(pd)

Three-state, driven
low

Parallel Port Address Latch enable. ALE is asserted whenever the processor drives
a new address on the parallel port address pins. On reset, ALE is active high. However,
it can be reconfigured using software to be active low. When AD150 are flags, this
pin remains deasserted. ALE has a 20 k

internal pulldown resistor.

FLAG30

I/O/A

Three-state

Flag Pins. Each flag pin is configured via control bits as either an input or output. As
an input, it can be tested as a condition. As an output, it can be used to signal external
peripherals. These pins can be used as an SPI interface slave select output during SPI
mastering. These pins are also multiplexed with the IRQx and the TIMEXP signals.
In SPI master boot mode, FLAG0 is the slave select pin that must be connected to an
SPI EPROM. FLAG0 is configured as a slave select during SPI master boot. When bit 16
is set (=1) in the SYSCTL register, FLAG0 is configured as IRQ0.
When bit 17 is set (=1) in the SYSCTL register, FLAG1 is configured as IRQ1.
When bit 18 is set (=1) in the SYSCTL register, FLAG2 is configured as IRQ2.
When bit 19 is set (=1) in the SYSCTL register, FLAG3 is configured as TIMEXP which
indicates that the system timer has expired.

Rev. PrB

Page 12 of 52

September 2004

ADSP-21364

Preliminary Technical Data

DAI_P201

I/O/T
(pu)

Three-state with
programmable
pullup

Digital Audio Interface Pins. These pins provide the physical interface to the SRU.
The SRU configuration registers define the combination of on-chip peripheral inputs
or outputs connected to the pin and to the pin's output enable. The configuration
registers of these peripherals then determines the exact behavior of the pin. Any input
or output signal present in the SRU may be routed to any of these pins. The SRU
provides the connection from the Serial ports, Input data port, precision clock gener-
ators and timers, sample rate converters and SPI to the DAI_P201 pins These pins
have internal 22.5 k

pullup resistors which are enabled on reset. These pullups can

be disabled in the DAI_PIN_PULLUP register.

SPICLK

I/O
(pu)

Three-state with
pullup enabled

Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls
the rate at which data is transferred. The master may transmit data at a variety of baud
rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active
during data transfers, only for the length of the transferred word. Slave devices ignore
the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift
out and shift in the data driven on the MISO and MOSI lines. The data is always shifted
out on one clock edge and sampled on the opposite edge of the clock. Clock polarity
and clock phase relative to data are programmable into the SPICTL control register
and define the transfer format. SPICLK has a 22.5 k

internal pullup resistor.

SPIDS

Input only

Serial Peripheral Interface Slave Device Select. An active low signal used to select
the processor as an SPI slave device. This input signal behaves like a chip select, and
is provided by the master device for the slave devices. In multimaster mode the DSPs
SPIDS signal can be driven by a slave device to signal to the processor (as SPI master)
that an error has occurred, as some other device is also trying to be the master device.
If asserted low when the device is in master mode, it is considered a multimaster error.
For a single-master, multiple-slave configuration where flag pins are used, this pin
must be tied or pulled high to V

DDEXT

on the master device. For ADSP-21364 to

ADSP-21364 SPI interaction, any of the master ADSP-21364's flag pins can be used to
drive the SPIDS signal on the ADSP-21364 SPI slave device.

MOSI

I/O (O/D)
(pu)

Three-state with
pullup enabled

SPI Master Out Slave In. If the ADSP-21364 is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21364 is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input
data. In an ADSP-21364 SPI interconnection, the data is shifted out from the MOSI
output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a
22.5 k

internal pullup resistor.

MISO

I/O (O/D)
(pu)

Three-state with
pullup enabled

SPI Master In Slave Out. If the ADSP-21364 is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21364 is
configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting
output data. In an ADSP-21364 SPI interconnection, the data is shifted out from the
MISO output pin of the slave and shifted into the MISO input pin of the master. MISO
has a 22.5 k

internal pullup resistor. MISO can be configured as O/D by setting the

OPD bit in the SPICTL register.
Note: Only one slave is allowed to transmit data at any given time. To enable broadcast
transmission to multiple SPI-slaves, the processor's MISO pin may be disabled by
setting (=1) bit 5 (DMISO) of the SPICTL register.

BOOTCFG10

Input only

Boot Configuration Select. This pin is used to select the boot mode for the processor.
The BOOTCFG pins must be valid before reset is asserted. See

Table 6

for a description

of the boot modes.

Table 3. Pin Descriptions (Continued)

Pin Type

State

During

After Reset

Function

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 13 of 52

September 2004

CLKIN

Input only

Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21364 clock input.
It configures the ADSP-21364 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21364 to use the external clock source such as an
external clock oscillator. The core is clocked either by the PLL output or this clock input
depending on the CLKCFG10 pin settings. CLKIN may not be halted, changed, or
operated below the specified frequency.

XTAL

Output only

Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.

CLKCFG10

Input only

Core/CLKIN Ratio Control. These pins set the start up clock frequency. See

Table 7

for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multiplier
and divider in the PMCTL register at any time after the core comes out of reset.

RSTOUT/CLKOUT O

Output only

Local Clock Out/ Reset Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin.The functionality can be switched
between the PLL output clock and reset out by setting bit 12 of the PMCTREG register.
The default is reset out.

RESET

I/A

Input only

Processor Reset. Resets the ADSP-21364 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must be
asserted (low) at power-up.

TCK

Input only

Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21364.

TMS

I/S
(pu)

Three-state with
pullup enabled

Test Mode Select (JTAG). Used to control the test state machine. TMS has a 22.5 k

internal pullup resistor.

TDI

I/S
(pu)

Three-state with
pullup enabled

Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k

internal pullup resistor.

TDO

Three-state

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

I/A
(pu)

Three-state with
pullup enabled

Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low)
after power-up or held low for proper operation of the ADSP-21364. TRST has a
22.5 k

internal pullup resistor.

EMU

O (O/D)
(pu)

Three-state with
pullup enabled

Emulation Status. Must be connected to the ADSP-21364 Analog Devices processor
Tools product line of JTAG emulators target board connector only. EMU has a 22.5 k

internal pullup resistor.

DDINT

Core Power Supply. Nominally +1.2 V dc and supplies the processor's core processor
(13 pins on the Mini-BGA package, 32 pins on the LQFP package).

DDEXT

I/O Power Supply. Nominally +3.3 V dc. (6 pins on the Mini-BGA package, 10 pins on
the LQFP package).

VDD

Analog Power Supply. Nominally +1.2 V dc and supplies the processor's internal PLL
(clock generator). This pin has the same specifications as V

DDINT

, except that added

filtering circuitry is required.

For more information, see Power Supplies on Page 8.

VSS

Analog Power Supply Return.

GND

Power Supply Return. (54 pins on the Mini-BGA package, 39 pins on the LQFP
package).

RD, WR, and ALE are three-stated (and not driven) only when RESET is active.

Output only is a three-state driver with its output path always enabled.

Input only is a three-state driver with both output path and pullup disabled.

Three-state is a three-state driver with pullup disabled.

Table 3. Pin Descriptions (Continued)

Pin Type

State

During

After Reset

Function

Rev. PrB

Page 14 of 52

September 2004

ADSP-21364

Preliminary Technical Data

ADDRESS DATA PINS AS FLAGS

To use these pins as flags (FLAGS150) set (=1) bit 20 of the
SYSCTL register to disable the parallel port. Then set (=1) bits
22 to 25 in the SYSCTL register accordingly.

ADDRESS DATA MODES

The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23A8 when asserted, fol-
lowed by address bits A7A0 and data bits D7D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15A0 when asserted, followed by data bits D15D0 when
deasserted.

BOOT MODES

CORE INSTRUCTION RATE TO CLKIN RATIO MODES

For details on processor timing, see

Timing Specifications

and

Figure 5

on Page 17

Table 4. AD150 to Flag Pin Mapping

AD Pin

Flag Pin

AD Pin

Flag Pin

AD0

FLAG8

AD8

FLAG0

AD1

FLAG9

AD9

FLAG1

AD2

FLAG10

AD10

FLAG2

AD3

FLAG11

AD11

FLAG3

AD4

FLAG12

AD12

FLAG4

AD5

FLAG13

AD13

FLAG5

AD6

FLAG14

AD14

FLAG6

AD7

FLAG15

AD15

FLAG7

Table 5. Address/ Data Mode Selection

EP Data
Mode

ALE

AD70
Function

AD158
Function

8-bit

Asserted

A158

A2316

8-bit

Deasserted

D70

A70

16-bit

Asserted

A70

A158

16-bit

Deasserted

D70

D158

Table 6. Boot Mode Selection

BOOTCFG10

Booting Mode

SPI Slave Boot

SPI Master Boot

Parallel Port boot via EPROM

Table 7. Core Instruction Rate/ CLKIN Ratio Selection

CLKCFG10

Core to CLKIN Ratio

6:1

32:1

16:1

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 15 of 52

September 2004

ADSP-21364 SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

Specifications subject to change without notice.

K Grade

B Grade

C Grade

Min

Max

Min

Max

Min

Max

Unit

DDINT

Internal (Core) Supply Voltage

1.14

1.26

1.14

1.26

0.95

1.05

VDD

Analog (PLL) Supply Voltage

1.14

1.26

1.14

1.26

0.95

1.05

DDEXT

External (I/O) Supply Voltage

3.13

3.47

3.13

3.47

3.13

3.47

Applies to input and bidirectional pins: AD150, FLAG30, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.

High Level Input Voltage @ V

DDEXT

= max

2.0

DDEXT

+ 0.5

2.0

DDEXT

+ 0.5

2.0

DDEXT

+ 0.5

Low Level Input Voltage @ V

DDEXT

= min

0.5

+0.8

0.5

+0.8

0.5

+0.8

IH_CLKIN

Applies to input pin CLKIN.

High Level Input Voltage @ V

DDEXT

= max

1.74

DDEXT

+ 0.5

1.74

DDEXT

+ 0.5

1.74

DDEXT

+ 0.5

IL_CLKIN

Low Level Input Voltage @ V

DDEXT

= min

0.5

+1.19

0.5

+1.19

0.5

+1.19

AMB

See

Thermal Characteristics on Page 44

for information on thermal specifications.

See Engineer-to-Engineer Note (No. TBD) for further information.

Ambient Operating Temperature

+70

+85

+105

°C

Parameter

Test Conditions

Min

Max

Unit

High Level Output Voltage

@ V

DDEXT

= min, I

= 1.0 mA

2.4

Low Level Output Voltage

@ V

DDEXT

= min, I

= 1.0 mA

0.4

4, 5

High Level Input Current

@ V

DDEXT

= max, V

= V

DDEXT

max

µA

Low Level Input Current

@ V

DDEXT

= max, V

= 0 V

µA

ILPU

Low Level Input Current Pullup

@ V

DDEXT

= max, V

= 0 V

200

µA

OZH

6, 7

Three-State Leakage Current

@ V

DDEXT

= max, V

= V

DDEXT

max

µA

OZL

Three-State Leakage Current

@ V

DDEXT

= max, V

= 0 V

µA

OZLPU

Three-State Leakage Current Pullup

@ V

DDEXT

= max, V

= 0 V

200

µA

DD-INTYP

8, 9

Supply Current (Internal)

CCLK

= min, V

DDINT

= nom

500

Supply Current (Analog)

VDD

= max

11,

Input Capacitance

=1 MHz, T

CASE

=25°C, V

=1.2V

4.7

Specifications subject to change without notice.

Applies to output and bidirectional pins: AD150, RD, WR, ALE, FLAG30, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.

See

Output Drive Currents on Page 43

for typical drive current capabilities.

Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.

Applies to input pins with 22.5 k internal pullups: TRST, TMS, TDI.

Applies to three-statable pins: FLAG30.

Applies to three-statable pins with 22.5 k pullups: AD15-0, DAI_Px, SPICLK, EMU, MISO, MOSI.

Typical internal current data reflects nominal operating conditions.

See Engineer-to-Engineer Note (No. TBD) for further information.

Characterized, but not tested.

Applies to all signal pins.

Guaranteed, but not tested.

Rev. PrB

Page 16 of 52

September 2004

ADSP-21364

Preliminary Technical Data

MAXIMUM POWER DISSIPATION

The data in this table is based on theta JA (

) established per

JEDEC standards JESD51-2 and JESD51-6. See Engineer-to-
Engineer note (EE-TBD) for further information. For informa-
tion on package thermal specifications, see

Thermal

Characteristics on Page 44

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

TIMING SPECIFICATIONS

The ADSP-21364's internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the processor's internal clock frequency and
external (CLKIN) clock frequency with the CLKCFG10 pins.

To determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).

The ADSP-21364's internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the processor uses an internal phase-locked loop (PLL).
This PLL-based clocking minimizes the skew between the sys-
tem clock (CLKIN) signal and the processor's internal clock (the
clock source for the parallel port logic and I/O pads).

Max Ambient
Temp

Power Dissipation greater than that listed above may cause permanent damage to the device.

For more information, see Thermal Characteristics on Page 44.

144 INTHS
LQFP

Heat slug soldered to PCB

144 INTHS
LQFP

Heat slug not soldered to PCB

136 Mini-
BGA

Thermal vias in PCB

136 Mini-
BGA

No thermal vias in PCB

°C

3.33W

2.10W

2.44W

2.18W

°C

2.42W

N/A

1.77W

N/A

105

°C

1.21W

N/A

Parameter

Rating

Internal (Core) Supply Voltage (V

DDINT

)

Stresses greater than those listed above may cause permanent damage to the device. These

are stress ratings only; functional operation of the device at these or any other conditions
greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

0.3 V to +1.5 V

Analog (PLL) Supply Voltage (A

VDD

)

0.3 V to +1.5 V

External (I/O) Supply Voltage (V

DDEXT

)

0.3 V to +4.6 V

Input Voltage0.5 V to V

DDEXT

+ 0.5 V

Output Voltage Swing0.5 V to V

DDEXT

+ 0.5 V

Load Capacitance

200 pF

Storage Temperature Range

°C to +150°C

Junction Temperature under Bias

125

°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21364 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 17 of 52

September 2004

Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (

Table 8

Figure 5

shows Core to CLKIN ratios of 6:1, 16:1 and 32:1 with

external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2136x SHARC Processor Programming Reference.

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times. See

Figure 38 on page 43

under Test Conditions for voltage refer-

ence levels.

Switching Characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.

Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

Table 8. ADSP-21364 CLKOUT and CCLK Clock
Generation Operation

Timing
Requirements

Description

Calculation

CLKIN Input

Clock

1/t

CCLK

Core Clock

1/t

CCLK

Table 9. Clock Periods

Timing
Requirements

Description

where:
SR = serial port-to-core clock ratio (wide range, determined by

SPORT CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by
SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock

CLKIN Clock Period

CCLK

(Processor) Core Clock Period

PCLK

(Peripheral) Clock Period = 2 × t

CCLK

SCLK

Serial Port Clock Period = (t

PCLK

) × SR

SPICLK

SPI Clock Period = (t

PCLK

) × SPIR

Figure 5. Core Clock and System Clock Relationship to CLKIN

CLKIN

CCLK
(CORE CLOCK)

PLLILCLK

XTAL

OSC

PLL

6:1, 16:1,

32:1

CLKOUT

CLK-CFG [1:0]

Rev. PrB

Page 18 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Power-Up Sequencing

The timing requirements for processor startup are given in

Table 10

Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)

Parameter

Min

Max

Unit

Timing Requirements

RSTVDD

RESET Low Before V

DDINT

DDEXT

IVDDEVDD

DDINT

on Before V

DDEXT

200

CLKVDD

CLKIN Valid After V

DDINT

DDEXT

Valid

200

CLKRST

CLKIN Valid Before RESET Deasserted

µs

PLLRST

PLL Control Setup Before RESET Deasserted

µs

Switching Characteristic

CORERST

Core Reset Deasserted After RESET Deasserted

4096t

+ 2 t

CCLK

4, 5

Valid V

DDINT

DDEXT

assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds

depending on the design of the power supply subsystem.

Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.

Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.

Based on CLKIN cycles

Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and

propagate default states at all I/O pins.

The 4096 cycle count depends on t

SRST

specification in

Table 12

. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097

cycles maximum.

Figure 6. Power Up Sequencing

CLKIN

RESET

RSTOUT

VDDEXT

VDDINT

PLLRST

CLKRST

CLKVDD

IVDDEVDD

CLK_CFG1-0

CORERST

RSTVDD

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 19 of 52

September 2004

Clock Input

Clock Signals

The ADSP-21364 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21364 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.

Figure 8

shows

the component connections used for a crystal operating in fun-
damental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.

Table 11. Clock Input

Parameter

333 MHz

Unit

Min

Max

Timing Requirements

CLKIN Period

Applies only for CLKCFG10 = 00 and default values for PLL control bits in PMCTL.

TBD

Applies only for CLKCFG10 = 01 and default values for PLL control bits in PMCTL.

CKL

CLKIN Width Low

7.5

TBD

CKH

CLKIN Width High

7.5

TBD

CKRF

CLKIN Rise/Fall (0.4V2.0V)

TBD

CCLK

Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t

CCLK

CCLK Period

3.0

TBD

Figure 7. Clock Input

CLKIN

CKH

CKL

Figure 8. 333 MHz Operation (Fundamental Mode Crystal)

CLKIN

XTAL

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 23 of 52

September 2004

Precision Clock Generator (Direct Pin Routing)

This timing is only valid when the SRU is configured such that
the Precision Clock Generator (PCG) takes its inputs directly
from the DAI pins (via pin buffers) and sends its outputs
directly to the DAI pins. For the other cases, where the PCG's

inputs and outputs are not directly routed to/from DAI pins (via
pin buffers) there is not timing data available. All Timing
Parameters and Switching Characteristics apply to external DAI
pins (DAI_P07 DAI_P20).

Table 18. Precision Clock Generator (Direct Pin Routing)

Parameter

Min

Max

Unit

Timing Requirements

PCGIW

Input Clock Period

STRIG

PCG Trigger Setup Before Falling Edge of PCG Input Clock

HTRIG

PCG Trigger Hold After Falling Edge of PCG Input Clock

Switching Characteristics

DPCGIO

PCG Output Clock and Frame Sync Active Edge Delay After PCG
Input Clock

2.5

DTRIG

PCG Output Clock and Frame Sync Delay After PCG Trigger

2.5 + 2.5 × t

PCGOW

10 + 2.5 × t

PCGOW

Output Clock Period

Figure 15. Precision Clock Generator (Direct Pin Routing)

DAI_PN

PCG_TRIGX_I

STRIG

DAI_PM

PCG_EXTX_I

(CLKIN)

DAI_PY

PCG_CLKX_O

DAI_PZ

PCG_FSX_O

HTRIG

DPCGIO

DTRIG

PCGIW

PCGOW

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 25 of 52

September 2004

Memory Read--Parallel Port

Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21364 is accessing external memory space.

Table 20. 8-Bit Memory Read Cycle

Parameter

Min

Max Unit

Timing Requirements

DRS

Address/Data 70 Setup Before RD High

3.3

DRH

Address/Data 70 Hold After RD High

DAD

Address 158 to Data Valid

D + t

PCLK

Switching Characteristics

ALEW

ALE Pulse Width

2 × t

PCLK

2.0

ADAS

Address/Data 150 Setup Before ALE Deasserted

PCLK

2.5

RRH

Delay Between RD Rising Edge to Next Falling Edge.

H + t

PCLK

ALERW

ALE Deasserted to Read Asserted

2 × t

PCLK

RWALE

Read Deasserted to ALE Asserted

F + H + 0.5

ADAH

Address/Data 150 Hold After ALE Deasserted

PCLK

0.8

ALEHZ

ALE Deasserted to Address/Data70 in High Z

PCLK

0.8

PCLK

RD Pulse Width

D 2

RDDRV

RD Address Drive After Read High

F + H + t

PCLK

ADRH

Address/Data 158 Hold After RD High

D = (Data Cycle Duration = the value set by the PPDUR bits (51) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set else F = 0)

PCLK

= (Peripheral) Clock Period = 2 × t

CCLK

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 17. Read Cycle For 8-Bit Memory Timing

VALID ADDRESS

VALID

ADDRESS

AD15-8

ADAS

VALID ADDRESS

AD7-0

ALEW

ALE

ADAH

ADRH

DRS

DRH

DAD

ALERW

RWALE

VALID

DATA

VALID

ADDRESS

RDDRV

ALEHZ

VALID ADDRESS

VALID

DATA

RRH

Rev. PrB

Page 26 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Table 21. 16-bit Memory Read Cycle

Parameter

Min

Max Unit

Timing Requirements

DRS

Address/Data 150 Setup Before RD High

3.3

DRH

Address/Data 150 Hold After RD High

Switching Characteristics

ALEW

ALE Pulse Width

2 × t

PCLK

ADAS

Address/Data 150 Setup Before ALE Deasserted

PCLK

2.5

ALERW

ALE Deasserted to Read Asserted

2 × t

PCLK

RRH

Delay Between RD Rising Edge to Next Falling Edge.

H + t

PCLK

RWALE

Read Deasserted to ALE Asserted

F + H + 0.5

RDDRV

RD Address Drive After Read High

F + H + t

PCLK

ADAH

Address/Data 150 Hold After ALE Deasserted

PCLK

0.8

ALEHZ

ALE Deasserted to Address/Data150 in High Z

PCLK

0.8

RD Pulse Width

D 2

D = (Data Cycle Duration = the value set by the PPDUR bits (51) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set else F = 0)

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 18. Read Cycle For 16-Bit Memory Timing

AD15-0

DRS

DRH

RDDRV

ALEHZ

ADAH

ADAS

VALID ADDRESS

VALID DATA

VALID

ADDRESS

ALEW

ALERW

RW ALE

RRH

ALE

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 27 of 52

September 2004

Memory Write--Parallel Port

Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21364 is accessing external memory space.

Table 22. 8-bit Memory Write Cycle

Parameter

Min

Max Unit

Switching Characteristics:

ALEW

ALE Pulse Width

2 × t

PCLK

ADAS

Address/Data 150 Setup Before ALE Deasserted

PCLK

2.5

ALERW

ALE Deasserted to Read/Write Asserted

2 × t

PCLK

RWALE

Write Deasserted to ALE Asserted

H + 0.5

WRH

Delay Between WR Rising Edge to next WR Falling Edge

F + H + t

PCLK

ADAH

Address/Data 150 Hold After ALE Deasserted

PCLK

0.5

WR Pulse Width

D F 2

ADWL

Address/Data 158 to WR Low

PCLK

1.5

ADWH

Address/Data 158 Hold After WR High

DWS

Address/Data 70 Setup Before WR High

D F + t

PCLK

DWH

Address/Data 70 Hold After WR High

DAWH

Address/Data to WR High

D F + t

PCLK

D = (Data Cycle Duration = the value set by the PPDUR bits (51) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set else F = 0)

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 19. Write Cycle For 8-Bit Memory Timing

AD15-8

VALID

ADDRESS

VALID ADDRESS

ADAS

AD7-0

ALE

ADAH

ADWH

ADWL

VALID DATA

DAWH

WRH

RWALE

VALID

ADDRESS

VALID DATA

ALEW

ALERW

DWS

DWH

VALID ADDRESS

Rev. PrB

Page 28 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Table 23. 16-bit Memory Write Cycle

Parameter

Min

Max Unit

Switching Characteristics

ALEW

ALE Pulse Width

2 × t

PCLK

ADAS

Address/Data 150 Setup Before ALE Deasserted

PCLK

2.5

ALERW

ALE Deasserted to Write Asserted

2 × t

PCLK

RWALE

Write Deasserted to ALE Asserted

H + 0.5

WRH

Delay Between WR Rising Edge to next WR Falling Edge

F + H + t

PCLK

ADAH

Address/Data 150 Hold After ALE Deasserted

PCLK

0.5

WR Pulse Width

D F 2

ALEHZ

ALE Deasserted to Address/Data150 in High Z

PCLK

1.5

DWS

Address/Data 150 Setup Before WR High

D F + t

PCLK

DWH

Address/Data 150 Hold After WR High

D = (Data Cycle Duration = the value set by the PPDUR bits (51) in the PPCTL register) × t

PCLK

H = t

PCLK

(if a hold cycle is specified, else H = 0)

F = 7 x t

PCLK

(if FLASH_MODE is set else F = 0)

On reset, ALE is an active high cycle. However, it can be configured by software to be active low.

Figure 20. Write Cycle For 16-Bit Memory Timing

AD15-0

VALID

ADDRESS

VALID DATA

ADAS

ALE

ADAH

WRH

RWALE

ALEW

ALERW

DWS

DWH

VALID DATA

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 29 of 52

September 2004

Serial Ports

To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.

Serial port signals (SCLK, FS, DxA,/DxB) are routed to the
DAI_P201 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P201 pins.

Table 24. Serial Ports--External Clock

Parameter

Min

Max Unit

Timing Requirements

SFSE

FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)

2.5

HFSE

FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)

2.5

SDRE

Receive Data Setup Before Receive SCLK

2.5

HDRE

Receive Data Hold After SCLK

2.5

SCLKW

SCLK Width

SCLK

SCLK Period

Switching Characteristics

DFSE

FS Delay After SCLK
(Internally Generated FS in either Transmit or Receive Mode)

HOFSE

FS Hold After SCLK
(Internally Generated FS in either Transmit or Receive Mode)

DDTE

Transmit Data Delay After Transmit SCLK

HDTE

Transmit Data Hold After Transmit SCLK

Referenced to sample edge.

Referenced to drive edge.

Table 25. Serial Ports--Internal Clock

Parameter

Min

Max Unit

Timing Requirements

SFSI

FS Setup Before SCLK
(Externally Generated FS in either Transmit or Receive Mode)

HFSI

FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)

2.5

SDRI

Receive Data Setup Before SCLK

HDRI

Receive Data Hold After SCLK

2.5

Switching Characteristics

DFSI

FS Delay After SCLK (Internally Generated FS in Transmit Mode)

HOFSI

FS Hold After SCLK (Internally Generated FS in Transmit Mode)

1.0

DFSI

FS Delay After SCLK (Internally Generated FS in Receive or Mode)

HOFSI

FS Hold After SCLK (Internally Generated FS in Receive Mode)

1.0

DDTI

Transmit Data Delay After SCLK

HDTI

Transmit Data Hold After SCLK

1.0

SCLKIW

Transmit or Receive SCLK Width

0.5t

SCLK

0.5t

SCLK

+ 2

Referenced to the sample edge.

Referenced to drive edge.

Rev. PrB

Page 30 of 52

September 2004

ADSP-21364

Preliminary Technical Data

Table 26. Serial Ports--Enable and Three-State

Parameter

Min

Max Unit

Switching Characteristics

DDTEN

Data Enable from External Transmit SCLK

DDTTE

Data Disable from External Transmit SCLK

DDTIN

Data Enable from Internal Transmit SCLK

Referenced to drive edge.

Table 27. Serial Ports--External Late Frame Sync

Parameter

Min

Max Unit

Switching Characteristics

DDTLFSE

Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0

DDTENFS

Data Enable for MCE = 1, MFD = 0

0.5

The t

DDTLFSE

and t

DDTENFS

parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.

Figure 21. External Late Frame Sync

This figure reflects changes made to support Left-justified Sample Pair mode.

DRIVE

SAMPLE

DRIVE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DRIVE

SAMPLE

DRIVE

LATE EXTERNAL TRANSMIT FS

EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0

1ST BIT

2ND BIT

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

1ST BIT

2ND BIT

HFSE/I

SFSE/I

DDTE/I

DDTENFS

DDTLFSE

HDTE/I

SFSE/I

DDTE/I

DDTENFS

DDTLFSE

HDTE/I

DAI_P20-1

(DATA CHANNEL A/B)

NOTE
SERIAL PORT SIGNALS (SCLK, FS,

DATA CHANNEL A/B

) ARE ROUTED TO THE DAI_P20-1 PINS

USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.

HFSE/I

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 31 of 52

September 2004

Figure 22. Serial Ports

DRIVE EDGE

DAI_P20-1

SCLK (INT)

DRIVE EDGE

SCLK

DAI_P20-1

SCLK (EXT)

DDTTE

DDTEN

DDTIN

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DRIVE EDGE

SAMPLE EDGE

DATA RECEIVE-- INTERNAL CLOCK

DATA RECEIVE-- EXTERNAL CLOCK

DRIVE EDGE

SAMPLE EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

SDRI

HDRI

SFSI

HFSI

DFSI

HOFSI

SCLKIW

SDRE

HDRE

SFSE

HFSE

DFSE

SCLKW

HOFSE

DAI_P20-1

(DATA CHANNEL A/B)

DDTI

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT -- INTERNAL CLOCK

SFSI

HFSI

DFSI

HOFSI

SCLKIW

HDTI

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTE

DRIVE EDGE

SAMPLE EDGE

DATA TRANSMIT -- EXTERNAL CLOCK

SFSE

HFSE

DFSE

HOFSE

SCLKW

HDTE

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

DAI_P20-1

(DATA CHANNEL A/B)

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 33 of 52

September 2004

Parallel Data Acquisition Port (PDAP)

The timing requirements for the PDAP are provided in

Table 29

. PDAP is the parallel mode operation of channel 0 of

the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2136x SHARC Processor Hardware Refer-

ence. Note that the most significant 16 bits of external PDAP
data can be provided through either the parallel port AD150 or
the DAI_P205 pins. The remaining 4 bits can only be sourced
through DAI_P41. The timing below is valid at the
DAI_P201 pins or at the AD150 pins.

Table 29. Parallel Data Acquisition Port (PDAP)

Parameter

Min

Max

Unit

Timing Requirements

SPCLKEN

PDAP_CLKEN Setup Before PDAP_CLK Sample Edge

2.5

HPCLKEN

PDAP_CLKEN Hold After PDAP_CLK Sample Edge

2.5

PDSD

PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge

2.5

PDHD

PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge

2.5

PDCLKW

Clock Width

PDCLK

Clock Period

Switching Characteristics

PDHLDD

Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word

2 × t

CCLK

PDSTRB

PDAP Strobe Pulse Width

1 × t

CCLK

Source pins of DATA are ADDR70, DATA70, or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.

Figure 24. PDAP Timing

DAI_P20-1

(PDAP_CLK)

SAMPLE EDGE

PDSD

PDHD

SPCLKEN

HPCLKEN

PDCLKW

DATA

DAI_P20-1

(PDAP_CLKEN)

PDSTRB

PDHLDD

DAI_P20-1

(PDAP_STROBE)

PDCLK

Rev. PrB

Page 36 of 52

September 2004

ADSP-21364

Preliminary Technical Data

SPDIF Transmitter

Serial data input to the SPDIF transmitter can be formatted as
left justified, I

S or right justified with word widths of 16, 18, 20,

or 24 bits. The following sections provide timing for the
transmitter.

SPDIF Transmitter--Serial Input Waveforms

Figure 27

shows the right-justified mode. LRCLK is HI for the

left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output

mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.

Figure 28

shows the default I2S-justified mode. LRCLK is LO

for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.

Figure 29

shows the left-justified mode. LRCLK is HI for the left

channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.

Figure 27. Right-Justified Mode

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB-1

MSB-2

LSB+2 LSB+1

LSB

MSB

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

Figure 28. I

S-Justified Mode

MSB-1

MSB-2

LSB+2 LSB+1

LSB

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

Figure 29. Left-Justified Mode

LRCLK

SCLK

SDATA

LEFT CHANNEL

RIGHT CHANNEL

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

MSB-1

MSB-2

LSB+2

LSB+1

LSB

MSB

MSB+1

MSB

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 37 of 52

September 2004

SPDIF Transmitter Input Data Timing

The timing requirements for the Input port are given in

Table 32

. Input Signals (SCLK, FS, SDATA) are routed to the

DAI_P201 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P201 pins.

Over Sampling Clock (TXCLK) Switching Characteristics

SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the Biphase Clock.

Table 32. SPDIF Transmitter Input Data Timing

Parameter

Min

Max Unit

Timing Requirements

SIFS

FS Setup Before SCLK Rising Edge

SIHFS

FS Hold After SCLK Rising Edge

5.5

SISD

SData Setup Before SCLK Rising Edge

SIHD

SData Hold After SCLK Rising Edge

5.5

SISCLKW

Clock Width

SISCLK

Clock Period

DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.

Figure 30. SPDIF Transmitter Input Timing

DAI_P20-1

(SCLK)

DAI_P20-1

(FS)

SAMPLE EDGE

SISD

SIH D

SISFS

SIHFS

SISCLKW

DAI_P20-1

(SDATA)

Table 33. Over Sampling Clock (TXCLK) Switching Characteristics

Parameter

Min

Max

Unit

TXCLK Frequency for TXCLK = 768 × FS

147.5

MHz

TXCLK Frequency for TXCLK = 512 × FS

98.4

MHz

TXCLK Frequency for TXCLK = 384 × FS

73.8

MHz

TXCLK Frequency for TXCLK = 256 × FS

49.2

MHz

Frame Rate

192.0

MHz

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 39 of 52

September 2004

External PLL Mode

In External PLL Mode internal Digital PLL is disabled and the
receiver runs on the PLL that is connected to the processor
externally. This external PLL generates the 512 x Fs clock
(MCLK) from the reference clock (LRCLK) and gives it to
SPDIF receiver.

Table 35. SPDIF Receiver External PLL Mode Timing

Parameter

Min

Max

Unit

Timing Requirements

MCP

MCLK Period

FMCLK

MCLK Frequency (1/t

MCP

)

100

MHz

BDM

SCLK Propagation Delay from MCLK to the Falling Edge

LDM

LRCLK Propagation Delay From MCLK

DDP

Data Propagation Delay From MCLK

DDS

Data Output Setup To SCLK

1/2 SCLK Period

DDH

Data Output Hold From SCLK

1/2 SCLK Period

Figure 32. SPDIF Receiver External PLL Mode Timing

LDM

BDM

DDS

MSB

DDH

MCLK INPUT

(NOT TO SCALE)

BCLK OUTPUT

LRCLK

OUTPUT

SDATA OUTPUT

I2S-JUSTIFIED

MODE

DDP

DDS

DDH

DDP

MSB

LSB

DDH

DDS

SDATA OUTPUT

RIGHT-JUSTIFIED

MODE

Rev. PrB

Page 40 of 52

September 2004

ADSP-21364

Preliminary Technical Data

SPI Interface--Master

Table 36. SPI Interface Protocol -- Master Switching and Timing Specifications

Parameter

Min

Max Unit

Timing Requirements

SSPIDM

Data Input Valid to SPICLK Edge (Data Input Set-up Time)

HSPIDM

SPICLK Last Sampling Edge to Data Input Not Valid

Switching Characteristics

SPICLKM

Serial Clock Cycle

8 × t

PCLK

SPICHM

Serial Clock High Period

4 × t

PCLK

SPICLM

Serial Clock Low Period

4 × t

PCLK

DDSPIDM

SPICLK Edge to Data Out Valid (Data Out Delay Time)

HDSPIDM

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

SDSCIM

FLAG30IN (SPI Device Select) Low to First SPICLK Edge

4 × t

PCLK

HDSM

Last SPICLK edge to FLAG30IN High

4 × t

PCLK

SPITDM

Sequential Transfer Delay

4 × t

PCLK

Figure 33. SPI Master Timing

LSB

VALID

MSB

VALID

S S P ID M

H S P I D M

HDSPIDM

LSB

MSB

H S S P I D M

D D S P I D M

MOSI

(OUTPUT)

MISO

(INPUT)

FLAG3-0

(OUTPUT)

SPICLK
(CP = 0)

(OUTPUT)

SPICLK
(CP = 1)

(OUTPUT)

S P I C H M

S P I C L M

S P I C L K M

S P I C H M

H D S M

S P I TD M

H D S P I D M

LSB

VALID

LSB

MSB

VALID

H S P I D M

D D S P I D M

MOSI

(OUTPUT)

MISO

(INPUT)

S S P ID M

CPHASE=1

CPHASE=0

S D S C I M

S S P I D M

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 41 of 52

September 2004

SPI Interface--Slave

Table 37. SPI Interface Protocol --Slave Switching and Timing Specifications

Parameter

Min

Max Unit

Timing Requirements

SPICLKS

Serial Clock Cycle

4 × t

PCLK

SPICHS

Serial Clock High Period

2 × t

PCLK

SPICLS

Serial Clock Low Period

2 × t

PCLK

SDSCO

SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1

2 × t

PCLK

2 × t

PCLK

HDS

Last SPICLK Edge to SPIDS Not Asserted, CPHASE = 0

2 × t

PCLK

SSPIDS

Data Input Valid to SPICLK edge (Data Input Set-up Time)

HSPIDS

SPICLK Last Sampling Edge to Data Input Not Valid

SDPPW

SPIDS Deassertion Pulse Width (CPHASE=0)

2 × t

PCLK

Switching Characteristics

DSOE

SPIDS Assertion to Data Out Active

DSDHI

SPIDS Deassertion to Data High Impedance

DDSPIDS

SPICLK Edge to Data Out Valid (Data Out Delay Time)

9.4

HDSPIDS

SPICLK Edge to Data Out Not Valid (Data Out Hold Time)

2 × t

PCLK

DSOV

SPIDS Assertion to Data Out Valid (CPHASE=0)

5 × t

PCLK

Figure 34. SPI Slave Timing

H S P I D S

D D S P I D S

D S D H I

LSB

MSB

MSB VALID

D S O E

D D S P I D S

H D LS B S

MISO

(OUTPUT)

MOSI

(INPUT)

S S P I D S

SPIDS

(INPUT)

SPICLK
(CP = 0)
(INPUT)

SPICLK
(CP = 1)
(INPUT)

S D S C O

S P IC H S

S P I C L S

S P I C L K S

H D S

S P I C H S

S S P I D S

H S P I D S

D S D H I

LSB VALID

MSB

MSB VALID

D S O E

D D S P I D S

MISO

(OUTPUT)

MOSI

(INPUT)

S S P I D S

LSB VALID

LSB

CPHASE=1

CPHASE=0

S D P P W

D S O V

H D L S B S

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 43 of 52

September 2004

OUTPUT DRIVE CURRENTS

Figure 36

shows typical I-V characteristics for the output driv-

ers of the ADSP-21364. The curves represent the current drive
capability of the output drivers as a function of output voltage.

TEST CONDITIONS

The ac signal specifications (timing parameters) appear

Table 12 on Page 20

through

Table 38 on Page 42

. These include

output disable time, output enable time, and capacitive loading.
The timing specifications for the SHARC apply for the voltage
reference levels in

Figure 37

Timing is measured on signals when they cross the 1.5 V level as
described in

Figure 38 on Page 43

. All delays (in nanoseconds)

are measured between the point that the first signal reaches
1.5 V and the point that the second signal reaches 1.5 V.

CAPACITIVE LOADING

Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see

Figure 37

Figure 41

shows graphically

how output delays and holds vary with load capacitance. The
graphs of

Figure 39

Figure 40

, and

Figure 41

may not be linear

outside the ranges shown for Typical Output Delay vs. Load
Capacitance and Typical Output Rise Time (20%-80%, V=Min)
vs. Load Capacitance.

Figure 36. ADSP-21364 Typical Drive

Figure 37. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Figure 38. Voltage Reference Levels for AC Measurements

SWEEP (VDDEXT) VOLTAGE (V)

-20

3.5

0.5

1.5

2.5

-40

-30

-10

(
V

)

(
m

)

VOL

3.11V, 125° C

3.3V, 25° C

3.47V, -45° C

VOH

3.11V, 125° C

3.3V, 25° C

3.47V, -45° C

1.5V

30pF

OUTPUT

PIN

INPUT

OUTPUT

1.5V

Figure 39. Typical Output Rise/Fall Time (20%-80%,

DDEXT

= Max)

Figure 40. Typical Output Fall Time (20%-80%,

DDEXT

= Min)

LOAD CAPACITANCE (pF)

100

250

I
S

I
M

(
n

)

200

150

FALL

y = 0.0467x + 1.6323

y = 0.045x + 1.524

RISE

LOAD CAPACITANCE (pF)

100

150

200

250

I
S

I
M

(
n

)

RISE

FALL

y = 0.049x + 1.5105

y = 0.0482x + 1.4604

Rev. PrB

Page 44 of 52

September 2004

ADSP-21364

Preliminary Technical Data

THERMAL CHARACTERISTICS

The ADSP-21364 processor is rated for performance to a maxi-
mum junction temperature of 125°C.

Table 39

airflow measurements comply with JEDEC standards

JESD51-2 and JESD51-6 and the junction-to-board measure-
ment complies with JESD51-8. Test board and thermal via
design comply with JEDEC standards JESD51-9 (Mini-BGA)
and JESD51-5 (Integrated Heatsink LQFP). The junction-to-
case measurement complies with MIL- STD-883. All measure-
ments use a 2S2P JEDEC test board.

Industrial applications using the Mini-BGA package require
thermal vias, to an embedded ground plane, in the PCB. Refer to
JEDEC Standard JESD51-9 for printed circuit board thermal
ball land and thermal via design information. Industrial applica-
tions using the LQFP package require thermal trace squares and
thermal vias, to an embedded ground plane, in the PCB. The
bottom side heat slug must be soldered to the thermal trace
squares. Refer to JEDEC Standard JESD51-5 for more
information.

To determine the Junction Temperature of the device while on
the application PCB, use:

where:

= Junction temperature ×C

CASE

= Case temperature (×C) measured at the top center of

the package

= Junction-to-Top (of package) characterization parameter

is the Typical value from

Table 39

and

Table 41

= Power dissipation (see EE Note #216)

Values of

are provided for package comparison and PCB

design considerations.

can be used for a first order approxi-

mation of T

by the equation:

where:

= Ambient Temperature

Values of

are provided for package comparison and PCB

design considerations when an external heatsink is required.

Values of

are provided for package comparison and PCB

design considerations.

Figure 41. Typical Output Delay or Hold vs. Load Capacitance

(at Ambient Temperature)

LOAD CAPACITANCE (pF)

200

100

150

(
n

)

-4

-2

Y = 0.0488X - 1.5923

CASE

(

)

Table 39. Thermal Characteristics for 136 Ball Mini-BGA
(No thermal vias in PCB)

Parameter

Condition

Typical

Unit

Airflow = 0 m/s

25.20

°C/W

JMA

Airflow = 1 m/s

21.70

°C/W

JMA

Airflow = 2 m/s

20.80

°C/W

5.00

°C/W

Airflow = 0 m/s

0.140

°C/W

JMT

Airflow = 1 m/s

0.330

°C/W

JMT

Airflow = 2 m/s

0.410

°C/W

Table 40. Thermal Characteristics for 136 Ball Mini-BGA
(Thermal vias in PCB)

Parameter

Condition

Typical

Unit

Airflow = 0 m/s

22.50

°C/W

JMA

Airflow = 1 m/s

19.30

°C/W

JMA

Airflow = 2 m/s

18.40

°C/W

5.00

°C/W

Airflow = 0 m/s

0.130

°C/W

JMT

Airflow = 1 m/s

0.300

°C/W

JMT

Airflow = 2 m/s

0.360

°C/W

Table 41. Thermal Characteristics for 144-Lead Integrated
Heatsink (INTHS) LQFP (With heat slug not soldered to
PCB)

Parameter

Condition

Typical

Unit

Airflow = 0 m/s

26.08

°C/W

JMA

Airflow = 1 m/s

24.59

°C/W

JMA

Airflow = 2 m/s

23.77

°C/W

6.83

°C/W

Airflow = 0 m/s

0.236

°C/W

JMT

Airflow = 1 m/s

0.427

°C/W

JMT

Airflow = 2 m/s

0.441

°C/W

(

)

Rev. PrB

Page 46 of 52

September 2004

ADSP-21364

Preliminary Technical Data

136-BALL BGA PIN CONFIGURATIONS

The following table shows the ADSP-21364's pin names and
their default function after reset (in parentheses).

Table 43. 136-Ball Mini-BGA Pin Assignments

Pin Name

BGA
Pin#

Pin Name

BGA
Pin#

Pin Name

BGA
Pin#

Pin Name

BGA
Pin#

CLKCFG0

A01

CLKCFG1

B01

BOOTCFG1

C01

DDINT

D01

XTAL

A02

GND

B02

BOOTCFG0

C02

GND

D02

TMS

A03

DDEXT

B03

GND

C03

GND

D04

TCK

A04

CLKIN

B04

GND

C12

GND

D05

TDI

A05

TRST

B05

GND

C13

GND

D06

CLKOUT

A06

VSS

B06

DDINT

C14

GND

D09

TDO

A07

VDD

B07

GND

D10

EMU

A08

DDEXT

B08

GND

D11

MOSI

A09

SPICLK

B09

GND

D13

MISO

A10

RESET

B10

DDINT

D14

SPIDS

A11

DDINT

B11

DDINT

A12

GND

B12

GND

A13

GND

B13

GND

A14

GND

B14

DDINT

E01

FLAG1

F01

AD7

G01

AD6

H01

GND

E02

FLAG0

F02

DDINT

G02

DDEXT

H02

GND

E04

GND

F04

DDEXT

G13

DAI_P18 (SD5B)

H13

GND

E05

GND

F05

DAI_P19 (SCLK45)

G14

DAI_P17 (SD5A)

H14

GND

E06

GND

F06

GND

E09

GND

F09

GND

E10

GND

F10

GND

E11

GND

F11

GND

E13

FLAG2

F13

FLAG3

E14

DAI_P20 (SFS45)

F14

ADSP-21364

Preliminary Technical Data

Rev. PrB

Page 49 of 52

September 2004

144-LEAD LQFP PIN CONFIGURATIONS

The following table shows the ADSP-21364's pin names and
their default function after reset (in parentheses).

Table 44. 144-Lead LQFP Pin Assignments

Pin Name

LQFP
Pin No.

Pin Name

LQFP
Pin No.

Pin Name

LQFP
Pin No.

Pin Name

LQFP
Pin No.

DDINT

DDEXT

GND

109

CLKCFG0

GND

DDINT

110

CLKCFG1

DDINT

GND

111

BOOTCFG0

ALE

GND

76 V

DDINT

112

BOOTCFG1

AD15

DAI_P10 (SD2B)

GND

113

GND

AD14

DAI_P11 (SD3A)

DDINT

114

DDEXT

AD13

DAI_P12 (SD3B)

GND

115

GND

44 DAI_P13

(SCLK23)

DDEXT

116

DDINT

DDEXT

DAI_P14 (SFS23)

GND

117

GND

AD12

DAI_P15 (SD4A)

DDINT

118

DDINT

GND

119

GND

DDINT

120

DDINT

AD11

GND

RESET

121

GND

AD10

DAI_P16 (SD4B)

SPIDS

122

FLAG0

AD9

DAI_P17 (SD5A)

GND

123

FLAG1

AD8

DAI_P18 (SD5B)

DDINT

124

AD7

DAI_P1 (SD0A) 53

DAI_P19 (SCLK45)

SPICLK

125

GND

18 V

DDINT

MISO

126

DDINT

GND

55 GND

MOSI

127

GND

DAI_P2 (SD0B) 56

GND

128

DDEXT

DAI_P3 (SCLK0) 57

DDEXT

DDINT

129

GND

DAI_P20 (SFS45)

DDEXT

130

DDINT

DDEXT

GND

VDD

131

AD6

DDINT

VSS

132

AD5

GND

FLAG2

GND

133

AD4

DAI_P4 (SFS0)

FLAG3

CLKOUT

134

DDINT

DAI_P5 (SD1A) 63

DDINT

EMU

135

GND

DAI_P6 (SD1B) 64

GND

100

TDO

136

AD3

DAI_P7 (SCLK1) 65

DDINT

101

TDI

137

AD2

DDINT

GND

102

TRST

138

DDEXT

GND

DDINT

103

TCK

139

GND

DDINT

GND

104

TMS

140

AD1

GND

69 V

DDINT

105

GND

141

AD0

DAI_P8 (SFS1)

GND

106

CLKIN

142

DAI_P9 (SD2A) 71

DDINT

107

XTAL

143

DDINT

108

DDEXT

144

Rev. PrB

Page 52 of 52

September 2004

ADSP-21364

Preliminary Technical Data

ORDERING GUIDE

Analog Devices offers a wide variety of audio algorithms and combinations to run on the ADSP-21364 processor. These products are sold
as part of a chip set, bundled with necessary application software under special part numbers. For a complete list, visit our web site at

www.analog.com/SHARC

These products also may contain 3rd party IPs that may require users to have authorization from the respective IP holders to receive them.
Royalty for use of the 3rd party IPs may also be payable by users.

Part Number

Z indicates Lead Free package. For more information about lead free package offerings, please visit www.analog.com.

See

Thermal Characteristics on Page 44

for information on package thermal specifications.

See EngineertoEngineer Note (EE TBD) for further information.

Ambient
Temperature
Range

°C

Instruction
Rate

On-Chip
SRAM

ROM

Operating Voltage
Internal/External
Volts

Package

ADSP-21364SKBCZENG

0 to 70

333MHz

3M bit

4M bit

1.2/3.3

136 Mini-BGA Pb-free

ADSP-21364SKBC-ENG

0 to 70

333MHz

3M bit

4M bit

1.2/3.3

136 Mini-BGA

ADSP-21364SKSQZENG

0 to 70

333MHz

3M bit

4M bit

1.2/3.3

144 INTHS LQFP Pb-free

ADSP-21364SKSQ-ENG

0 to 70

333MHz

3M bit

4M bit

1.2/3.3

144 INTHS LQFP

ADSP-21364SBBCZENG

PCB must have thermal vias. See

Thermal Characteristics on Page 44

. For more information see JEDEC Standard JESD51-9.

40 to 85

333MHz

3M bit

4M bit

1.2/3.3

136 Mini-BGA Pb-free

ADSP-21364SBBC-ENG

40 to 85

333MHz

3M bit

4M bit

1.2/3.3

136 Mini-BGA

ADSP-21364SBSQZENG

Heat slug must be soldered to the PCB. See

Thermal Characteristics on Page 44

. For more information see JEDEC Standard JESD51-5.

40 to 85

333MHz

3M bit

4M bit

1.2/3.3

144 INTHS LQFP Pb-free

ADSP-21364SBSQ-ENG

40 to 85

333MHz

3M bit

4M bit

1.2/3.3

144 INTHS LQFP

ADSP-21364SCSQZENG

40 to 105

200MHz

3M bit

4M bit

1.0/3.3

144 INTHS LQFP Pb-free

ADSP-21364SCSQ-ENG

40 to 105

200MHz

3M bit

4M bit

1.0/3.3

144 INTHS LQFP

PR04624-0-10/04(PrB)

Document Outline

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Document Outline

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