FUNCTIONAL BLOCK DIAGRAM

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADSP-2100 Family

DSP Microcomputers

ADSP-21xx

SUMMARY
16-Bit Fixed-Point DSP Microprocessors with

On-Chip Memory

Enhanced Harvard Architecture for Three-Bus

Performance: Instruction Bus & Dual Data Buses

Independent Computation Units: ALU, Multiplier/

Accumulator, and Shifter

Single-Cycle Instruction Execution & Multifunction

Instructions

On-Chip Program Memory RAM or ROM

& Data Memory RAM

Integrated I/O Peripherals: Serial Ports, Timer,

Host Interface Port (ADSP-2111 Only)

FEATURES
25 MIPS, 40 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data

(Three-Bus Performance)

Dual Data Address Generators with Modulo and

Bit-Reverse Addressing

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory (e.g., EPROM )

Double-Buffered Serial Ports with Companding Hardware,

Automatic Data Buffering, and Multichannel Operation

ADSP-2111 Host Interface Port Provides Easy Interface

to 68000, 80C51, ADSP-21xx, Etc.

Automatic Booting of ADSP-2111 Program Memory

Through Host Interface Port

Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PGA, PLCC, PQFP, and TQFP Packages
MIL-STD-883B Versions Available

This data sheet describes the following ADSP-2100 Family
processors:

ADSP-2101
ADSP-2103

3.3 V Version of ADSP-2101

ADSP-2105

Low Cost DSP

ADSP-2111

DSP with Host Interface Port

ADSP-2115
ADSP-2161/62/63/64

Custom ROM-programmed DSPs

The following ADSP-2100 Family processors are not included
in this data sheet:

ADSP-2100A

DSP Microprocessor

ADSP-2165/66

ROM-programmed ADSP-216x processors

with powerdown and larger on-chip
memories (12K Program Memory ROM,
1K Program Memory RAM, 4K Data
Memory RAM)

ADSP-21msp5x

Mixed-Signal DSP Processors with

integrated on-chip A/D and D/A plus
powerdown

ADSP-2171

Speed and feature enhanced ADSP-2100

Family processor with host interface port,
powerdown, and instruction set extensions
for bit manipulation, multiplication, biased
rounding, and global interrupt masking

ADSP-2181

ADSP-21xx processor with ADSP-2171

features plus 80K bytes of on-chip RAM
configured as 16K words of program
memory and 16K words of data memory.

Refer to the individual data sheet of each of these processors for
further information.

GENERAL DESCRIPTION

The ADSP-2100 Family processors are single-chip micro-
computers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-21xx processors are all built upon a common core. Each
processor combines the core DSP architecture--computation
units, data address generators, and program sequencer--with
differentiating features such as on-chip program and data
memory RAM, a programmable timer, one or two serial ports,
and, on the ADSP-2111, a host interface port.

EXTERNAL

ADDRESS

BUS

DATA

MEMORY

PROGRAM

MEMORY

EXTERNAL

DATA

BUS

ADSP-2100 CORE

ARITHMETIC UNITS

SHIFTER

MAC

ALU

MEMORY

SERIAL PORTS

SPORT 0

SPORT 1

HOST

INTERFACE

PORT

(ADSP-2111)

FLAGS

(ADSP-2111)

DATA ADDRESS

GENERATORS

DAG 1

DAG 2

PROGRAM

SEQUENCER

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

TIMER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

ADSP-21xx

REV. B

Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-21xx proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.

The ADSP-2100 Family's flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-21xx can perform all of the following
operations:

Generate the next program address

Fetch the next instruction

Perform one or two data moves

Update one or two data address pointers

Perform a computation

Receive and transmit data via one or two serial ports

Receive and/or transmit data via the host interface port
(ADSP-2111 only)

The ADSP-2101, ADSP-2105, and ADSP-2115 comprise the
basic set of processors of the family. Each of these three devices
contains program and data memory RAM, an interval timer,
and one or two serial ports. The ADSP-2103 is a 3.3 volt
power supply version of the ADSP-2101; it is identical to the
ADSP-2101 in all other characteristics. Table I shows the
features of each ADSP-21xx processor.

The ADSP-2111 adds a 16-bit host interface port (HIP) to the
basic set of ADSP-21xx integrated features. The host port
provides a simple interface to host microprocessors or
microcontrollers such as the 8031, 68000, or ISA bus.

TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 4
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . . 6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . 13
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Procedure for ADSP-216x ROM Processors . . . . 13
Wafer Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional Differences for Older Revision Devices . . . . . . 14
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

SPECIFICATIONS

(ADSP-2101/2105/2115/2161/2163) . . . . . . . . . . . . . . . 17

Recommended Operating Conditions . . . . . . . . . . . . . . . . 17
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply Current & Power (ADSP-2101/2161/2163) . . . . . . 18
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 19
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 19
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SPECIFICATIONS

(ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Recommended Operating Conditions . . . . . . . . . . . . . . . . 21
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 23
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 23

Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SPECIFICATIONS (ADSP-2103/2162/2164) . . . . . . . . . 25
Recommended Operating Conditions . . . . . . . . . . . . . . . . 25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . . 27
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

TIMING PARAMETERS

(ADSP-2101/2105/2111/2115/2161/2163) . . . . . . . . . . . . 29

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bus RequestBus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Host Interface Port (ADSP-2111) . . . . . . . . . . . . . . . . . . . 36

TIMING PARAMETERS (ADSP-2103/2162/2164) . . . . 44
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Bus RequestBus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PIN CONFIGURATIONS
68-Pin PGA (ADSP-2101) . . . . . . . . . . . . . . . . . . . . . . . . 51
68-Lead PLCC (ADSP-2101/2103/2105/2115/216x) . . . . 52
80-Lead PQFP (ADSP-2101/2103/2115/216x) . . . . . . . . . 53
80-Lead TQFP (ADSP-2115) . . . . . . . . . . . . . . . . . . . . . . 53
100-Pin PGA (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . . . 54
100-Lead PQFP (ADSP-2111) . . . . . . . . . . . . . . . . . . . . . 55

PACKAGE OUTLINE DIMENSIONS
68-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
80-Lead PQFP, 80-Lead TQFP . . . . . . . . . . . . . . . . . . . . 58
100-Pin PGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
100-Lead PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . 61-62

ADSP-21xx

REV. B

Table I. ADSP-21xx Processor Features

Feature

2101

2103

2105

2115

2111

Data Memory (RAM)

Program Memory (RAM)

Timer

Serial Port 0 (Multichannel)

Serial Port 1

Host Interface Port

Speed Grades (Instruction Cycle Time)

10.24 MHz (76.9 ns)

13.0 MHz (76.9 ns)

13.824 MHz (72.3 ns)

16.67 MHz (60 ns)

20.0 MHz (50 ns)

25 MHz (40 ns)

Supply Voltage

5 V

3.3 V

5 V

Packages

68-Pin PGA

68-Lead PLCC

80-Lead PQFP

80-Lead TQFP

100-Pin PGA

100-Lead PQFP

Temperature Grades

K Commercial 0

C to +70

B Industrial

C to +85

T Extended

C to +125

Table II. ADSP-216x ROM-Programmed Processor Features

Feature

2161

2162

2163

2164

Data Memory (RAM)

Program Memory (ROM)

Program Memory (RAM)

Timer

Serial Port 0 (Multichannel)

Serial Port 1

Supply Voltage

5 V

3.3 V

5 V

3.3 V

Speed Grades (Instruction Cycle Time)

10.24 MHz (97.6 ns)

16.67 MHz (60 ns)

25 MHz (40 ns)

Packages

68-Lead PLCC

80-Lead PQFP

Temperature Grades

K Commercial 0

C to +70

B Industrial

C to +85

ADSP-21xx

REV. B

The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table II shows the features available in the ADSP-216x series of
custom ROM-coded processors.

The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.

Development Tools

The ADSP-21xx processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Devel-
opment Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-21xx
processors. The ANSI C compiler generates ADSP-21xx
assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. The ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators
provide an interactive instruction-level simulation with a
reconfigurable, windowed user interface. A PROM splitter
utility generates PROM programmer compatible files.

EZ-ICE

in-circuit emulators allow debugging of ADSP-21xx

systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB

demonstration boards are complete DSP

systems that execute EPROM-based programs.

The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.

Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.

Additional Information

This data sheet provides a general overview of ADSP-21xx
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User's Manual, available from Analog Devices.

ARCHITECTURE OVERVIEW

Figure 1 shows a block diagram of the ADSP-21xx architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract
operations. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control including multiword floating-point representations.

The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-21xx executes looped code with zero
overhead--no explicit jump instructions are required to
maintain the loop.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.

Efficient data transfer is achieved with the use of five internal
buses:

· Program Memory Address (PMA) Bus
· Program Memory Data (PMD) Bus
· Data Memory Address (DMA) Bus
· Data Memory Data (DMD) Bus
· Result (R) Bus

The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space is using the external buses.

Program memory can store both instructions and data, permit-
ting the ADSP-21xx to fetch two operands in a single cycle, one
from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.

The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor's buses with
the use of the bus request/grant signals (BR, BG).

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.

ADSP-21xx

REV. B

Figure 1. ADSP-21xx Block Diagram

One bus grant execution mode (GO Mode) allows the ADSP-
21xx to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.

Each ADSP-21xx processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer, serial ports, and, on the ADSP-2111,
the host interface port. There is also a master RESET signal.

Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, a 60 ns ADSP-2101 to use a 200 ns EPROM as
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.

The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device. The ADSP-2111 has three
additional flag outputs whose states are controlled through
software.

A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-21xx processors include two synchronous serial
ports ("SPORTs") for serial communications and multiproces-
sor communication. All of the ADSP-21xx processors have two
serial ports (SPORT0, SPORT1) except for the ADSP-2105,
which has only SPORT1.

The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.

Each serial port has a 5-pin interface consisting of the following
signals:

Signal Name

Function

SCLK

Serial Clock (I/O)

RFS

Receive Frame Synchronization (I/O)

TFS

Transmit Frame Synchronization (I/O)

Serial Data Receive

Serial Data Transmit

The ADSP-21xx serial ports offer the following capabilities:

Bidirectional--Each SPORT has a separate, double-buffered
transmit and receive function.

Flexible Clocking--Each SPORT can use an external serial
clock or generate its own clock internally.

R Bus

DMD BUS

HOST
PORT

CONTROL

PMD BUS

DMA BUS

PMA BUS

EXTERNAL
ADDRESS
BUS

EXTERNAL
DATA
BUS

HOST
PORT
DATA

BOOT

ADDRESS

GENERATOR

TIMER

BUS

EXCHANGE

COMPANDING

CIRCUITRY

RECEIVE REG

TRANSMIT REG

SERIAL

PORT 1

EXTERNAL

HOST PORT

BUS

DMA BUS

PMA BUS

DMD BUS

PMD BUS

HOST INTERFACE PORT

(ADSP-2111 Only)

FLAGS

(ADSP-2111 Only)

PROGRAM

SEQUENCER

INSTRUCTION

REGISTER

PROGRAM

MEMORY

SRAM

or ROM

DATA

MEMORY

SRAM

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

INPUT REGS

OUTPUT REGS

SHIFTER

INPUT REGS

OUTPUT REGS

MAC

INPUT REGS

OUTPUT REGS

ALU

RECEIVE REG

TRANSMIT REG

SERIAL
PORT 0

(Not on ADSP-2105)

MUX

ADSP-21xx

REV. B

of the ADSP-2111. The two status registers provide status
information to both the ADSP-2111 and the host processor.
HSR7 contains a software reset bit which can be set by both the
ADSP-2111 and the host.

HIP transfers can be managed using either interrupts or polling.
The HIP generates an interrupt whenever an HDR register
receives data from a host processor write. It also generates an
interrupt when the host processor has performed a successful
read of any HDR. The read/write status of the HDRs is also
stored in the HSR registers.

The HMASK register bits can be used to mask the generation of
read or write interrupts from individual HDR registers. Bits in
the IMASK register enable and disable all HIP read interrupts
or all HIP write interrupts. So, for example, a write to HDR4
will cause an interrupt only if both the HDR4 Write bit in
HMASK and the HIP Write interrupt enable bit in IMASK are
set.

The HIP provides a second method of booting the ADSP-2111
in which the host processor loads instructions into the HIP. The
ADSP-2111 automatically transfers the data, in this case
opcodes, to internal program memory. The BMODE pin
determines whether the ADSP-2111 boots from the host
processor through the HIP or from external EPROM over the
data bus.

Interrupts

The ADSP-21xx's interrupt controller lets the processor
respond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1, and IRQ2, are
provided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0

may be alternately configured as part of Serial Port 1. The

ADSP-21xx also supports internal interrupts from the timer, the
serial ports, and the host interface port (on the ADSP-2111).
The interrupts are internally prioritized and individually
maskable (except for RESET which is non-maskable). The
IRQx

input pins can be programmed for either level- or edge-

sensitivity. The interrupt priorities for each ADSP-21xx
processor are shown in Table III.

The ADSP-21xx uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instruc-
tions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.

Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.

The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).

Flexible Framing--The SPORTs have independent framing
for the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.

Different Word Lengths--Each SPORT supports serial data
word lengths from 3 to 16 bits.

Companding in Hardware--Each SPORT provides optional
A-law and

-law companding according to CCITT recommen-

dation G.711.

Flexible Interrupt Scheme--Receive and transmit functions
can generate a unique interrupt upon completion of a data word
transfer.

Autobuffering with Single-Cycle Overhead--Each SPORT
can automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.

Multichannel Capability (SPORT0 Only)--SPORT0
provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T1 or CEPT
interfaces, or as a network communication scheme for multiple
processors. (Note that the ADSP-2105 includes only SPORT1,
not SPORT0, and thus does not offer multichannel operation.)

Alternate Configuration--SPORT1 can be alternatively
configured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).

Host Interface Port (ADSP-2111)

The ADSP-2111 includes a Host Interface Port (HIP), a
parallel I/O port that allows easy connection to a host processor.
Through the HIP, the ADSP-2111 can be accessed by the host
processor as a memory-mapped peripheral. The host interface
port can be thought of as an area of dual-ported memory, or
mailbox registers, that allows communication between the
computational core of the ADSP-2111 and the host computer.
The host interface port is completely asynchronous. The host
processor can write data into the HIP while the ADSP-2111 is
operating at full speed.

Three pins configure the HIP for operation with different types
of host processors. The HSIZE pin configures HIP for 8- or 16-
bit communication with the host processor. HMD0 configures
the bus strobes, selecting either separate read and write strobes
or a single read/write select and a host data strobe. HMD1
selects either separate address (3-bit) and data (16-bit) buses or
a multiplexed 16-bit address/data bus with address latch enable.
Tying these pins to appropriate values configures the ADSP-
2111 for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.

The HIP contains six data registers (HDR5-0) and two status
registers (HSR7-6) with an associated HMASK register for
masking interrupts from individual HIP data registers. The HIP
data registers are memory-mapped in the internal data memory

ADSP-21xx

REV. B

The interrupt force and clear register, IFC, is a write-only
register that contains a force bit and a clear bit for each inter-
rupt (except for level-sensitive interrupts and the ADSP-2111
HIP interrupts--these cannot be forced or cleared in software).

When responding to an interrupt, the ASTAT, MSTAT, and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep (nine levels deep on the
ADSP-2111) to allow interrupt nesting. The stack is automati-
cally popped when a return from the interrupt instruction is
executed.

Pin Definitions

Table IV (on next page) shows pin definitions for the ADSP-
21xx processors. Any inputs not used must be tied to V

Table III. Interrupt Vector Addresses & Priority

ADSP-2105
Interrupt

Interrupt

Source

Vector Address

RESET

Startup

0x0000

IRQ2

0x0004 (High Priority)

SPORT1 Transmit or IRQ1

0x0010

SPORT1 Receive or IRQ0

0x0014

Timer

0x0018 (Low Priority)

ADSP-2101/2103/2115/216x
Interrupt

Interrupt

Source

Vector Address

RESET

Startup

0x0000

IRQ2

0x0004 (High Priority)

SPORT0 Transmit

0x0008

SPORT0 Receive

0x000C

SPORT1 Transmit or IRQ1

0x0010

SPORT1 Receive or IRQ0

0x0014

Timer

0x0018 (Low Priority)

ADSP-2111
Interrupt

Interrupt

Source

Vector Address

RESET

Startup

0x0000

IRQ2

0x0004 (High Priority)

HIP Write from Host

0x0008

HIP Read to Host

0x000C

SPORT0 Transmit

0x0010

SPORT0 Receive

0x0014

SPORT1 Transmit or IRQ1

0x0018

SPORT1 Receive or IRQ0

0x001C

Timer

0x0020 (Low Priority)

SYSTEM INTERFACE

Figure 3 shows a typical system for the ADSP-2101, ADSP-
2115, or ADSP-2103, with two serial I/O devices, a boot
EPROM, and optional external program and data memory. A
total of 15K words of data memory and 16K words of program
memory is addressable for the ADSP-2101 and ADSP-2103. A
total of 14.5K words of data memory and 15K words of
program memory is addressable for the ADSP-2115.

Figure 4 shows a system diagram for the ADSP-2105, with one
serial I/O device, a boot EPROM, and optional external
program and data memory. A total of 14.5K words of data
memory and 15K words of program memory is addressable for
the ADSP-2105.

Figure 5 shows a system diagram for the ADSP-2111, with two
serial I/O devices, a host processor, a boot EPROM, and
optional external program and data memory. A total of 15K
words of data memory and 16K words of program memory is
addressable.

Programmable wait-state generation allows the processors to
easily interface to slow external memories.

The ADSP-2101, ADSP-2103, ADSP-2115, and ADSP-2111
processors also provide either: one external interrupt (IRQ2)
and two serial ports (SPORT0, SPORT1), or three external
interrupts (IRQ2, IRQ1, IRQ0) and one serial port (SPORT0).

The ADSP-2105 provides either: one external interrupt (IRQ2)
and one serial port (SPORT1), or three external interrupts
(IRQ2, IRQ1, IRQ0) with no serial port.

Clock Signals

The ADSP-21xx processors' CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.

If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor's CLKIN input; in this case, the
XTAL input must be left unconnected.

Because the ADSP-21xx processors include an on-chip oscilla-
tor circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallel-
resonant, fundamental frequency, microprocessor-grade crystal
should be used.

Figure 2. External Crystal Connections

CLKIN

CLKOUT

XTAL

ADSP-21xx

ADSP-21xx

REV. B

A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor's internal cycles.

Reset

The RESET

signal initiates a complete reset of the ADSP-21xx.

The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor's internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor's internal clock continues and does
not require this stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 t

cycles will ensure that the PLL has locked (this does

not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, t

RSP

To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)

Table IV. ADSP-21xx Pin Definitions

Pin

# of

Input /

Name(s)

Pins

Output

Function

Address

Address outputs for program, data and boot memory.

Data

I/O

Data I/O pins for program and data memories. Input only for
boot memory, with two MSBs used for boot memory addresses.
Unused data lines may be left floating.

RESET

Processor Reset Input

IRQ2

External Interrupt Request #2

External Bus Request Input

External Bus Grant Output

PMS

External Program Memory Select

DMS

External Data Memory Select

BMS

Boot Memory Select

External Memory Read Enable

External Memory Write Enable

MMAP

Memory Map Select Input

CLKIN, XTAL

External Clock or Quartz Crystal Input

CLKOUT

Processor Clock Output

Power Supply Pins

GND

Ground Pins

SPORT0

I/O

Serial Port 0 Pins (TFS0, RFS0, DT0, DR0, SCLK0)

SPORT1

I/O

Serial Port 1 Pins (TFS1, RFS1, DT1, DR1, SCLK1)

or Interrupts & Flags:

IRQ0

(RFS1)

External Interrupt Request #0

IRQ1

(TFS1)

External Interrupt Request #1

FI (DR1)

Flag Input Pin

FO (DT1)

Flag Output Pin

FL20 (ADSP-2111 Only)

General Purpose Flag Output Pins

Host Interface Port
(ADSP-2111 Only)
HSEL

HIP Select Input

HACK

HIP Acknowledge Output

HSIZE

8/16-Bit Host Select (0 = 16-Bit, 1 = 8-Bit)

BMODE

Boot Mode Select (0 = Standard EPROM Booting, 1 = HIP Booting)

HMD0

Bus Strobe Select (0 = RD/WR, 1 = RW/DS)

HMD1

HIP Address/Data Mode Select (0 = Separate, 1 = Multiplexed)

HRD

/HRW

HIP Read Strobe or Read/Write Select

HWR

/HDS

HIP Write Strobe or Host Data Strobe Select

HD150/HAD15-0

I/O

HIP Data or HIP Data and Address

HA2/ALE

Host Address 2 Input or Address Latch Enable Input

HA10/Unused

Host Address 1 and 0 Inputs

NOTES

Unused data bus lines may be left floating.

must be tied high (to V

) if not used.

ADSP-2105 does not have SPORT0. (SPORT0 pins are No Connects on the ADSP-2105.)

ADSP-21xx

REV. B

Figure 4. ADSP-2105 System

Figure 3. ADSP-2101/ADSP-2103/ADSP-2115 System

CLKIN

RESET

IRQ2

BMS

ADSP-2101

ADSP-2103

ADSP-2115

CLKOUT

ADDR

DATA

(OPTIONAL)

1x CLOCK

CRYSTAL

PMS

DMS

ADDR

13-0

DATA

23-0

ADDR

DATA

(OPTIONAL)

ADDR

DATA

BOOT

MEMORY

e.g. EPROM

2764

27128
27256
27512

PROGRAM

MEMORY

DATA

MEMORY

PERIPHERALS

23-22

13-0

15-8

23-0

23-8

13-0

XTAL

MMAP

SERIAL
DEVICE

(OPTIONAL)

SCLK1
RFS1

or IRQ0

TFS1

or IRQ1

DT1

or FO

DR1

or FI

SPORT 1

SCLK0
RFS0
TFS0
DT0
DR0

SPORT 0

SERIAL
DEVICE

(OPTIONAL)

THE TWO MSBs OF THE DATA BUS (D

23-22

) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

CLKIN

RESET

IRQ2

BMS

ADSP-2105

CLKOUT

ADDR

DATA

(OPTIONAL)

1x CLOCK

CRYSTAL

PMS

DMS

ADDR

13-0

DATA

23-0

ADDR

DATA

(OPTIONAL)

ADDR

DATA

BOOT

MEMORY

e.g. EPROM

2764

27128
27256
27512

PROGRAM

MEMORY

DATA

MEMORY

PERIPHERALS

23-22

13-0

15-8

23-0

23-8

13-0

XTAL

MMAP

SERIAL
DEVICE

(OPTIONAL)

SCLK1
RFS1

or IRQ0

TFS1

or IRQ1

DT1

or FO

DR1

or FI

SPORT 1

THE TWO MSBs OF THE DATA BUS (D

23-22

) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

ADSP-21xx

REV. B

Figure 5. ADSP-2111 System

The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). The first
instruction is then fetched from internal program memory
location 0x0000.

Program Memory Interface

The on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.

The external address bus is 14 bits wide. For the ADSP-2101,
ADSP-2103, and ADSP-2111, these lines can directly address
up to 16K words, of which 2K are on-chip. For the ADSP-2105
and ADSP-2115, the address lines can directly address up to
15K words, of which 1K is on-chip.

The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.

The ADSP-21xx processors write data from their 16-bit
registers to 24-bit program memory using the PX register to
provide the lower eight bits. When the processor reads 16-bit
data from 24-bit program memory to a 16-bit data register, the
lower eight bits are placed in the PX register.

The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET

Program Memory Maps

Program memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 6 shows the two program
memory maps for the ADSP-2101, ADSP-2103, and
ADSP-2111. Figure 8 shows the program memory maps for the
ADSP-2105 and ADSP-2115. Figures 7 and 9 show the
program memory maps for the ADSP-2161/62 and ADSP-2163/
64, respectively.

CLKIN

RESET

IRQ2

BMS

CLKOUT

ADDR

DATA

(OPTIONAL)

1x CLOCK

CRYSTAL

PMS

DMS

ADDR

13-0

DATA

23-0

ADDR

DATA

(OPTIONAL)

ADDR

DATA

BOOT

MEMORY

e.g. EPROM

2764

27128
27256
27512

PROGRAM

MEMORY

DATA

MEMORY

PERIPHERALS

23-22

13-0

15-8

23-0

23-8

13-0

XTAL

MMAP

SERIAL
DEVICE

(OPTIONAL)

SCLK1
RFS1

IRQ0

TFS1

IRQ1

DT1

DR1

SPORT 1

SCLK0
RFS0
TFS0
DT0
DR0

SPORT 0

SERIAL
DEVICE

(OPTIONAL)

ADSP-2111

HOST

PROCESSOR

(OPTIONAL)

HOST INTERFACE PORT

CONTROL

DATA / ADDR

(OPTIONAL)

FL0
FL1
FL2

THE TWO MSBs OF THE DATA BUS (D

23-22

) ARE USED TO SUPPLY THE TWO MSBs OF THE

BOOT MEMORY EPROM ADDRESS. THIS IS ONLY REQUIRED FOR THE 27256 AND 27512.

ADSP-21xx

REV. B

ADSP-2101/ADSP-2103/ADSP-2111

When MMAP = 0, on-chip program memory RAM occupies
2K words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configurationwhen MMAP = 0the boot
loading sequence (described below in "Boot Memory Inter-
face") is automatically initiated when RESET is released.

When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the upper 2K words, beginning at address 0x3800. In
this configuration, program memory is not booted although it
can be written to and read under program control.

ADSP-2105/ADSP-2115

When MMAP = 0, on-chip program memory RAM occupies
1K words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configurationwhen MMAP = 0the boot
loading sequence (described below in "Boot Memory Inter-
face") is automatically initiated when RESET is released.

When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
located in the 1K words between addresses 0x38000x3BFF. In
this configuration, program memory is not booted although it
can be written to and read under program control.

INTERNAL

RAM

LOADED FROM

EXTERNAL

BOOT MEMORY

EXTERNAL

0x07FF
0x0800

0x3FFF

0x0000

EXTERNAL

No Booting

0x37FF
0x3800

0x3FFF

0x0000

MMAP=0

MMAP=1

INTERNAL

RAM

14K

Figure 6. ADSP-2101/ADSP-2103/ADSP-2111 Program
Memory Maps

Figure 8. ADSP-2105/ADSP-2115 Program Memory Maps

Figure 7. ADSP-2161/62 Program Memory Maps

Figure 9. ADSP-2163/64 Program Memory Maps

0x07FF
0x0800

0x1FF0

0x1FFF
0x2000

0x1FF0

0x1FFF
0x2000

MMAP=0

0x3FFF

0x0000

EXTERNAL

INTERNAL

ROM

0x0000

MMAP=1

0x3FFF

0x3800

0x37FF

EXTERNAL

INTERNAL

ROM

EXTERNAL

INTERNAL

ROM

RESERVED

INTERNAL RAM

LOADED FROM

EXTERNAL

BOOT MEMORY

EXTERNAL

0x03FF
0x0400

0x3FFF

0x0000

EXTERNAL

0x3BFF
0x3C00

0x3FFF

0x0000

MMAP=0

MMAP=1

No Booting

0x37FF
0x3800

0x07FF
0x0800

RESERVED

14K

INTERNAL RAM

RESERVED

INTERNAL

ROM

12K

EXTERNAL

0x3FFF

0x0000

EXTERNAL

0x3FFF

0x0000

MMAP=0

MMAP=1

0x37FF
0x3800

INTERNAL

ROM

INTERNAL

ROM

10K

EXTERNAL

0x07FF
0x0800

0x0FF0

0x0FFF
0x1000

0x0FF0

RESERVED

0x0FFF
0x1000

ADSP-21xx

REV. B

All Processors

The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.

Boot Memory Interface

On the ADSP-2101, ADSP-2103, and ADSP-2111, boot
memory is an external 64K by 8 space, divided into eight
separate 8K by 8 pages. On the ADSP-2105 and ADSP-2115,
boot memory is a 32K by 8 space, divided into eight separate
4K by 8 pages. The 8-bit bytes are automatically packed into
24-bit instruction words by each processor, for loading into on-
chip program memory.

Three bits in the processors' System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.

The boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. This allows
the ADSP-21xx to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.

The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. To accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.

The ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.

The BR signal is recognized during the booting sequence. The
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.

Bus Interface

The ADSP-21xx processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the ADSP-21xx is not performing an external
memory access, it responds to the active BR input in the next
cycle by:

Three-stating the data and address buses and the PMS,

DMS, BMS, RD, WR output drivers,

Asserting the bus grant (BG) signal,

and halting program execution.

If the Go mode is set, however, the ADSP-21xx will not halt
program execution until it encounters an instruction that
requires an external memory access.

Data Memory Interface

The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.

The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.

The ADSP-21xx processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.

Data Memory Map
ADSP-2101/ADSP-2103/ADSP-2111

For the ADSP-2101, ADSP-2103, and ADSP-2111, on-chip
data memory RAM resides in the 1K words beginning at
address 0x3800, as shown in Figure 10. Data memory locations
from 0x3C00 to the end of data memory at 0x3FFF are
reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.

ADSP-2105/ADSP-2115

For the ADSP-2105 and ADSP-2115, on-chip data memory
RAM resides in the 512 words beginning at address 0x3800,
also shown in Figure 10. Data memory locations from 0x3A00
to the end of data memory at 0x3FFF are reserved. Control and
status registers for the system, timer, wait-state configuration,
and serial port operations are located in this region of memory.

Figure 10. Data Memory Map (All Processors)

0x3A00

0x0400

0x0000

1K EXTERNAL

DWAIT0

1K EXTERNAL

DWAIT1

10K EXTERNAL

DWAIT2

1K EXTERNAL

DWAIT3

0x0800

0x3000

512 for ADSP-2105

ADSP-2115
ADSP-216x

EXTERNAL

RAM

INTERNAL

RAM

0x3C00

0x3FFF

1K for ADSP-2101

ADSP-2103
ADSP-2111

MEMORY-MAPPED

CONTROL REGISTERS

& RESERVED

1K EXTERNAL

DWAIT4

0x3400

0x3800

ADSP-21xx

REV. B

If the ADSP-21xx is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces or assert the BG signal until the
cycle after the access completes (up to eight cycles later depend-
ing on the number of wait states). The instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus in between two memory accesses if an instruction
requires more than one external memory access.

When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.

The bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to V

Low Power IDLE Instruction

The IDLE instruction places the ADSP-21xx processor in low
power state in which it waits for an interrupt. When an interrupt
occurs, it is serviced and execution continues with instruction
following IDLE. Typically this next instruction will be a JUMP
back to the IDLE instruction. This implements a low-power
standby loop.

The IDLE n instruction is a special version of IDLE that slows
the processor's internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:

IDLE n;

where n = 16, 32, 64, or 128.

The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor's other
internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.

When the IDLE n instruction is used, it slows the processor's
internal clock and thus its response time to incoming interrupts
the 1-cycle response time of the standard IDLE state is in-
creased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.

When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor's reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).

ADSP-216x Prototyping

You can prototype your ADSP-216x system with either the
ADSP-2101 or ADSP-2103 RAM-based processors. When code
is fully developed and debugged, it can be submitted to Analog

Devices for conversion into a ADSP-216x ROM product.

The ADSP-2101 EZ-ICE emulator can be used for develop-
ment of ADSP-216x systems. For the 3.3 V ADSP-2162 and
ADSP-2164, a voltage converter interface board provides 3.3 V
emulation.

Additional overlay memory is used for emulation of ADSP-
2161/62 systems. It should be noted that due to the use of off-
chip overlay memory to emulate the ADSP-2161/62, a perfor-
mance loss may be experienced when both executing instruc-
tions and fetching program memory data from the off-chip
overlay memory in the same cycle. This can be overcome by
locating program memory data in on-chip memory.

Ordering Procedure for ADSP-216x ROM Processors

To place an order for a custom ROM-coded ADSP-2161,
ADSP-2162, ADSP-2163, or ADSP-2164 processor, you must:

1. Complete the following forms contained in the ADSP ROM

Ordering Package, available from your Analog Devices sales
representative:

ADSP-216x ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products

2. Return the forms to Analog Devices along with two copies of

the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).

3. Place a purchase order with Analog Devices for non-recurring

engineering changes (NRE) associated with ROM product
development.

After this information is received, it is entered into Analog
Devices' ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.

To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.

ADSP-21xx

REV. B

A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.

Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.

There is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.

Package & Speed

Lot # & Revision Code

Date Code

Functional Differences for Older Revision Devices

Older revisions of the ADSP-21xx processors have slight
differences in functionality. The two differences are as follows:

Bus Grant (BG) is asserted in the same cycle that Bus
Request (BR) is recognized (i.e. when setup and hold time
requirements are met for the BR input). Bus Request input is
a synchronous input rather than asynchronous. (In newer
revision devices, BG is asserted in the cycle after BR is
recognized.)

Only the standard IDLE instruction is available, not the
clock-reducing IDLE n instruction.

To determine the revision of a particular ADSP-21xx device,
inspect the marking on the device. For example, an ADSP-2101
of revision 6.0 will have the following marking:

The revision codes for the older versions of each ADSP-21xx
device are as follows:

Processor

Old Functionality

New Functionality

ADSP-2101

Revision Code

5.0

Revision Code

6.0

ADSP-2105

No Revision Code

Revision Code

1.0

ADSP-2115

Revision Code < 1.0

Revision Code

1.0

ADSP-2111

RevisionCode < 2.0

Revision Code

2.0

ADSP-2103

Revision code

5.0

Revision code

6.0

ADSP-2101

KS-66

EE/A12345-6.0

9234

ADSP-21xx

REV. B

Instruction Set

The ADSP-21xx assembly language uses an algebraic syntax for
ease of coding and readability. The sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.

Every instruction assembles into a single 24-bit word and
executes in a single cycle. The instructions encompass a wide
variety of instruction types along with a high degree of

operational parallelism. There are five basic categories of
instructions: data move instructions, computational instruc-
tions, multifunction instructions, program flow control instruc-
tions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.

The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.

ALU Instructions

[IF cond]

AR|AF

xop + yop [+ C] ;

Add/Add with Carry

xop yop [+ C 1] ;

Subtract X Y/Subtract X Y with Borrow

yop xop [+ C 1] ;

Subtract Y X/Subtract Y X with Borrow

xop AND yop ;

AND

xop OR yop ;

xop XOR yop ;

XOR

PASS xop ;

Pass, Clear

xop ;

Negate

NOT xop ;

NOT

ABS xop ;

Absolute Value

yop + 1 ;

Increment

yop 1 ;

Decrement

DIVS yop, xop ;

Divide

DIVQ xop ;

MAC Instructions

[IF cond]

MR|MF =

xop * yop ;

Multiply

MR + xop * yop ;

Multiply/Accumulate

MR xop * yop ;

Multiply/Subtract

MR ;

Transfer MR

0 ;

Clear

IF MV SAT MR ;

Conditional MR Saturation

Shifter Instructions

[IF cond]

SR = [SR OR] ASHIFT xop ;

Arithmetic Shift

[IF cond]

SR = [SR OR] LSHIFT xop ;

Logical Shift

SR = [SR OR] ASHIFT xop BY <exp>;

Arithmetic Shift Immediate

SR = [SR OR] LSHIFT xop BY <exp>;

Logical Shift Immediate

[IF cond]

SE = EXP xop ;

Derive Exponent

[IF cond]

SB = EXPADJ xop ;

Block Exponent Adjust

[IF cond]

SR = [SR OR] NORM xop ;

Normalize

Data Move Instructions

reg = reg ;

Register-to-Register Move

reg = <data> ;

Load Register Immediate

reg = DM (<addr>) ;

Data Memory Read (Direct Address)

dreg = DM (Ix , My) ;

Data Memory Read (Indirect Address)

dreg = PM (Ix , My) ;

Program Memory Read (Indirect Address)

DM (<addr>) = reg ;

Data Memory Write (Direct Address)

DM (Ix , My) = dreg ;

Data Memory Write (Indirect Address)

PM (Ix , My) = dreg ;

Program Memory Write (Indirect Address)

Multifunction Instructions

<ALU>|<MAC>|<SHIFT> , dreg = dreg ;

Computation with Register-to-Register Move

<ALU>|<MAC>|<SHIFT> , dreg = DM (Ix , My) ;

Computation with Memory Read

<ALU>|<MAC>|<SHIFT> , dreg = PM (Ix , My) ;

Computation with Memory Read

DM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;

Computation with Memory Write

PM (Ix , My) = dreg , <ALU>|<MAC>|<SHIFT> ;

Computation with Memory Write

dreg = DM (Ix , My) , dreg = PM (Ix , My) ;

Data & Program Memory Read

<ALU>|<MAC> , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;

ALU/MAC with Data & Program Memory Read

ADSP-21xx

REV. B

Program Flow Instructions

DO <addr> [UNTIL term] ;

Do Until Loop

[IF cond] JUMP (Ix) ;

Jump

[IF cond] JUMP <addr>;
[IF cond] CALL (Ix) ;

Call Subroutine

[IF cond] CALL <addr>;
IF [NOT ] FLAG_IN

JUMP <addr>;

Jump/Call on Flag In Pin

IF [NOT ] FLAG_IN

CALL <addr>;

[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ;

Modify Flag Out Pin

[IF cond] RTS ;

Return from Subroutine

[IF cond] RTI ;

Return from Interrupt Service Routine

IDLE [(n)] ;

Idle

Miscellaneous Instructions

NOP ;

No Operation

MODIFY (Ix , My);

Modify Address Register

[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;

Stack Control

ENA|DIS

SEC_REG [, ...] ;

Mode Control

BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE

Assembly Code Example

The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.

MF=MX0* MY1 ( RND), MX0=DM(I2,M1);

{ MF=error * b eta}

MR=MX0* MF ( RND), AY0=PM(I6,M5);

DO adapt UNTIL CE;

AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);

adapt:

PM(I6,M6)= A R, MR=MX0 * MF ( RND);

MODIFY(I2,M3);

{Point to oldest data}

MODIFY(I6,M7);

{Point to start of data}

Notation Conventions

Index registers for indirect addressing

Modify registers for indirect addressing

<data>

Immediate data value

<addr>

Immediate address value

<exp>

Exponent (shift value) in shift immediate instructions (8-bit signed number)

<ALU>

Any ALU instruction (except divide)

<MAC>

Any multiply-accumulate instruction

<SHIFT>

Any shift instruction (except shift immediate)

cond

Condition code for conditional instruction

term

Termination code for DO UNTIL loop

dreg

Data register (of ALU, MAC, or Shifter)

reg

Any register (including dregs)

;

A semicolon terminates the instruction

Commas separate multiple operations of a single instruction

[ ]

Optional part of instruction

[, ...]

Optional, multiple operations of an instruction

option1 | option2

List of options; choose one.

REV. B

ADSP-2101/2105/2115/2161/2163SPECIFICATIONS

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21xx processors feature proprietary ESD protection circuitry to dissipate high energy
electrostatic discharges (Human Body Model), permanent damage may occur to devices subjected
to such discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts,
and the foam should be discharged to the destination socket before the devices are removed. Per
method 3015 of MIL-STD-883, the ADSP-21xx processors have been classified as Class 1 devices.

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

T Grade

Parameter

Min

Max

Min

Max

Min

Max

Unit

Supply Voltage

4.50

5.50

4.50

5.50

4.50

5.50

AMB

Ambient Operating Temperature

+70

+85

+125

See "Environmental Conditions" for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

Hi-Level Input Voltage

3, 5

@ V

= max

2.0

Hi-Level CLKIN Voltage

@ V

= max

2.2

Lo-Level Input Voltage

1, 3

@ V

= min

0.8

Hi-Level Output Voltage

2, 3, 7

@ V

= min, I

= 0.5 mA

2.4

@ V

= min, I

= 100

0.3

Lo-Level Output Voltage

2, 3, 7

@ V

= min, I

= 2 mA

0.4

Hi-Level Input Current

@ V

= max, V

= V

max

Lo-Level Input Current

@ V

= max, V

= 0 V

OZH

Tristate Leakage Current

@ V

= max, V

= V

max

OZL

Tristate Leakage Current

@ V

= max, V

= 0 V

Input Pin Capacitance

1, 8, 9

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

Output Pin Capacitance

4, 8, 9, 10

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

NOTES

Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).

Output pins: BG, PMS, DMS, BMS, RD, WR, A0A13, CLKOUT, DT1, DT0 (not on ADSP-2105).

Bidirectional pins: D0D23, SCLK1, RFS1, TFS1, SCLK0 (not on ADSP-2105), RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105).

Tristatable pins: A0A13, D0D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0 (not on ADSP-2105), SCLK0 (not on ADSP-2105),
RFS0 (not on ADSP-2105), TFS0 (not on ADSP-2105).

Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0 (not on ADSP-2105).

0 V on BR, CLKIN Active (to force tristate condition).

Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to V

and GND, assuming no dc loads.

Guaranteed but not tested.

Applies to PGA, PLCC, PQFP package types.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range (Ambient) . . . 55ºC to +125ºC
Storage Temperature Range . . . . . . . . . . . . . 65ºC to +150ºC
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . . +300ºC
Lead Temperature (5 sec) PLCC, PQFP, TQFP . . . . +280ºC

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

WARNING!

ESD SENSITIVE DEVICE

ADSP-21xx

ADSP-21xx

REV. B

SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)

SUPPLY CURRENT & POWER (ADSP-2101/2105/2115/2161/2163)

Parameter

Test Conditions

Min

Max

Unit

Supply Current (Dynamic)

@ V

= max, t

= 40 ns

@ V

= max, t

= 50 ns

@ V

= max, t

= 72.3 ns

Supply Current (Idle)

1, 3

@ V

= max, t

= 40 ns

@ V

= max, t

= 50 ns

@ V

= max, t

= 72.3 ns

NOTES

Current reflects device operating with no output loads.

= 0.4 V and 2.4 V.

Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

ADSP-2105 is not available in a 25 MHz speed grade.

For typical supply current (internal power dissipation) figures, see Figure 11.

Figure 11. ADSP-2101 Power (Typical) vs. Frequency

VALID FOR ALL TEMPERATURE GRADES.

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

MAXIMUM POWER DISSIPATION AT V

5.5V DURING EXECUTION OF

IDLE n INSTRUCTION.

POWER mW

30.00

20.00

13.83

10.00

25.00

IDLE 128

IDD IDLE

IDLE 16

51mW

41mW

40mW

64mW

43mW
42mW

FREQUENCY

 MHz

IDD IDLE n MODES

POWER mW

30.00

20.00

13.83

10.00

25.00

140

100

120

160

200

180

220

129mW

100mW

74mW

205mW

157mW

118mW

FREQUENCY

 MHz

IDD DYNAMIC

5.5V

5.0V

4.5V

POWER mW

30.00

20.00

13.83

10.00

25.00

51mW

38mW

28mW

64mW

49mW

35mW

FREQUENCY

 MHz

IDD IDLE

1,2

5.5V

5.0V

4.5V

ADSP-21xx

REV. B

POWER DISSIPATION EXAMPLE

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2101 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the
address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

= 5.0 V and t

= 50 ns.

Total Power Dissipation = P

INT

+ (C

f )

INT

= internal power dissipation (from Figure 11).

f ) is calculated for each output:

# of

Output

Pins

Address, DMS 8

10 pF

20 MHz = 40.0 mW

Data, WR

10 pF

10 MHz = 22.5 mW

10 pF

10 MHz = 2.5 mW

CLKOUT

10 pF

20 MHz = 5.0 mW

70.0 mW

Total power dissipation for this example = P

INT

+ 70.0 mW.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

AMB

= T

CASE

(PD

)

CASE

= Case Temperature in

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

= Thermal Resistance (Junction-to-Ambient)

= Thermal Resistance (Junction-to-Case)

Package

PGA

C/W

PLCC

C/W

PQFP

C/W

TQFP

C/W

SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)

CAPACITIVE LOADING

Figures 12 and 13 show capacitive loading characteristics for the
ADSP-2101, ADSP-2105, ADSP-2115, and ADSP-2161/2163.

 pF

150

125

100

RISE TIME (0.8V - 2.0V) ns

= 4.5V

175

Figure 12. Typical Output Rise Time vs. Load Capacitance, C

(at Maximum Ambient Operating Temperature)

Figure 13. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating Temperature)

 pF

100

125

150

VALID OUTPUT DELAY OR HOLD ns

= 4.5V

175

ADSP-21xx

REV. B

TEST CONDITIONS

Figure 14 shows voltage reference levels for ac measurements.

Figure 14. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t

DIS

) is the difference of t

MEASURED

and

DECAY

, as shown in Figure 15. The time t

MEASURED

is the

interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.

The decay time, t

DECAY

, is dependent on the capacitative load,

, and the current load, i

, on the output pin. It can be

approximated by the following equation:

DECAY

0.5 V

from which

DIS

= t

MEASURED

DECAY

is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

E NA

) is the interval from

when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 15. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.

SPECIFICATIONS (ADSP-2101/2105/2115/2161/2163)

3.0V
1.5V
0.0V

2.0V

1.5V

0.8V

INPUT

OUTPUT

Figure 15. Output Enable/Disable

OUTPUT

PIN

50pF

+1.5V

Figure 16. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.

(MEASURED)

ADSP-2111SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

T Grade

Parameter

Min

Max

Min

Max

Min

Max

Unit

Supply Voltage

4.50

5.50

4.50

5.50

4.50

5.50

AMB

Ambient Operating Temperature

+70

+85

+125

See "Environmental Conditions" for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

Hi-Level Input Voltage

3, 5

@ V

= max

2.0

Hi-Level CLKIN Voltage

@ V

= max

2.2

Lo-Level Input Voltage

1, 3

@ V

= min

0.8

Hi-Level Output Voltage

2, 3, 7

@ V

= min, I

= 0.5 mA

2.4

@ V

= min, I

= 100

0.3

Lo-Level Output Voltage

2, 3, 7

@ V

= min, I

= 2 mA

0.4

Hi-Level Input Current

@ V

= max, V

= V

max

Lo-Level Input Current

@ V

= max, V

= 0V

OZH

Tristate Leakage Curren

@ V

= max, V

= V

max

OZL

Tristate Leakage Current

@ V

= max, V

= 0V

Input Pin Capacitance

1, 8, 9

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

Output Pin Capacitance

4, 8, 9, 10

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

NOTES

Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.

Output pins: BG, PMS, DMS, BMS, RD, WR, A0A13, CLKOUT, DT1, DT0, HACK, FL2-0.

Bidirectional pins: D0D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0, HD0HD15/HAD0HAD15.

Tristatable pins: A0A13, D0D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0, HD0HD15/HAD0HAD15.

Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HRW, HWR/HDS, HA2/ALE, HA1-0.

0 V on BR, CLKIN Active (to force tristate condition).

Although specified for TTL outputs, all ADSP-2111 outputs are CMOS-compatible and will drive to V

and GND, assuming no dc loads.

Guaranteed but not tested.

Applies to ADSP-2111 PGA and PQFP packages.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

*Stresses greater than those listed above may cause permanent damage to the

ADSP-21xx

REV. B

ADSP-21xx

REV. B

SUPPLY CURRENT & POWER (ADSP-2111)

Parameter

Test Conditions

Min

Max

Unit

Supply Current (Dynamic)

@ V

= max, t

= 50 ns

@ V

= max, t

= 60 ns

@ V

= max, t

= 76.9 ns

Supply Current (Idle)

1, 3

@ V

= max, t

= 50 ns

@ V

= max, t

= 60 ns

@ V

= max, t

= 76.9 ns

NOTES

Current reflects device operating with no output loads.

= 0.4 V and 2.4 V.

Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

For typical supply current (internal power dissipation) figures, see Figure 17.

SPECIFICATIONS (ADSP-2111)

Figure 17. ADSP-2111 Power (Typical) vs. Frequency

POWER (P

DLE

) mW

POWER, IDLE

1,2

100

100mW

70mW

50mW

 MHz

40mW

55mW

80mW

POWER, IDLE

n MODES

IDLE;

32mW

34mW

IDLE 16;
IDLE 128;

70mW

55mW

36mW

38mW

POWER (P

IDLE

) mW

 MHz

VALID FOR ALL TEMPERATURE GRADES.

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

MAXIMUM POWER DISSIPATION AT V

= 5.0V DURING EXECUTION OF

IDLE

INSTRUCTION.

POWER (P

INT

) mW

 MHz

330mW

260mW

200mW

250mW

200mW

155mW

POWER, INTERNAL

190

150

170

250

210

230

270

310

290

330

5.5V

5.0V

4.5V

5.5V

5.0V

4.5V

5.0V

ADSP-21xx

REV. B

POWER DISSIPATION EXAMPLE

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2111 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the
address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

= 5.0 V and t

= 50 ns.

Total Power Dissipation = P

INT

+ (C

f )

INT

= internal power dissipation (from Figure 17).

f ) is calculated for each output:

# of

Output

Pins

Address, DMS 8

10 pF

20 MHz = 40.0 mW

Data, WR

10 pF

10 MHz = 22.5 mW

10 pF

10 MHz = 2.5 mW

CLKOUT

10 pF

20 MHz = 5.0 mW

70.0 mW

Total power dissipation for this example = P

INT

+ 70.0 mW.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

AMB

= T

CASE

(PD

)

CASE

= Case Temperature in

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

= Thermal Resistance (Junction-to-Ambient)

= Thermal Resistance (Junction-to-Case)

Package

PGA

C/W

PQFP

C/W

SPECIFICATIONS (ADSP-2111)

CAPACITIVE LOADING

Figures 18 and 19 show capacitive loading characteristics for the
ADSP-2111.

 pF

150

125

100

RISE TIME (0.8V - 2.0V) ns

= 4.5V

Figure 18. Typical Output Rise Time vs. Load Capacitance, C

(at Maximum Ambient Operating Temperature)

 pF

100

125

150

VALID OUTPUT DELAY OR

HOLD ns

+10

+12

NOMINAL

= 4.5V

Figure 19. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating Temperature)

ADSP-21xx

REV. B

SPECIFICATIONS (ADSP-2111)

The decay time, t

DECAY

, is dependent on the capacitative load,

, and the current load, i

, on the output pin. It can be

approximated by the following equation:

DECAY

0.5 V

from which

DIS

= t

MEASURED

DECAY

is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

E NA

) is the interval from

when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 21. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.

TEST CONDITIONS

Figure 20 shows voltage reference levels for ac measurements.

Figure 20. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t

DIS

) is the difference of t

MEASURED

and

DECAY

, as shown in Figure 21. The time t

MEASURED

is the

interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.

3.0V
1.5V
0.0V

2.0V

1.5V

0.8V

INPUT

OUTPUT

Figure 22. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.

(MEASURED)

Figure 21. Output Enable/Disable

OUTPUT

PIN

50pF

+1.5V

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

Parameter

Min

Max

Min

Max

Unit

Supply Voltage

3.00

3.60

3.00

3.60

AMB

Ambient Operating Temperature

+70

+85

See "Environmental Conditions" for information on thermal specifications.

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Max

Unit

Hi-Level Input Voltage

1, 3

@ V

= max

2.0

Lo-Level Input Voltage

1, 3

@ V

= min

0.4

Hi-Level Output Voltage

2, 3, 6

@ V

= min, I

= 0.5 mA

2.4

Lo-Level Output Voltage

2, 3, 6

@ V

= min, I

= 2 mA

0.4

Hi-Level Input Current

@ V

= max, V

= V

max

Lo-Level Input Current

@ V

= max, V

= 0 V

OZH

Tristate Leakage Current

@ V

= max, V

= V

max

OZL

Tristate Leakage Current

@ V

= max, V

= 0 V

Input Pin Capacitance

1, 7, 8

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

Output Pin Capacitance

4, 7, 8, 9

@ V

= 2.5 V, f

= 1.0 MHz, T

AMB

= 25

NOTES

Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.

Output pins: BG, PMS, DMS, BMS, RD, WR, A0A13, CLKOUT, DT1, DT0.

Bidirectional pins: D0D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.

Tristatable pins: A0A13, D0D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.

0 V on BR, CLKIN Active (to force tristate condition).

All ADSP-2103, ADSP-2162, and ADSP-2164 outputs are CMOS and will drive to V

and GND with no dc loads.

Guaranteed but not tested.

Applies to PLCC and PQFP package types.

Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

ADSP-2103/2162/2164SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Output Voltage Swing . . . . . . . . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range (Ambient) . . . . 40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . . . 65ºC to +150ºC
Lead Temperature (5 sec) PLCC, PQFP . . . . . . . . . . . +280ºC

*Stresses greater than those listed above may cause permanent damage to the

ADSP-21xx

REV. B

ADSP-21xx

REV. B

SPECIFICATIONS (ADSP-2103/2162/2164)

SUPPLY CURRENT & POWER (ADSP-2103/2162/2164)

Parameter

Test Conditions

Min

Max

Unit

Supply Current (Dynamic)

@ V

= max, t

= 72.3 ns

Supply Current (Idle)

1, 3

@ V

= max, t

= 72.3 ns

NOTES

Current reflects device operating with no output loads.

= 0.4 V and 2.4 V.

Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

For typical supply current (internal power dissipation) figures, see Figure 23.

VALID FOR ALL TEMPERATURE GRADES.

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

IDLE REFERS TO ADSP-21xx OPERATION DURING EXECUTION OF IDLE INSTRUCTION.

DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

MAXIMUM POWER DISSIPATION AT V

= 3.6V DURING EXECUTION OF

IDLE

INSTRUCTION.

15.00

13.83

10.00

7.00

5.00

POWER mW

IDD IDLE

FREQUENCY

 MHz

9mW

6mW

5mW

13mW

10mW

8mW

POWER mW

IDLE DYNAMIC

1,2

FREQUENCY

 MHz

48mW

37mW

29mW

15mW

15.00

13.83

10.00

7.00

5.00

24mW

19mW

15.00

13.83

10.00

7.00

5.00

POWER mW

FREQUENCY

 MHz

IDLE 128

IDLE 16

IDD IDLE

9mW

5mW

4mW

13mW

7mW

6mW

IDD IDLE n MODES

3.6V

3.30V

3.0V

3.6V

3.30V

3.0V

Figure 23. ADSP-2103 Power (Typical) vs. Frequency

ADSP-21xx

REV. B

POWER DISSIPATION EXAMPLE

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

C = load capacitance, f = output switching frequency.

Example:

In an ADSP-2103 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:

Assumptions:

External data memory is accessed every cycle with 50% of the
address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

= 3.3 V and t

= 100 ns.

Total Power Dissipation = P

INT

+ (C

f )

INT

= internal power dissipation (from Figure 23).

f ) is calculated for each output:

# of

Output

Pins

Address, DMS 8

10 pF

3.3

10 MHz = 8.71 mW

Data, WR

10 pF

3.3

5 MHz

= 4.90 mW

10 pF

3.3

5 MHz

= 0.55 mW

CLKOUT

10 pF

3.3

10 MHz = 1.09 mW

15.25 mW

Total power dissipation for this example = P

INT

+ 15.25 mW.

ENVIRONMENTAL CONDITIONS

Ambient Temperature Rating:

AMB

= T

CASE

(PD

)

CASE

= Case Temperature in

PD = Power Dissipation in W

= Thermal Resistance (Case-to-Ambient)

= Thermal Resistance (Junction-to-Ambient)

= Thermal Resistance (Junction-to-Case)

Package

PGA

C/W

PQFP

C/W

SPECIFICATIONS (ADSP-2103/2162/2164)

Figure 25. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating Temperature)

Figure 24. Typical Output Rise Time vs. Load Capacitance, C

(at Maximum Ambient Operating Temperature)

CAPACITIVE LOADING

Figures 24 and 25 show capacitive loading characteristics for the
ADSP-2103, ADSP-2162, and ADSP-2164.

150

125

100

 pF

RISE TIME (0.8V-2.0V) ns

= 3.0V

VALID OUTPUT DELAY OR HOLD ns

NOMINAL

150

125

100

 pF

= 3.0V

ADSP-21xx

REV. B

The decay time, t

DECAY

, is dependent on the capacitative load,

, and the current load, i

, on the output pin. It can be

approximated by the following equation:

DECAY

0.5 V

from which

DIS

= t

MEASURED

DECAY

is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t

E NA

) is the interval from

when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 27. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.

SPECIFICATIONS (ADSP-2103/2162/2164)

TEST CONDITIONS

Figure 26 shows voltage reference levels for ac measurements.

Figure 26. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)

Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (t

DIS

) is the difference of t

MEASURED

and

DECAY

, as shown in Figure 27. The time t

MEASURED

is the

interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.

INPUT

OUTPUT

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5V.

(MEASURED)

OUTPUT

PIN

50pF

Figure 27. Output Enable/Disable

Figure 28. Equivalent Device Loading for AC Measurements
(Except Output Enable/Disable)

ADSP-21xx

REV. B

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its
signals. You have no control over this timing--circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)

switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.

MEMORY REQUIREMENTS

The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.

Memory

ADSP-21xx

Timing

Device

Timing

Parameter

Specification

Parameter

Definition

Address Setup to Write Start

ASW

A0A13, DMS, PMS Setup before WR Low

Address Setup to Write End

A0A13, DMS, PMS Setup before WR Deasserted

Address Hold Time

WRA

A0A13, DMS, PMS Hold after WR Deasserted

Data Setup Time

Data Setup before WR High

Data Hold Time

Data Hold after WR High

OE to Data Valid

RDD

RD Low to Data Valid

Address Access Time

A0A13, DMS, PMS, BMS to Data Valid

ADSP-21xx

REV. B

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)

Frequency

13 MHz

13.824 MHz

16.67 MHz

20 MHz

25 MHz

Dependency

Parameter

Min

Max

Min

Max

Min Max

Min

Max

Unit

Timing Requirement:
t

IFS

IRQx

or FI Setup before

34.2

33.1

27.5

0.25t

+ 15

CLKOUT Low

2, 3

IFS

IRQx

or FI Setup before

37.2

36.1

30.5

0.25t

+ 18

CLKOUT Low (ADSP-2111)

2, 3

IFH

IRQx

or FI Hold after CLKOUT 19.2

18.1

12.5

0.25t

High

2, 3

Switching Characteristic:
t

FOH

FO Hold after CLKOUT High

FOD

FO Delay from CLKOUT High

NOTES

IRQx=IRQ0, IRQ1, and IRQ2.

If IRQx and FI inputs meet t

IFS

and t

IFH

setup/hold requirements, they will be recognized during the current clock cycle; otherwise they will be recognized

during the following cycle. (Refer to the "Interrupt Controller" section in Chapter 3, Program Control, of the

ADSP-2100 Family User's Manual for further

information on interrupt servicing.)

Edge-sensitive interrupts require pulse widths greater than 10 ns. Level-sensitive interrupts must be held low until serviced.

IFS

(min) = 0.25t

+ 20 ns for ADSP-2101TG-50, ADSP-2101TG/883B-50, ADSP-2111TG-52, and ADSP-2111TG/883B-52 ( Extended Temperature Range

devices).

FOH

(min) = 5 ns for ADSP-2111TG-52 and ADSP-2111TG/883B-52 (Extended Temperature Range devices).

INTERRUPTS & FLAGS

Figure 30. Interrupts & Flags

CLKOUT

FLAG

OUTPUT(S)

FOD

IRQ

FOH

IFH

IFS

ADSP-21xx

REV. B

Frequency

13 MHz

13.824 MHz 16.67 MHz

20 MHz

25 MHz

Dependency

Parameter

Min Max Min Max

Min Max

Min Max Min Max Min

Max

Unit

Timing Requirement:
t

BR Hold after CLKOUT High

24.2

23.1

17.5

0.25t

+ 5

BR Setup before CLKOUT Low

39.2

38.1

32.5

0.25t

+ 20

Switching Characteristic:
t

CLKOUT High to DMS,

39.2

38.1

32.5

0.25t

+ 20 ns

PMS, BMS, RD, WR Disable

SDB

DMS, PMS, BMS, RD, WR

Disable to BG Low

BG High to DMS, PMS,

BMS, RD, WR Enable

SEC

DMS, PMS, BMS, RD, WR

9.2

8.1

2.5

1.5

0.25t

Enable to CLKOUT High

NOTES

If BR meets the t

and t

setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires

a pulse width greater than 10 ns.

For 25 MHz only the minimum frequency dependency formula for t

SEC

= (0.25t

8.5).

Section 10.2.4, "Bus Request/Grant," on page 212 of the

ADSP-2100 Family User's Manual (1st Edition, 1993) states that "When BR is recognized, the processor

responds immediately by asserting BG during the same cycle." This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after
BR is recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)

BUS REQUEST/GRANT

CLKOUT

PMS

DMS

BMS

CLKOUT

SDB

SEC

Figure 31. Bus Request/Grant

ADSP-21xx

REV. B

Frequency Dependency
(CLKIN

25 MHz)

Parameter

Min

Max

Unit

Timing Requirement:
t

RDD

RD Low to Data Valid

0.5t

13 + w

A0A13, PMS, DMS, BMS to Data Valid

0.75t

18 + w

RDH

Data Hold from RD High

Switching Characteristic:
t

RD Pulse Width

0.5t

8 + w

CRD

CLKOUT High to RD Low

0.25t

+ 10

ASR

A0A13, PMS, DMS, BMS Setup before
RD Low

0.25t

RDA

A0A13, PMS, DMS, BMS Hold after RD
Deasserted

0.25t

RWR

RD High to RD or WR Low

0.5t

NOTES

For 25 MHz only minimum frequency dependency formula for t

ASR

= (0.25t

8.5).

w = wait states

CK.

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)

MEMORY READ

Figure 32. Memory Read

CLKOUT

A0 A13

RDA

DMS, PMS

BMS

RWR

ASR

CRD

RDD

RDH

13 MHz

13.824 MHz

16.67 MHz

20 MHz

25 MHz

Parameter

Min

Max

Min

Max

Min

Max

Min

Max Min

Max Unit

Timing Requirement:
t

RDD

RD Low to Data Valid

23.5

23.2

A0A13, PMS, DMS, BMS to Data Valid

37.7

36.2

19.5

RDH

Data Hold from RD High

Switching Characteristic:
t

RD Pulse Width

33.5

28.2

CRD

CLKOUT High to RD Low

14.2

29.2

13.1

28.1

7.5

22.5

ASR

A0A13, PMS, DMS, BMS Setup before

9.2

8.1

2.5

1.5

RD Low

RDA

A0A13, PMS, DMS, BMS Hold after RD

10.2

9.1

3.5

Deasserted

RWR

RD High to RD or WR Low

33.5

31.2

ADSP-21xx

REV. B

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)

MEMORY WRITE

13 MHz

13.824 MHz 16.67 MHz

20 MHz

25 MHz

Parameter

Min

Max Min

Max

Min

Max

Min

Max

Min

Max Unit

Switching Characteristic:
t

Data Setup before WR High

25.5

23.2

Data Hold after WR High

9.2

8.1

2.5

WR Pulse Width

30.5

28.2

WDE

WR Low to Data Enabled

ASW

A0A13, DMS, PMS Setup before

9.2

8.1

2.5

1.5

WR Low

DDR

Data Disable before WR or RD Low

9.2

8.1

2.5

1.5

CWR

CLKOUT High to WR Low

14.2

29.2

13.1

28.1

7.5

22.5

A0A13, DMS, PMS, Setup before WR

35.7

32.2

15.5

Deasserted

WRA

A0A13, DMS, PMS Hold after WR

10.2

9.1

3.5

Deasserted

WWR

WR High to RD or WR Low

33.5

31.2

Figure 33. Memory Write

CLKOUT

A0 A13

WR A

DMS, PMS

WWR

AS W

CWR

DD R

WDE

Frequency Dependency
(CLKIN

25 MHz)

Parameter

Min

Max

Unit

Switching Characteristic:
t

Data Setup before WR High

0.5t

13 + w

Data Hold after WR High

0.25t

WR Pulse Width

0.5t

8 + w

WDE

WR Low to Data Enabled

ASW

A0A13, DMS, PMS Setup before WR Low

0.25t

DDR

Data Disable before WR or RD Low

0.25t

CWR

CLKOUT High to WR Low

0.25t

+ 10

A0A13, DMS, PMS, Setup before WR
Deasserted

0.75t

22 + w

WRA

A0A13, DMS, PMS Hold after WR
Deasserted

0.25t

WWR

WR High to RD or WR Low

0.5t

NOTES

For 25 MHz only the minimum frequency dependency formula for t

ASW

and t

DDR

= (0.25t

8.5).

w = wait states

ADSP-21xx

REV. B

Frequency

12.5 MHz

13.0 MHz

13.824 MHz*

Dependency

Parameter

Min Max

Min

Max

Min

Max

Unit

Timing Requirement:
t

SCK

SCLK Period

76.9

72.3

SCS

DR/TFS/RFS Setup before SCLK Low

SCH

DR/TFS/RFS Hold after SCLK Low

SCP

SCLK

Width

Switching Characteristic:
t

CLKOUT High to SCLK

OUT

19.2 34.2

18.1

33.1

0.25t

+ 15ns

SCDE

SCLK High to DT Enable

SCDV

SCLK High to DT Valid

TFS/RFS

OUT

Hold after SCLK High

TFS/RFS

OUT

Delay from SCLK High

SCDH

DT Hold after SCLK High

TDE

TFS (Alt) to DT Enable

TDV

TFS (Alt) to DT Valid

SCDD

SCLK High to DT Disable

RDV

RFS

(Multichannel, Frame Delay Zero)

to DT Valid

*Maximum serial port operating frequency is 13.824 MHz for all processor speed grades except the 12.5 MHz ADSP-2101 and 13.0 MHz ADSP-2111.

TIMING PARAMETERS (ADSP-2101/2105/2111/2115/2161/2163)

SERIAL PORTS

CLKOUT

SCLK

TFS

RFS

TFS

( ALTERNATE

FRAME MODE )

SCK

SCP

SCS

SCH

RFS

OUT

TFS

OUT

SCDV

SCDE

SCDH

SCDD

TDE

TDV

RDV

( MULTICHANNEL MODE,

FRAME DELAY 0 {MFD = 0} )

Figure 34. Serial Ports

ADSP-21xx

REV. B

TIMING PARAMETERS (ADSP-2111)

HOST INTERFACE PORT

Multiplexed Data & Address (HMD1 = 1)
Read/Write Strobe & Data Strobe (HMD0 = 1 )

13.0 MHz

16.67 MHz

20 MHz

No Frequency

Parameter

Min

Max

Min

Max

Min

Max

Dependency

Unit

Timing Requirement:
t

HALP

ALE Pulse Width

HASU

HAD15-0 Address Setup before ALE Low

HAH

HAD15-0 Address Hold after ALE Low

HALS

Start of Write or Read after ALE Low

HSU

HRW Setup before Start of Write or Read

HDSU

HAD15-0 Data Setup before End of Write

HWDH

HAD15-0 Data Hold after End of Write

HRW Hold after End of Write or Read

HRWP

Read or Write Pulse Width

Switching Characteristic:
t

HSHK

HACK Low after Start of Write or Read

HKH

HACK Hold after End of Write or Read

HDE

HAD15-0 Data Enabled after Start of Read

HDD

HAD15-0 Data Valid after Start of Read

HRDH

HAD15-0 Data Hold after End of Read

HRDD

HAD15-0 Data Disabled after End of Read

NOTES

Start of Write or Read = HDS Low and HSEL Low.

End of Write or Read = HDS High or HSEL High.

Read or Write Pulse Width = HDS Low and HSEL Low.

ADSP-21xx

REV. B

TIMING PARAMETERS (ADSP-2103/2162/2164)

Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.

MEMORY REQUIREMENTS

The table below shows common memory device specifications
and the corresponding ADSP-21xx timing parameters, for your
convenience.

GENERAL NOTES

TIMING NOTES

ADSP-21xx

Memory Specification

Timing Parameter

Timing Parameter Definition

Address Setup to Write Start

ASW

A0A13, DMS, PMS Setup before WR Low

Address Setup to Write End

A0A13, DMS, PMS Setup before WR Deasserted

Address Hold Time

WRA

A0A13, DMS, PMS Hold after WR Deasserted

Data Setup Time

Data Setup before WR High

Data Hold Time

Data Hold after WR High

OE to Data Valid

RDD

RD Low to Data Valid

Address Access Time

A0A13, DMS, PMS, BMS to Data Valid

ADSP-21xx

REV. B

PGA

Pin

Number

Name

GND

A10

A11

A12

A13

PMS

DMS

BMS

XTAL

CLKIN

L10

CLKOUT

Index (NC)

PIN CONFIGURATIONS

68-Pin PGA

PGA

Pin

Number

Name

A10

B10

D10

D11

GND

D12

D13

D14

D15

D16

D17

D18

PGA

Pin

Number

Name

GND

D19

D20

D21

D22

D23

MMAP

IRQ2

RESET

PGA PACKAGE

ADSP-2101

TOP VIEW

(PINS DOWN)

IRQ1

(TFS1)

GND

A10

A12

PMS

BMS

XTAL

CLK
OUT

A11

A13

DMS

CLK

GND

D19

D17

D15

D13

GND

D10

RESET

IRQ2

MMAP

D22

D23

D20

D21

INDEX

(NC)

D18

D16

D14

D12

D11

SCLK1

TFS0

DT0

GND

RFS0

SCLK0

DR0

(DT1)

IRQ0

(RFS1)

(DR1)

PGA PACKAGE

ADSP-2101

BOTTOM VIEW

(PINS UP)

IRQ1

(TFS1)

GND

A10

A12

PMS

BMS

XTAL

CLK
OUT

A11

A13

DMS

CLK

GND

D19

D17

D15

D13

GND

D10

RESET

IRQ2

MMAP

D22

D23

D20

D21

INDEX

(NC)

D18

D16

D14

D12

D11

SCLK1

TFS0

DT0

GND

RFS0

SCLK0

DR0

(DT1)

IRQ0

(RFS1)

(DR1)

NC = NO CONNECT

PGA

Pin

Number

Name

K11

K10

J11

DT0

J10

TFS0

H11

RFS0

H10

GND

G11

DR0

G10

SCLK0

F11

(DT1)

F10

IRQ1

(TFS1)

E11

IRQ0

(RFS1)

E10

(DR1)

D11

SCLK1

D10

C11

C10

B11

ADSP-21xx

REV. B

PLCC

Pin

Number Name

(DT1)

IRQ1

(TFS1)

IRQ0

(RFS1)

(DR1)

SCLK1

D10

PIN CONFIGURATIONS

68-Lead PLCC

PLCC

Pin

Number Name

D11

GND

D12

D13

D14

D15

D16

D17

D18

GND

D19

D20

D21

D22

D23

MMAP

PLCC

Pin

Number Name

IRQ2

RESET

GND

A10

A11

PLCC

Pin

Number Name

A12

A13

PMS

DMS

BMS

XTAL

CLKIN

CLKOUT

DT0

(NC on ADSP-2105)

TFS0

(NC on ADSP-2105)

RFS0

(NC on ADSP-2105)

GND

DR0

(NC on ADSP-2105)

SCLK0 (NC on ADSP-2105)

NC = NO CONNECT

GND

D19

D20

D21

D22

D23

MMAP

IRQ2

RESET

D18

D17

D16

D15

D14

D13

D12

GND

D11

D10

PIN 1

IDENTIFIER

SCLK1

(DR1)

IRQ0

(RFS1)

IRQ1

(TFS1)

(DT1)

SCLK0

(NC on ADSP-2105)

DR0

(NC on ADSP-2105)

GND

RFS0

(NC on ADSP-2105)

TFS0

(NC on ADSP-2105)

DT0

(NC on ADSP-2105)

GND

A10

A11

A12

A13

PMS

DMS

BMS

XTAL

CLKIN

CLKOUT

PLCC PACKAGE

ADSP-2101
ADSP-2103
ADSP-2105
ADSP-2115

ADSP-2161/62/63/64

TOP VIEW

(PINS DOWN)

ADSP-21xx

REV. B

PIN CONFIGURATIONS

80-Lead PQFP
80-Lead TQFP

PQFP/
TQFP

Pin

Number Name

GND

A10

A11

A12

A13

PMS

DMS

BMS

XTAL

CLKIN

PQFP/
TQFP

Pin

Number Name

CLKOUT

DT0

TFS0

RFS0

GND

DR0

SCLK0

(DT1)

IRQ1

(TFS1)

IRQ0

(RFS1)

(DR1)

SCLK1

PQFP/
TQFP

Pin

Number Name

D10

D11

GND

D12

D13

D14

D15

D16

D17

D18

PQFP/
TQFP

Pin

Number Name

GND

D19

D20

D21

D22

D23

MMAP

IRQ2

RESET

GND

A10

A11

A12

A13

PMS

DMS

BMS

XTAL

CLKIN

D18

D17

D16

D15

D14

D13

D12

GND

D11

D10

CLKOUT

DT0

TFS0

RFS0

GND

DR0

SCLK0

(DT1)

IRQ1

(TFS1)

IRQ0

(RFS1)

(DR1)

SCLK1

RESET

IRQ2

MMAP

D23

D22

D21

D20

D19

GND

PQFP PACKAGE

ADSP-2101
ADSP-2103
ADSP-2115

ADSP-2161/62/63/64

TOP VIEW

(PINS DOWN)

NC = NO CONNECT

ADSP-21xx

REV. B

PGA

Pin

Number Name

FL2

FL1

D10

D12

D11

GND

D13

D14

D15

D16

D17

N10

D18

M10

D19

N11

D20

M11

D22

PGA

Pin

Number Name

N13

D23

N12

D21

M13

MMAP

M12

GND

L13

L12

RESET

K13

PMS

K12

J13

BMS

J12

DMS

H13

H12

H11

G13

G12

G11

F13

F12

F11

E13

GND

E12

D13

D12

C13

C12

A11

PIN CONFIGURATIONS

100-Pin PGA

PGA PACKAGE

ADSP-2111

TOP VIEW

(PINS DOWN)

CLK
OUT

(D R1)

INDEX

PIN

(NC)

HD1

HD3

HA1

HD13

HD11

HD8

HD4

HD15

A12

A10

HD2

CLK

HD0

HD12

HD10

GND

HD6

HD5

HD14

A13

HA0

D18

D16

D13

D12

D10

D20

D21

D23

D19

D17

D14

D11

D22

GND

MMAP

FL1

D15

GND

FL2

FL0

SCLK1

GND

SCLK0

RFSO

TFS0

DR0

DT0

GND

BMODE

HMD1

HMD0

HD9

HD7

XTAL

A11

HSIZE

HWR/

HDS

RESET

PMS

BMS

DMS

IRQ1

(TFS1)

IRQ0

(RFS1)

(D T1)

HACK

IRQ2

HRD /

HRW

HSEL

HA2 /

ALE

NC = NO CONNECT

PGA PACKAGE

ADSP-2111

BOTTOM VIEW

(PINS UP)

D15

GND

HD9

HD7

XTAL

GND

PMS

BMS

RESET

A11

DMS

(D T1)

HACK

(DR1)

FL0

SCLK0

DT0

HMD0

IRQ1

(TFS1)

IRQ2

CLK
OUT

D12

D18

D16

D20

D13

D10

D23

D21

D19

D17

D11

D22

D14

MMAP

GND

FL1

FL2

SCLK1

GND

RFSO

DR0

TFS0

BMODE

HMD1

IRQ0

(RFS1)

INDEX

PIN

(NC)

HSIZE

HRD/

HRW

HD1

HD3

HD11

HD13

HD15

HD8

HD4

A10

A12

HWR/

HDS

HSEL

HA1

HD2

CLK

HD10

HD6

HD12

HD14

GND

HD5

A13

HA0

HA2 /

ALE

HD0

PGA

Pin

Number Name

Index (NC)

HA2/ALE

HA0

HWR/HDS

HSEL

HSIZE

HRD/HRW

HMD0

HMD1

IRQ2

BMODE

DT0

CLKOUT

HACK

DR0

TFS0

RFS0

SCLK0

GND

(DT1)

IRQ1

(TFS1)

IRQ0

(RFS1)

(DR1)

SCLK1

FL0

PGA

Pin

Number Name

B13

A10

A13

A12

A13

B12

A12

A11

HD14

B11

HD15

A10

HD12

B10

HD13

HD10

HD11

GND

HD8

HD9

HD6

HD7

HD5

HD4

XTAL

CLKIN

HD3

HD2

HD1

HD0

HA1

ADSP-21xx

REV. B

PIN CONFIGURATIONS

100-Lead Bumpered PQFP

PQFP

Pin

Number Name

GND

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

GND

MMAP

RESET

PMS

DMS

BMS

PQFP

Pin

Number Name

GND

A10

A11

A12

A13

HD15

HD14

HD13

HD12

HD11

HD10

HD9

HD8

GND

PQFP

Pin

Number Name

HD7

HD6

HD5

HD4

XTAL

CLKIN

HD3

HD2

HD1

HD0

HA2/ALE

HA1

HA0

HSEL

HWR/HDS

HRD/HRW

HSIZE

HMD1

HMD0

BMODE

IRQ2

HACK

CLKOUT

DT0

TFS0

PQFP

Pin

Number Name

RFS0

DR0

SCLK0

GND

(DT1)

IRQ1

(TFS1)

IRQ0

(RFS1)

(DR1)

SCLK1

FL0

FL1

FL2

D10

100

D11

A12

A13

HD15

HD14

HD13

HD12

HD11

HD10

HD9

HD8

GND

VDD

HD7

HD6

HD5

HD4

XTAL

CLKIN

HD3

HD2

HD1

HD0

HA2/ALE

HA1

HA0

NOTE: PIN 1 IS LOCATED AT THE CENTER OF THE BEVELED-EDGE SIDE OF THE PACKAGE.

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

GND

D11

D10

BEVELED EDGE

100

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38

88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64

PQFP PACKAGE

ADSP-2111

TOP VIEW

(PINS DOWN)

GND

MMAP

RESET

PMS
DMS
BMS

A0
A1
A2
A3
A4
A5

GND

A6
A7
A8
A9

A10
A11

VDD

VDD
FL2
FL1
FL0
SCLK1
FI

(DR1)

IRQ0

(RFS1)

IRQ1

(TFS1)

(DT1)

GND
SCLK0
DR0
RFS0
TFS0
DT0
CLKOUT

HACK
IRQ2

BMODE
HMD0
HMD1
HSIZE

HRD

/HRW

HWR

HDS

HSEL

ADSP-21xx

REV. B

MILLIMETERS

INCHES

SYMBOL

MIN

TYP

MAX

MIN

TYP

MAX

2.45

0.096

0.25

0.010

1.90

2.00

2.10

0.075

0.079

0.083

D, E

16.95

17.20

17.45

0.667

0.678

0.690

, E

13.90

14.00

14.10

0.547

0.551

0.555

, E

12.35

12.43

0.486

0.490

0.65

0.80

0.95

0.026

0.031

0.037

0.57

0.65

0.73

0.023

0.026

0.029

0.22

0.30

0.38

0.009

0.012

0.015

0.10

0.004

OUTLINE DIMENSIONS

ADSP-21xx

80-Lead Metric Plastic Quad Flatpack (PQFP)

80-Lead Metric Thin Quad Flatpack (TQFP)

MILLIMETERS

INCHES

MIN

TYP

MAX

MIN

TYP

MAX

1.60

0.063

0.05

0.15

0.002

0.006

1.35

1.40

1.45

0.053

0.055 0.057

15.75 16.00

16.25

0.620

0.630 0.640

13.95 14.00

14.05

0.549

0.551 0.553

12.35

12.43

0.486 0.490

0.50

0.60

0.75

0.020

0.024 0.030

0.57

0.65

0.73

0.022

0.026 0.029

0.25

0.30

0.35

0.010

0.012 0.014

0.10

0.004

PQFP

TQFP

TOP VIEW

(PINS DOWN)

SEATING

PLANE

ADSP-21xx

REV. B

ORDERING GUIDE

Ambient
Temperature

Instruction

Package

Part Number

Range

Rate (MHz)

Description

Option

ADSP-2101KG-66

C to +70

16.67 MHz

68-Pin PGA

G-68A

ADSP-2101BG-66

C to +85

16.67 MHz

68-Pin PGA

G-68A

ADSP-2101KP-66

C to +70

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2101BP-66

C to +85

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2101KS-66

C to +70

16.67 MHz

80-Lead PQFP

S-80

ADSP-2101BS-66

C to +85

16.67 MHz

80-Lead PQFP

S-80

ADSP-2101KG-80

C to +70

20.0 MHz

68-Pin PGA

G-68A

ADSP-2101BG-80

C to +85

20.0 MHz

68-Pin PGA

G-68A

ADSP-2101KP-80

C to +70

20.0 MHz

68-Lead PLCC

P-68A

ADSP-2101BP-80

C to +85

20.0 MHz

68-Lead PLCC

P-68A

ADSP-2101KS-80

C to +70

20.0 MHz

80-Lead PQFP

S-80

ADSP-2101BS-80

C to +85

20.0 MHz

80-Lead PQFP

S-80

ADSP-2101KP-100

C to +70

25.0 MHz

68-Pin PLCC

P-68A

ADSP-2101BP-100

C to +85

25.0 MHz

68-Pin PLCC

P-68A

ADSP-2101KS-100

C to +70

25.0 MHz

80-Lead PQFP

S-80

ADSP-2101BS-100

C to +85

25.0 MHz

80-Lead PQFP

S-80

ADSP-2101KG-100

C to +70

25.0 MHz

68-Lead PGA

G-68A

ADSP-2101BG-100

C to +85

25.0 MHz

68-Lead PGA

G-68A

ADSP-2101TG-50

C to +125

12.5 MHz

68-Pin PGA

G-68A

ADSP-2103KP-40 (3.3 V)

C to +70

10.24 MHz

68-Lead PLCC

P-68A

ADSP-2103BP-40 (3.3 V)

C to +85

10.24 MHz

68-Lead PLCC

P-68A

ADSP-2103KS-40 (3.3 V)

C to +70

10.24 MHz

80-Lead PQFP

S-80

ADSP-2103BS-40 (3.3 V)

C to +85

10.24 MHz

80-Lead PQFP

S-80

ADSP-2105KP-55

C to +70

13.824 MHz

68-Lead PLCC

P-68A

ADSP-2105BP-55

C to +85

13.824 MHz

68-Lead PLCC

P-68A

ADSP-2105KP-80

C to +70

20.0 MHz

68-Lead PLCC

P-68A

ADSP-2105BP-80

C to +85

20.0 MHz

68-Lead PLCC

P-68A

ADSP-2115KP-66

C to +70

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2115BP-66

C to +85

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2115KS-66

C to +70

16.67 MHz

80-Lead PQFP

S-80

ADSP-2115BS-66

C to +85

16.67 MHz

80-Lead PQFP

S-80

ADSP-2115KST-66

C to +70

16.67 MHz

80-Lead TQFP

ST-80

ADSP-2115BST-66

C to +85

16.67 MHz

80-Lead TQFP

ST-80

ADSP-2115KP-80

C to +70

20.0 MHz

68-Lead PLCC

P-68A

ADSP-2115BP-80

C to +85

20.0 MHz

68-Lead PLCC

P-68A

ADSP-2115KS-80

C to +70

20.0 MHz

80-Lead PQFP

S-80

ADSP-2115BS-80

C to +85

20.0 MHz

80-Lead PQFP

S-80

ADSP-2115KST-80

C to +70

20.0 MHz

80-Lead TQFP

ST-80

ADSP-2115BST-80

C to +85

20.0 MHz

80-Lead TQFP

ST-80

ADSP-2115KP-100

C to +70

25.0 MHz

68-Lead PLCC

P-68A

ADSP-2115BP-100

C to +85

25.0 MHz

68-Lead PLCC

P-68A

NOTES

K = Commercial Temperature Range (0

C to +70

C).

B = Industrial Temperature Range (40

C to +85

C).

T = Extended Temperature Range (55

C to +125

C).

G = Ceramic PGA (Pin Grid Array).
P = PLCC (Plastic Leaded Chip Carrier).
S = PQFP (Plastic Quad Flatpack).
ST = TQFP (Thin Quad Flatpack)

ADSP-21xx

REV. B

ORDERING GUIDE

Ambient
Temperature

Instruction

Package

Part Number

Range

Rate (MHz)

Description

Option

ADSP-2111KG-52

C to +70

13.0 MHz

100-Pin PGA

G-100A

ADSP-2111BG-52

C to +85

13.0 MHz

100-Pin PGA

G-100A

ADSP-2111KS-52

C to +70

13.0 MHz

100-Lead PQFP

S-100A

ADSP-2111BS-52

C to +85

13.0 MHz

100-Lead PQFP

S-100A

ADSP-2111KG-66

C to +70

16.67 MHz

100-Pin PGA

G-100A

ADSP-2111BG-66

C to +85

16.67 MHz

100-Pin PGA

G-100A

ADSP-2111KS-66

C to +70

16.67 MHz

100-Lead PQFP

S-100A

ADSP-2111BS-66

C to +85

16.67 MHz

100-Lead PQFP

S-100A

ADSP-2111KG-80

C to +70

20.0 MHz

100-Pin PGA

G-100A

ADSP-2111BG-80

C to +85

20.0 MHz

100-Pin PGA

G-100A

ADSP-2111KS-80

C to +70

20.0 MHz

100-Lead PQFP

S-100A

ADSP-2111BS-80

C to +85

20.0 MHz

100-Lead PQFP

S-100A

ADSP-2111TG-52

C to +125

13.0 MHz

100-Pin PGA

G-100A

ADSP-2161KP-66

C to +70

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2161BP-66

C to +85

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2161KS-66

C to +70

16.67 MHz

80-Lead PQFP

S-80

ADSP-2161BS-66

C to +85

16.67 MHz

80-Lead PQFP

S-80

ADSP-2162KP-40 (3.3 V)

C to +70

10.24 MHz

68-Lead PLCC

P-68A

ADSP-2162BP-40 (3.3 V)

C to +85

10.24 MHz

68-Lead PLCC

P-68A

ADSP-2162KS-40 (3.3 V)

C to +70

10.24 MHz

80-Lead PQFP

S-80

ADSP-2162BS-40 (3.3 V)

C to +85

10.24 MHz

80-Lead PQFP

S-80

ADSP-2163KP-66

C to +70

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2163BP-66

C to +85

16.67 MHz

68-Lead PLCC

P-68A

ADSP-2163KS-66

C to +70

16.67 MHz

80-Lead PQFP

S-80

ADSP-2163BS-66

C to +85

16.67 MHz

80-Lead PQFP

S-80

ADSP-2163KP-100

C to +70

25 MHz

68-Lead PLCC

P-68A

ADSP-2163BP-100

C to +85

25 MHz

68-Lead PLCC

P-68A

ADSP-2163KS-100

C to +70

25 MHz

80-Lead PQFP

S-80

ADSP-2163BS-100

C to +85

25 MHz

80-Lead PQFP

S-80

ADSP-2164KP-40 (3.3 V)

C to +70

10.24 MHz

68-Lead PLCC

P-68A

ADSP-2164BP-40 (3.3 V)

C to +85

10.24 MHz

68-Lead PLCC

P-68A

ADSP-2164KS-40 (3.3 V)

C to +70

10.24 MHz

80-Lead PQFP

S-80

ADSP-2164BS-40 (3.3 V)

C to +85

10.24 MHz

80-Lead PQFP

S-80

NOTES

K = Commercial Temperature Range (0

C to +70

C).

B = Industrial Temperature Range (40

C to +85

C).

T = Extended Temperature Range (55

C to +125

C).

G = Ceramic PGA (Pin Grid Array).
P = PLCC (Plastic Leaded Chip Carrier).
S = PQFP (Plastic Quad Flatpack).

Minimum order quantities required. Contact factory for further information.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-2163BS-66

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-2163BS-66