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REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

ADSP-2189M

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

DSP Microcomputer

FUNCTIONAL BLOCK DIAGRAM

SERIAL PORTS

SPORT 1

SPORT 0

MEMORY

PROGRAMMABLE

I/O

AND

FLAGS

BYTE DMA

CONTROLLER

PROGRAM

MEMORY

32K
24 BIT

DATA

MEMORY

48K
16 BIT

TIMER

ADSP-2100 BASE

ARCHITECTURE

SHIFTER

MAC

ALU

ARITHMETIC UNITS

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

DAG 2

DAG 1

DATA ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

EXTERNAL

DATA

BUS

EXTERNAL

ADDRESS

BUS

INTERNAL

DMA

PORT

EXTERNAL

DATA

BUS

FULL MEMORY

MODE

HOST MODE

GENERAL DESCRIPTION

The ADSP-2189M is a single-chip microcomputer optimized
for digital signal processing (DSP) and other high speed nu-
meric processing applications.

The ADSP-2189M combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.

The ADSP-2189M integrates 192K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM and 48K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2189M is available in a 100-lead LQFP
package.

In addition, the ADSP-2189M supports new instructions, which
include bit manipulations--bit set, bit clear, bit toggle, bit test--
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.

FEATURES
PERFORMANCE
13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),

75 MIPS Sustained Performance

Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION
ADSP-2100 Family Code Compatible (Easy to Use Alge-

braic Syntax), with Instruction Set Extensions

192K Bytes of On-Chip RAM, Configured as 32K Words

On-Chip Program Memory RAM and 48K Words On-
Chip Data Memory RAM

Dual Purpose Program Memory for Both Instruction

and Data Storage

Independent ALU, Multiplier/Accumulator and Barrel

Shifter Computational Units

Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP

SYSTEM INTERFACE
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;

All Inputs Tolerate Up to 3.6 V, Regardless of Mode

16-Bit Internal DMA Port for High Speed Access to On-

Chip Memory (Mode Selectable)

4 MByte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program

and Data Memory Transfers (Mode Selectable)

I/O Memory Interface with 2048 Locations Supports

Parallel Peripherals (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits "Glueless" System Design

Programmable Wait-State Generation
Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port

Six External Interrupts
13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT Reconfiguration
ICE-PortTM Emulator Interface Supports Debugging in

Final Systems

ICE-Port is a trademark of Analog Devices, Inc.

REV. A

ADSP-2189M

Fabricated in a high speed, low power, CMOS process, the
ADSP-2189M operates with a 13.3 ns instruction cycle time.
Every instruction can execute in a single processor cycle.

The ADSP-2189M's flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle, the ADSP-2189M can:

· Generate the next program address
· Fetch the next instruction
· Perform one or two data moves
· Update one or two data address pointers
· Perform a computational operation

This takes place while the processor continues to:

· Receive and transmit data through the two serial ports
· Receive and/or transmit data through the internal DMA port
· Receive and/or transmit data through the byte DMA port
· Decrement timer

DEVELOPMENT SYSTEM

The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2189M. The System Builder provides a high
level method for defining the architecture of systems under
development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruc-
tion-level simulation with a reconfigurable user interface to
display different portions of the hardware environment.

A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation's
GNU C Compiler, generates ADSP-2189M assembly source
code. The source code debugger allows programs to be cor-
rected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.

The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x-based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-218x EZ-KIT Lite is a low cost, easy to use hard-
ware platform on which you can quickly get started with your
DSP software design. The EZ-KIT Lite includes the following
features:

· 33 MHz ADSP-218x
· Full 16-bit Stereo Audio I/O with AD1847 SoundPort

Codec

· RS-232 Interface to PC with Windows 3.1 Control Software
· EZ-ICE Connector for Emulator Control
· DSP Demo Programs

The ADSP-218x EZ-ICE

Emulator aids in the hardware de-

bugging of an ADSP-2189M system. The emulator consists of
hardware, host computer resident software and the target board
connector. The ADSP-2189M integrates on-chip emulation
support with a 14-pin ICE-Port interface. This interface pro-
vides a simpler target board connection that requires fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-2189M device need not be re-
moved from the target system when using the EZ-ICE, nor are
any adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.

The EZ-ICE performs a full range of functions, including:

· In-target operation
· Up to 20 breakpoints
· Single-step or full-speed operation
· Registers and memory values can be examined and altered
· PC upload and download functions
· Instruction-level emulation of program booting and execution
· Complete assembly and disassembly of instructions
· C source-level debugging

See "Designing An EZ-ICE-Compatible Target System" in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.

Additional Information

This data sheet provides a general overview of ADSP-2189M
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User's Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Develop-
ment Tools Data Sheet.

ARCHITECTURE OVERVIEW

The ADSP-2189M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2189M assembly language uses an
algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.

SERIAL PORTS

SPORT 1

SPORT 0

MEMORY

PROGRAMMABLE

I/O

AND

FLAGS

BYTE DMA

CONTROLLER

PROGRAM

MEMORY

32K
24 BIT

DATA

MEMORY

48K
16 BIT

TIMER

ADSP-2100 BASE

ARCHITECTURE

SHIFTER

MAC

ALU

ARITHMETIC UNITS

POWER-DOWN

CONTROL

PROGRAM

SEQUENCER

DAG 2

DAG 1

DATA ADDRESS

GENERATORS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

PROGRAM MEMORY DATA

DATA MEMORY DATA

EXTERNAL

DATA

BUS

EXTERNAL

ADDRESS

BUS

INTERNAL

DMA

PORT

EXTERNAL

DATA

BUS

FULL MEMORY

MODE

HOST MODE

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the ADSP-2189M. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.

The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.

EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.

REV. A

ADSP-2189M

The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.

A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2189M executes looped
code with zero overhead; no explicit jump instructions are re-
quired to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.

Efficient data transfer is achieved with the use of five internal
buses:

· Program Memory Address (PMA) Bus
· Program Memory Data (PMD) Bus
· Data Memory Address (DMA) Bus
· Data Memory Data (DMD) Bus
· Result (R) Bus

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit-
ting the ADSP-2189M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2189M can fetch an operand from program memory and
the next instruction in the same cycle.

In lieu of the address and data bus for external memory connec-
tion, the ADSP-2189M may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.

An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.

The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait-state generation. External devices can gain
control of external buses with bus request/grant signals (

BR,

BGH and BG). One execution mode (Go Mode) allows the
ADSP-2189M to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.

The ADSP-2189M can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master

RESET signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.

Each port can generate an internal programmable serial clock or
accept an external serial clock.

The ADSP-2189M provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.

A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycles, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).

Serial Ports

The ADSP-2189M incorporates two complete synchronous
serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.

Here is a brief list of the capabilities of the ADSP-2189M
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User's Manual, Third Edition.

· SPORTs are bidirectional and have a separate, double-buff-

ered transmit and receive section.

· SPORTs can use an external serial clock or generate their

own serial clock internally.

· SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.

· SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and

µ-law companding according

to CCITT recommendation G.711.

· SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

· SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.

· SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.

· SPORT1 can be configured to have two external interrupts

(

IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this con-
figuration.

PIN DESCRIPTIONS

The ADSP-2189M will be available in a 100-lead LQFP pack-
age. In order to maintain maximum functionality and reduce
package size and pin count, some serial port, programmable
flag, interrupt and external bus pins have dual, multiplexed
functionality. The external bus pins are configured during
RESET only, while serial port pins are software configurable
during program execution. Flag and interrupt functionality is
retained concurrently on multiplexed pins. In cases where pin

REV. A

ADSP-2189M

functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.

Common-Mode Pins

Pin

# of

Name(s)

Pins I/O Function

RESET

Processor Reset Input

Bus Request Input

Bus Grant Output

BGH

Bus Grant Hung Output

DMS

Data Memory Select Output

PMS

Program Memory Select Output

IOMS

Memory Select Output

BMS

Byte Memory Select Output

CMS

Combined Memory Select Output

Memory Read Enable Output

Memory Write Enable Output

IRQ2

Edge- or Level-Sensitive Interrupt
Requests

PF7

I/O Programmable I/O Pin.

IRQL1

Level-Sensitive Interrupt Requests

PF6

I/O Programmable I/O Pin

IRQL0

Level-Sensitive Interrupt Requests

PF5

I/O Programmable I/O Pin

IRQE

Edge-Sensitive Interrupt Requests

PF4

I/O Programmable I/O Pin

Mode D

Mode Select Input--Checked Only
During

RESET

PF3

I/O Programmable I/O Pin During

Normal Operation

Mode C

Mode Select Input--Checked Only
During

RESET

PF2

I/O Programmable I/O Pin During

Normal Operation

Mode B

Mode Select Input--Checked
Only During

RESET

PF1

I/O Programmable I/O Pin During

Normal Operation

Mode A

Mode Select Input--Checked Only
During

RESET

PF0

I/O Programmable I/O Pin During

Normal Operation

CLKIN, XTAL 2

Clock or Quartz Crystal Input

CLKOUT

Processor Clock Output

SPORT0

I/O Serial Port I/O Pins

SPORT1

I/O Serial Port I/O Pins

IRQ1:0, FI, FO

Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out

PWD

Power-Down Control Input

PWDACK

Power-Down Control Output

FL0, FL1, FL2 3

Output Flags

DDINT

Internal VDD (2.5 V) Power

DDEXT

External VDD (2.5 V or 3.3 V)
Power

GND

Ground

EZ-Port

I/O For Emulation Use

NOTES

Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, then the DSP will vector to the appropri-
ate interrupt vector address when the pin is asserted, either by external devices,
or set as a programmable flag.

SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.

Memory Interface Pins

The ADSP-2189M processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during

RESET and cannot be changed while

the processor is running.

Full Memory Mode Pins (Mode C = 0)

Pin

# of

Name

Pins

I/O

Function

A13:0

Address Output Pins for Program,
Data, Byte and I/O Spaces

D23:0

I/O

Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses.)

Host Mode Pins (Mode C = 1)

Pin

# of

Name

Pins

I/O

Function

IAD15:0

I/O

IDMA Port Address/Data Bus

Address Pin for External I/O,
Program, Data, or Byte Access

D23:8

I/O

Data I/O Pins for Program, Data
Byte and I/O Spaces

IWR

IDMA Write Enable

IRD

IDMA Read Enable

IAL

IDMA Address Latch Pin

IDMA Select

IACK

IDMA Port Acknowledge Config-
urable in Mode D; Open Drain

NOTE

In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS and IOMS signals.

Interrupts

The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2189M provides four dedicated external interrupt
input pins,

IRQ2, IRQL0, IRQL1 and IRQE (shared with the

PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-2189M also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
rupt levels are internally prioritized and individually maskable
(except power-down and reset). The

IRQ2, IRQ0 and IRQ1

input pins can be programmed to be either level- or edge-sensi-
tive.

IRQL0 and IRQL1 are level-sensitive and IRQE is edge-

sensitive. The priorities and vector addresses of all interrupts are
shown in Table I.

REV. A

ADSP-2189M

Table I. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Source Of Interrupt

Address (Hex)

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)

002C

IRQ2

0004

IRQL1

0008

IRQL0

000C

SPORT0 Transmit

0010

SPORT0 Receive

0014

IRQE

0018

BDMA Interrupt

001C

SPORT1 Transmit or

IRQ1

0020

SPORT1 Receive or

IRQ0

0024

Timer

0028 (Lowest Priority)

Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.

The ADSP-2189M masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the IMASK
register. This does not affect serial port autobuffering or DMA
transfers.

The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the

IRQ0, IRQ1 and IRQ2 external interrupts to

be either edge- or level-sensitive. The

IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.

The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or dis-
able servicing of the interrupts (including power-down), regard-
less of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.

ENA INTS;
DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW POWER OPERATION

The ADSP-2189M has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:

· Power-Down
· Idle
· Slow Idle

The CLKOUT pin may also be disabled to reduce external
power dissipation.

Power-Down

The ADSP-2189M processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. Refer to the ADSP-2100 Family User's Manual,

Third Edition, "System Interface" chapter, for detailed infor-
mation about the power-down feature.

Quick recovery from power-down. The processor begins
executing instructions in as few as 200 CLKIN cycles.

Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating and
200 CLKIN cycle recovery.

Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
mately 4096 CLKIN cycles for the crystal oscillator to start
or stabilize) and letting the oscillator run to allow 200 CLKIN
cycle start up.

Power-down is initiated by either the power-down pin
(

PWD) or the software power-down force bit. Interrupt

support allows an unlimited number of instructions to be
executed before optionally powering down. The power-down
interrupt also can be used as a nonmaskable, edge-sensitive
interrupt.

Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.

The

RESET pin also can be used to terminate power-down.

Power-down acknowledge pin indicates when the processor
has entered power-down.

Idle

When the ADSP-2189M is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt occurs.
When an unmasked interrupt occurs, it is serviced; execution
then continues with the instruction following the IDLE instruc-
tion. In Idle mode IDMA, BDMA and autobuffer cycle steals
still occur.

Slow Idle

The IDLE instruction is enhanced on the ADSP-2189M to let
the processor's internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction.

The format of the instruction is:

IDLE (n);

where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor's other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.

When the IDLE (n) instruction is used, it effectively slows down
the processor's internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2189M will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.

When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor's reduced internal clock rate.
Under these conditions, interrupts must not be generated at a

REV. A

ADSP-2189M

faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).

SYSTEM INTERFACE

Figure 2 shows typical basic system configurations with the
ADSP-2189M, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories (mode
selectable). Programmable Wait-State generation allows the
processor connects easily to slow peripheral devices. The
ADSP-2189M also provides four external interrupts and two
serial ports or six external interrupts and one serial port. Host
Memory Mode allows access to the full external data bus, but
limits addressing to a single address bit (A0). Additional system
peripherals can be added in this mode through the use of exter-
nal hardware to generate and latch address signals.

1/2x CLOCK

CRYSTAL

SERIAL
DEVICE

SCLK1
RFS1 OR

IRQ0

TFS1 OR

IRQ1

DT1 OR FO
DR1 OR FI

SPORT1

SCLK0
RFS0
TFS0
DT0
DR0

SPORT0

A0-A21

DATA

BYTE

MEMORY

I/O SPACE

(PERIPHERALS)

DATA

ADDR

DATA

ADDR

2048 LOCATIONS

OVERLAY

MEMORY

TWO 8K

PM SEGMENTS

TWO 8K

DM SEGMENTS

23-0

13-0

23-8

10-0

15-8

23-16

13-0

FL0-2

CLKIN

XTAL

ADDR13-0

DATA23-0

BMS

IOMS

PMS

DMS
CMS

BGH

PWD

ADSP-2189M

IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6

MODE C/PF2
MODE B/PF1
MODE A/PF0

FULL MEMORY MODE

PWDACK

MODE D/PF3

1/2x CLOCK

CRYSTAL

SERIAL
DEVICE

SYSTEM

INTERFACE

CONTROLLER

SCLK1
RFS1 OR

IRQ0

TFS1 OR

IRQ1

DT1 OR FO
DR1 OR FI

SPORT1

SCLK0
RFS0
TFS0
DT0
DR0

SPORT0

IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0

IDMA PORT

FL0-2

CLKIN

XTAL

DATA23-8

BMS

IOMS

PMS

DMS
CMS

BGH

PWD

ADSP-2189M

IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6

MODE C/PF2
MODE B/PF1
MODE A/PF0

HOST MEMORY MODE

PWDACK

MODE D/PF3

Figure 2. ADSP-2189M Basic System Interface

Clock Signals

The ADSP-2189M can be clocked by either a crystal or a TTL-
compatible clock signal.

The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User's Manual, Third Edition for detailed
information on this power-down feature.

If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor's CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.

The ADSP-2189M uses an input clock with a frequency equal
to half the instruction rate; a 37.50 MHz input clock yields a
13.3 ns processor cycle (which is equivalent to 75 MHz). Nor-
mally, instructions are executed in a single processor cycle. All
device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled.

Because the ADSP-2189M includes an on-chip oscillator cir-
cuit, an external crystal may be used. The crystal should be
connected across the CLKIN and XTAL pins, with two capaci-
tors connected as shown in Figure 3. Capacitor values are de-
pendent on crystal type and should be specified by the crystal
manufacturer. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used.

A clock output (CLKOUT) signal is generated by the processor
at the processor's cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.

CLKIN

CLKOUT

XTAL

DSP

Figure 3. External Crystal Connections

Reset

The

RESET signal initiates a master reset of the ADSP-2189M.

The

RESET signal must be asserted during the power-up se-

quence to assure proper initialization.

RESET during initial

power-up must be held long enough to allow the internal clock
to stabilize. If

RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

is ap-

plied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the

RESET signal should be held low. On

any subsequent resets, the

RESET signal must meet the mini-

mum pulsewidth specification, t

RSP

The

RESET input contains some hysteresis; however, if you use

an RC circuit to generate your

RESET signal, the use of an

external Schmidt trigger is recommended.

REV. A

ADSP-2189M

The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When

RESET is released, if there is no pending bus

request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.

Power Supplies

The ADSP-2189M has separate power supply connections for
the internal (V

DDINT

) and external (V

DDEXT

) power supplies.

The internal supply must meet the 2.5 V requirement. The
external supply can be connected to either a 2.5 V or 3.3 V
supply. All external supply pins must be connected to the same
supply. All input and I/O pins can tolerate input voltages up
to 3.6 V regardless of the external supply voltage. This fea-
ture provides maximum flexibility in mixing 2.5 V and 3.3 V
components.

MODES OF OPERATION
Setting Memory Mode

Memory Mode selection for the ADSP-2189M is made during
chip reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP's PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.

Table II. ADSP-2189M Modes of Operation

MODE D

MODE C

MODE B

MODE A

Booting Method

BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.

No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used but the processor does not automatically use or wait for these
operations.

BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode.

IACK has active pull-down.

(REQUIRES ADDITIONAL HARDWARE).

IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode.

IACK has active pull-down.

BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode;

IACK requires external pull-

down. (REQUIRES ADDITIONAL HARDWARE).

IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode.

IACK requires external pull-down.

NOTE

Considered as standard operating settings. Using these configurations allows for easier design and better memory management.

Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power
consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
10 k

, can be used. This value should be sufficient to pull the

pin to the desired level and still allow the pin to operate as a
programmable flag output without undue strain on the processor's
output driver. For minimum power consumption during power-
down, reconfigure PF2 to be an input, as the pull-up or pull-
down will hold the pin in a known state and will not switch.

Active Configuration involves the use of a three-statable ex-
ternal driver connected to the Mode C pin. A driver's output
enable should be connected to the DSP's

RESET signal such

that it only drives the PF2 pin when

RESET is active (low).

When

RESET is deasserted, the driver should three-state, thus

allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
stated buffer. This ensures that the pin will be held at a constant
level and will not oscillate should the three-state driver's level
hover around the logic switching point.

IACK Configuration
Mode D = 0 and in host mode:

IACK is an active, driven signal

and cannot be wire OR-ed.

REV. A

ADSP-2189M

Mode D = 1 and in host mode:

IACK is an open source and

requires an external pull-down, but multiple

IACK pins can be

wire OR-ed together.

MEMORY ARCHITECTURE

The ADSP-2189M provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
ADSP-2189M.

Program Memory

Program Memory, Full Memory Mode is a 24-bit-wide space
for storing both instruction op codes and data. The ADSP-2189M
has 32K words of Program Memory RAM on chip and the
capability of accessing up to two 8K external memory overlay
spaces using the external data bus.

Program Memory, Host Mode allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available in
host mode due to a restricted data bus that is 16-bits wide only.

Table III. PMOVLAY Bits

PMOVLAY

Memory

A13

A12:0

0, 4, 5

Internal

Not Applicable Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x2000
and 0x3FFF

External

13 LSBs of Address

Overlay 2

Between 0x2000
and 0x3FFF

Data Memory

Data Memory, Full Memory Mode is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2189M has 48K words on Data
Memory RAM on-chip. Part of this space is used by 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All inter-
nal accesses complete in one cycle. Accesses to external memory
are timed using the wait-states specified by the DWAIT register
and the wait-state mode bit.

ACCESSIBLE WHEN
DMOVLAY = 2

ACCESSIBLE WHEN
DMOVLAY = 1

0 0000
0 1FFF

EXTERNAL
MEMORY

32 MEMORY

MAPPED

REGISTERS

0 3FFF

0 2000

0 1FFF

INTERNAL

8160

WORDS

0 0000

DATA MEMORY

ADDRESS

INTERNAL
MEMORY

8K INTERNAL

DMOVLAY =

0, 4, 5, 6, 7

EXTERNAL 8K

DMOVLAY = 1, 2

0 3FE0

0 3FDF

DATA MEMORY

ACCESSIBLE WHEN
DMOVLAY = 7

ACCESSIBLE WHEN
DMOVLAY = 6

0 0000
0 1FFF

ACCESSIBLE WHEN
DMOVLAY = 5

ALWAYS

ACCESSIBLE
AT ADDRESS

0 2000 0 3FFF

ACCESSIBLE WHEN

DMOVLAY = 0

ACCESSIBLE WHEN
DMOVLAY = 4

0 0000
0 1FFF

Figure 5. Data Memory Map

ACCESSIBLE WHEN
PMOVLAY = 2

ACCESSIBLE WHEN
PMOVLAY = 1

ACCESSIBLE WHEN
PMOVLAY = 5

ALWAYS

ACCESSIBLE
AT ADDRESS

0 0000 0 1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN
PMOVLAY = 4

INTERNAL
MEMORY

EXTERNAL
MEMORY

0 2000
0 3FFF

PM (MODE B = 0)

8K INTERNAL
PMOVLAY = 0

8K EXTERNAL

PROGRAM MEMORY

MODE B = 1

ADDRESS

0 3FFF

0 2000

0 1FFF

0 0000

8K INTERNAL

PMOVLAY = 0, 4, 5

8K EXTERNAL

PMOVLAY = 1, 2

0 3FFF

0 2000

0 1FFF

8K INTERNAL

0 0000

PROGRAM MEMORY

MODE B = 0

ADDRESS

ACCESSIBLE WHEN
PMOVLAY = 1

RESERVED

INTERNAL
MEMORY

EXTERNAL
MEMORY

0 2000
0 3FFF

0 0000
0 1FFF

PM (MODE B = 1)

RESERVED

WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

SEE TABLE III FOR PMOVLAY BITS

ACCESSIBLE WHEN

PMOVLAY = 0

RESERVED

0 0000
0 1FFF

Figure 4. Program Memory

REV. A

ADSP-2189M

Data Memory, Host Mode allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).

Table IV. DMOVLAY Bits

PMOVLAY

Memory

A13

A12:0

0, 4, 5, 6, 7

Internal

Not Applicable Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x2000
and 0x3FFF

External

13 LSBs of Address

Overlay 2

Between 0x2000
and 0x3FFF

Memory Mapped Registers (New to the ADSP-2189M)

The ADSP-2189M has three memory mapped registers that
differ from other ADSP-21xx Family DSPs. The slight modifi-
cations to these registers (Wait-State Control, Programmable
Flag and Composite Select Control and System Control) pro-
vide the ADSP-2189M's wait-state and

BMS control features.

DWAIT

IOWAIT3

IOWAIT2

IOWAIT1

IOWAIT0

DM(0x3FFE)

WAIT STATE MODE SELECT (ADSP-2189M)
0 = NORMAL MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7)
1 = 2N+1 MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 15)

WAIT-STATE CONTROL

15 14 13 12 11 10

Figure 6. Wait-State Control Register (ADSP-2189M)

BMWAIT

(BIT-15, ADSP-2189M)

CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS

DM(0x3FE6)

PROGRAMMABLE FLAG & COMPOSITE SELECT CONTROL

PFTYPE
0 = INPUT
1 = OUTPUT

(WHERE BIT: 11-IOM, 10BM, 9-DM, 8-PM)

15 14 13 12 11 10

Figure 7. Programmable Flag and Composite Select Con-
trol Register

RESERVED, ALWAYS = 0

(ADSP-2189M)

SPORT0 ENABLE
0 = DISABLE
1 = ENABLE

DM(0x3FFF)

SYSTEM CONTROL

SPORT1 ENABLE
0 = DISABLE
1 = ENABLE

SPORT1 CONFIGURE
0 = FI, FO,

IRQ0, IRQ1, SCLK

1 = SPORT1

DISABLE

BMS (ADSP-2189M)

0 = ENABLE

BMS

1 = DISABLE

BMS, EXCEPT WHEN MEMORY

STROBES ARE THREE-STATED

PWAIT
PROGRAM MEMORY
WAIT STATES

15 14 13 12 11 10

Figure 8. System Control Register

I/O Space (Full Memory Mode)

The ADSP-2189M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit-wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait-state
registers, IOWAIT03, which, in combination with the wait-
state mode bit, specify up to 15 wait-states to be automatically
generated for each of four regions. The wait-states act on ad-
dress ranges as shown in Table V.

Table V. Wait-States

Address Range

Wait-State Register

0x0000x1FF

IOWAIT0 and Wait-State Mode Select Bit

0x2000x3FF

IOWAIT1 and Wait-State Mode Select Bit

0x4000x5FF

IOWAIT2 and Wait-State Mode Select Bit

0x6000x7FF

IOWAIT3 and Wait-State Mode Select Bit

Composite Memory Select (

CMS)

The ADSP-2189M has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The

CMS signal is generated

to have the same timing as each of the individual memory
select signals (

PMS, DMS, BMS, IOMS) but can combine

their functionality.

When set, each bit in the CMSSEL register causes the

CMS

signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the

PMS and DMS bits in the

CMSSEL register and use the

CMS pin to drive the chip select

of the memory, and use either

DMS or PMS as the additional

address bit.

The

CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the

CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at
reset, except the

BMS bit.

Byte Memory Select (

BMS)

The ADSP-2189M's

BMS disable feature combined with the

CMS pin lets you use multiple memories in the byte memory
space. For example, an EPROM could be attached to the

BMS

select, and an SRAM could be connected to

CMS. Because

BMS is enabled at reset, the EPROM would be used for boot-
ing. After booting, software could disable

BMS and set the

CMS signal to respond to BMS, enabling the SRAM.

REV. A

ADSP-2189M

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K

× 8.

The byte memory space on the ADSP-2189M supports read
and write operations as well as four different data formats. The
byte memory uses data bits 15:8 for data. The byte memory
uses data bits 23:16 and address bits 13:0 to create a 22-bit
address. This allows up to a 4 meg

× 8 (32 megabit) ROM or

RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register and the wait-state mode bit.

Byte Memory DMA (BDMA, Full Memory Mode)

The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.

BDMA CONTROL

BMPAGE

BDMA
OVERLAY
BITS

BTYPE

BDIR
0 = LOAD FROM BM
1 = STORE TO BM

BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA

15 14 13 12 11 10

DM (0 3FE3)

Figure 9. BDMA Control Register

The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table VI shows the data formats
supported by the BDMA circuit.

Table VI. Data Formats

Internal

BTYPE

Memory Space

Word Size

Alignment

Program Memory

Full Word

Data Memory

Full Word

Data Memory

MSBs

Data Memory

LSBs

Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.

BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.

The source or destination of a BDMA transfer will always be
on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait-states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
external memory have priority over BDMA byte memory
accesses.

The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.

The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.

The BMWAIT field, which has four bits on ADSP-2189M,
allows selection of up to 15 wait-states for BDMA transfers.

Internal Memory DMA Port (IDMA Port; Host Memory
Mode)

The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2189M. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP's memory-
mapped control registers. A typical IDMA transfer process is
described as follows:

1. Host starts IDMA transfer.

2. Host checks

IACK control line to see if the DSP is busy.

3. Host uses

IS and IAL control lines to latch either the DMA

starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP's IDMA control registers. If Bit 15 = 1, the
value of bits 7:0 represent the IDMA overlay: Bits 14:8 must
be set to 0. If Bit 15 = 0, the value of bits 13:0 represent the
starting address of internal memory to be accessed and Bit 14
reflects PM or DM for access.

4. Host uses

IS and IRD (or IWR) to read (or write) DSP inter-

nal memory (PM or DM).

5. Host checks

IACK line to see if the DSP has completed the

previous IDMA operation.

6. Host ends IDMA transfer.

REV. A

ADSP-2189M

The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
pletely asynchronous and can be written while the ADSP-2189M
is operating at full speed.

The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.

IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-bit
address and 1-bit destination type can be driven onto the bus by
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
PM access. The falling edge of the IDMA address latch signal
(IAL) or the missing edge of the IDMA select signal (

IS) latches

this value into the IDMAA register.

Once the address is stored, data can then be either read from, or
written to, the ADSP-2189M's on-chip memory. Asserting the
select line (

IS) and the appropriate read or write line (IRD and

IWR respectively) signals the ADSP-2189M that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.

Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (

IS) and address latch enable (IAL) di-

rects the ADSP-2189M to write the address onto the IAD0-14
bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA
latches the address. If Bit 15 is set to 1, IDMA latches into the
OVLAY register. This register, shown below, is memory
mapped at address DM (0x3FE0). Note that the latched address
(IDMAA) cannot be read back by the host.

Refer to the following figures for more information on IDMA
and DMA memory maps.

IDMA CONTROL (U = UNDEFINED AT RESET)

DM(0 3FE0)

IDMAA ADDRESS

IDMAD DESTINATION MEMORY TYPE:
0 = PM
1 = DM

15 14 13 12 11 10

IDMA OVERLAY

DM(0 3FE7)

RESERVED SET TO 0

ID DMOVLAY

ID PMOVLAY

15 14 13 12 11 10

Figure 10. IDMA Control/OVLAY Registers

ACCESSIBLE WHEN
PMOVLAY = 5

ALWAYS

ACCESSIBLE
AT ADDRESS

0 0000 0 1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

ACCESSIBLE WHEN
PMOVLAY = 4

0 2000
0 3FFF

DMA

PROGRAM MEMORY

OVLAY

NOTE: IDMA AND BDMA HAVEN SEPARATE
DMA CONTROL REGISTERS

DMA

DATA MEMORY

OVLAY

ACCESSIBLE WHEN
DMOVLAY = 7

ACCESSIBLE WHEN
DMOVLAY = 6

0 0000
0 1FFF

ACCESSIBLE WHEN
DMOVLAY = 5

ALWAYS

ACCESSIBLE
AT ADDRESS

0 2000 0 3FFF

ACCESSIBLE WHEN

DMOVLAY = 0

ACCESSIBLE WHEN
DMOVLAY = 4

0 0000
0 1FFF

Figure 11. Direct Memory Access--PM and DM Memory
Maps

Bootstrap Loading (Booting)

The ADSP-2189M has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting is controlled by the Mode A, B and C configuration
bits.

When the MODE pins specify BDMA booting, the ADSP-2189M
initiates a BDMA boot sequence when reset is released.

The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.

The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.

The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
dresses to boot memory must be constructed externally to the
ADSP-2189M. The only memory address bit provided by the
processor is A0.

IDMA Port Booting

The ADSP-2189M can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
ADSP-2189M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.

REV. A

ADSP-2189M

Bus Request and Bus Grant

The ADSP-2189M can relinquish control of the data and ad-
dress buses to an external device. When the external device
requires access to memory, it asserts the bus request (

BR) sig-

nal. If the ADSP-2189M is not performing an external memory
access, it responds to the active

BR input in the following pro-

cessor cycle by:

Three-stating the data and address buses and the

PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers,

Asserting the bus grant (

BG) signal, and

Halting program execution.

If Go Mode is enabled, the ADSP-2189M will not halt program
execution until it encounters an instruction that requires an
external memory access.

If the ADSP-2189M is performing an external memory access
when the external device asserts the

BR signal, it will not three-

state the memory interfaces or assert the

BG signal until the

processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.

When the

BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program
execution from the point at which it stopped.

The bus request feature operates at all times, including when
the processor is booting and when

RESET is active.

The

BGH pin is asserted when the ADSP-2189M requires the

external bus for a memory or BDMA access, but is stopped.
The other device can release the bus by deasserting bus request.
Once the bus is released, the ADSP-2189M deasserts

BG and

BGH and executes the external memory access.

Flag I/O Pins

The ADSP-2189M has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2189M's
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.

In addition to the programmable flags, the ADSP-2189M has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.

Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.

INSTRUCTION SET DESCRIPTION

The ADSP-2189M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor's unique architecture, offers the following benefits:

The algebraic syntax eliminates the need to remember cryp-
tic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.

Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.

The syntax is a superset ADSP-2100 Family assembly language
and is completely source-and-object-code-compatible with
other family members. Programs may need to be relocated to
utilize on-chip memory and conform to the ADSP-2189M's
interrupt vector and reset vector map.

Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.

Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.

DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM

The ADSP-2189M has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE's in-circuit probe, a 14-pin
plug.

Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes),
then it does not matter that the mode information is latched by
an emulator reset. However, if using the

RESET pin as a

method of setting the value of the mode pins, the effects of an
emulator reset must be taken into consideration.

One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 12. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the

RESET or

ERESET pin.

PROGRAMMABLE I/O

MODE A/PFO

RESET

ERESET

ADSP-2189M

Figure 12. Mode A Pin/EZ-ICE Circuit

See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.

REV. A

ADSP-2189M

The ICE-Port interface consists of the following ADSP-2189M
pins:

EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,

and ELOUT.

These ADSP-2189M pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2189M and the connector must be kept as short as possible, no
longer than three inches.

The following pins are also used by the EZ-ICE:

BR, BG,

RESET, and GND.

The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2189M in the target system. This causes the
processor to use its

ERESET, EBR, and EBG pins instead of

the

RESET, BR, and BG pins. The BG output is three-stated.

These signals do not need to be jumper-isolated in your system.

The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown in
Figure 13. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.

GND

KEY (NO PIN)

RESET

TOP VIEW

EBG

EBR

ELOUT

EINT

ELIN

ECLK

EMS

ERESET

Figure 13. Target Board Connector for EZ-ICE

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion--you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1

× 0.1 inches. The pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.

Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.

Target Memory Interface

For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.

PM, DM, BM, IOM, and CM

Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in this data sheet. The performance of the EZ-ICE
may approach published worst case specification for some memory
access timing requirements and switching characteristics.

Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.

Restriction: All memory strobe signals on the ADSP-2189M
(

RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your

target system must have 10 k

pull-up resistors connected when

the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.

Target System Interface Signals

When the EZ-ICE board is installed, the performance on some
system signals change. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:

EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the

RESET

signal.

EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the

BR signal.

EZ-ICE emulation ignores

RESET and BR when single-

stepping.

EZ-ICE emulation ignores

RESET and BR when in Emula-

tor Space (DSP halted).

EZ-ICE emulation ignores the state of target

BR in certain

modes. As a result, the target system may take control of the
DSP's external memory bus only if bus grant (

BG) is as-

serted by the EZ-ICE board's DSP.

REV. A

ADSP-2189MSPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

K Grade

B Grade

Parameter

Min

Max

Min

Max

Unit

DDINT

2.37

2.63

2.25

2.75

DDEXT

2.37

3.6

2.25

3.6

INPUT

= 0.3

= 3.6

0.03

3.6

AMB

+70

+85

°C

NOTES

The ADSP-2189M is 3.3 V tolerant (always accepts up to 3.6 Volt max V

IH)

, but voltage compliance (on outputs, V

) depends on the input V

DDEXT

; because V

(max)

DDEXT

(max). This applies to Bidirectional pins (D0D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1A13, PF0PF7) and Input Only pins (CLKIN,

RESET, BR, DR0, DR1, PWD).

ELECTRICAL CHARACTERISTICS

K/B Grades

Parameter

Test Conditions

Min

Typ

Max

Unit

, Hi-Level Input Voltage

1, 2

@ V

DDINT

= max

1.5

, Hi-Level CLKIN Voltage

@ V

DDINT

= max

2.0

, Lo-Level Input Voltage

1, 3

@ V

DDINT

= min

0.6

, Hi-Level Output Voltage

1, 4 , 5

@ V

DDEXT

= min, I

= 0.5 mA

2.0

@ V

DDEXT

= 3.0 V, I

= 0.5 mA

2.4

@ V

DDEXT

= min, I

= 100

µA

DDEXT

0.3

, Lo-Level Output Voltage

1, 4, 5

@ V

DDEXT

= min, I

= 2 mA

0.4

, Hi-Level Input Current

@ V

DDINT

= max, V

= 3.6 V

µA

, Lo-Level Input Current

@ V

DDINT

= max, V

= 0 V

µA

OZH

, Three-State Leakage Current

@ V

DDINT

= max, V

= 3.6 V

µA

OZL

, Three-State Leakage Current

@ V

DDINT

= max, V

= 0 V

µA

, Supply Current (Idle)

@ V

DDINT

= 2.5, t

= 15 ns

, Supply Current (Idle)

@ V

DDINT

= 2.5, t

= 13.3 ns

, Supply Current (Dynamic)

@ V

DDINT

= 2.5, t

= 15 ns

AMB

= +25

°C

, Supply Current (Dynamic)

@ V

DDINT

= 2.5, t

= 13.3 ns

AMB

= +25

°C

, Supply Current (Power-Down)

12, 15

Lowest Power Mode

150

µA

, Input Pin Capacitance

3, 6, 13

@ V

= 2.5 V,

= 1.0 MHz,

AMB

= +25

°C

, Output Pin Capacitance

6, 7, 12, 14

@ V

= 2.5 V,

= 1.0 MHz,

AMB

= +25

°C

NOTES

Bidirectional pins: D0D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1A13, PF0PF7.

Input Only pins:

RESET, BR, DR0, DR1, PWD.

Input Only pins: CLKIN,

RESET, BR, DR0, DR1, PWD.

Output pins:

BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.

Although specified for TTL outputs, all ADSP-2189M outputs are CMOS-compatible and will drive to V

DDEXT

and GND, assuming no dc loads.

Guaranteed but not tested.

Three-statable pins: A0A13, D0-D23,

PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0PF7.

0 V on

BR.

Idle refers to ADSP-2189M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V

or GND.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2

and type 6, and 20% are idle instructions.

= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

See Chapter 9 of the ADSP-2100 Family User's Manual, Third Edition for details.

Applies to LQFP package type.

Output pin capacitance is the capacitive load for any three-stated output pin.

DDINT

= 2.5 V. T = 25

°C.

Specifications subject to change without notice.

REV. A

ADSP-2189M

TIMING PARAMETERS

GENERAL NOTES

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.

TIMING NOTES

Switching characteristics specify how the processor changes its
signals. You have no control over this timing--circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.

Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.

MEMORY TIMING SPECIFICATIONS

The table below shows common memory device specifications
and the corresponding ADSP-2189M timing parameters, for
your convenience.

Memory

Timing

Device

Parameter

Specification

Parameter Definition

Address Setup to

ASW

A0A13,

xMS Setup before

Write Start

WR Low

Address Setup to

A0A13,

xMS Setup before

Write End

WR Deasserted

Address Hold Time

WRA

A0A13,

xMS Hold before

WR Low

Data Setup Time

Data Setup before

High

Data Hold Time

Data Hold after

WR High

OE to Data Valid

RDD

RD Low to Data Valid

Address Access Time t

A0A13,

xMS to Data Valid

NOTE

xMS = PMS, DMS, BMS, CMS or IOMS.

ABSOLUTE MAXIMUM RATINGS

Value

Parameter

Min

Max

Internal Supply Voltage (V

DDINT

)

0.3 V

+3.0 V

External Supply Voltage (V

DDEXT

)

0.3 V

+4.6 V

Input Voltage

0.5 V

+4.6 V

Output Voltage Swing

0.5 V

DDEXT

+ 0.5 V

Operating Temperature Range (Ambient)

°C +85°C

Storage Temperature Range

°C +150°C

Lead Temperature (5 sec) LQFP

+280

°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Applies to Bidirectional pins (D0D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A1A13, PF0PF7) and Input only pins (CLKIN,

RESET, BR, DR0,

DR1,

PWD).

Applies to Output pins (

BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,

A0, DT0, DT1, CLKOUT, FL2-0,

BGH).

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-2189M features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A

ADSP-2189M

FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS

defined as 0.5t

CKI

. The ADSP-2189M uses an input clock

with a frequency equal to half the instruction rate: a 37.50 MHz
input clock (which is equivalent to 28 ns) yields a 13 ns proces-
sor cycle (equivalent to 75 MHz). t

values within the range of

0.5t

CKI

period should be substituted for all relevant timing pa-

rameters to obtain the specification value.

Example: t

CKH

= 0.5t

7 ns = 0.5 (15 ns) 7 ns = 0.5 ns

ENVIRONMENTAL CONDITIONS

Rating Description

Symbol

Value

Thermal Resistance

(Case-to-Ambient)

°C/W

(Junction-to-Ambient)

°C/W

(Junction-to-Case)

°C/W

NOTE

Where the ambient temperature rating (T

AMB

) is:

AMB

= T

CASE

(PD

)

CASE

= Case temperature in

°C

PD = Power dissipation in W.

POWER DISSIPATION

To determine total power dissipation in a specific application,
the following equation should be applied for each output:

× V

× f

C = load capacitance, f = output switching frequency.

Example:

In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:

Assumptions:
·

External data memory is accessed every cycle with 50% of
the address pins switching.

External data memory writes occur every other cycle with
50% of the data pins switching.

Each address and data pin has a 10 pF total load at the pin.

The application operates at V

DDEXT

= 3.3 V and t

= 15 ns.

Total Power Dissipation = P

INT

+ (C

× V

DDEXT

× f)

INT

= internal power dissipation from Power vs. Frequency

graph (Figure 15).

× V

DDEXT

× f) is calculated for each output:

# of

Parameters

Pins C

DDEXT

Address,

DMS

10 pF

3.3

33.3 MHz

29.0 mW

Data Output,

WR 9

10 pF

3.3

16.67 MHz

16.3 mW

10 pF

3.3

16.67 MHz

1.8 mW

CLKOUT

10 pF

3.3

33.3 MHz

3.6 mW

50.7 mW

Total power dissipation for this example is P

INT

+ 50.7 mW.

Output Drive Currents

Figure 14 shows typical I-V characteristics for the output drivers
on the ADSP-2189M. The curves represent the current drive
capability of the output drivers as a function of output voltage.

SOURCE VOLTAGE V

0.5

1.0

SOURCE CURRENT

20

40

60

DDEXT

= 3.6V @ 40 C

DDEXT

= 3.3V @ +25 C

DDEXT

= 2.5V @ +85 C

DDEXT

= 2.5V @ +85 C

DDEXT

= 3.3V @ +25 C

DDEXT

= 3.6V @ 40 C

80

1.5

2.0

2.5

3.0

3.5

4.0

Figure 14. Typical Output Driver Characteristics

REV. A

ADSP-2189M

VALID FOR ALL TEMPERATURE GRADES.

POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.

TYPICAL POWER DISSIPATION AT 2.5V V

DDINT

AND +25 C EXCEPT

WHERE SPECIFIED.

MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM

INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION
(TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE
IDLE INSTRUCTIONS.

IDLE REFERS TO ADSP-2189M STATE OF OPERATION DURING EXECUTION

OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V

OR GND.

POWER (P

IDLE

)

20mW

15mW

14.25mW

15.7mW

16.4mW

24mW

IDLE (16)

IDLE (128)

IDLE

POWER, IDLE n MODES

1/t

 MHz

POWER (P

IDLE

)

24mW

28mW

= 2.65V

20mW

24mW

= 2.5V

16.5mW

20mW

= 2.35V

POWER, IDLE

1, 2, 4

1/t

 MHz

1/t

 MHz

82mW

70mW

61mW

95mW

82mW

2189L POWER, INTERNAL

1, 2, 3

110mW

POWER (P

INT

)

= 2.65V

= 2.5V

= 2.35V

100

105

110

115

= 2.65V

= 2.35V

= 2.5V

Figure 15. Power vs. Frequency

CAPACITIVE LOADING

Figure 16 and Figure 17 show the capacitive loading character-
istics of the ADSP-2189M.

 pF

RISE TIME (0.4V

2.4V

)

300

100

150

200

250

T = +85 C
V

= 0V TO 2.0V

Figure 16. Typical Output Rise Time vs. Load Capacitance,
C

(at Maximum Ambient Operating Temperature)

 pF

VALID OUTPUT DELAY OR HOLD

100

150

250

200

NOMINAL

Figure 17. Typical Output Valid Delay or Hold vs. Load
Capacitance, C

(at Maximum Ambient Operating

Temperature)

INTERNAL Volts

700

CURRENT

2.25

2.35

2.5

2.75

2.65

600

300

200

100

500

400

800

900

657 A

393 A

131 A

772 A

475 A

161 A

TEMP = +85 C

TEMP = +70 C

TEMP = +25 C

Figure 18. IDD Power-Down

REV. A

ADSP-2189M

TEST CONDITIONS
Output Disable Time

Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (t

DIS

) is the difference of t

MEASURED

and t

DECAY

as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.

The decay time, t

DECAY

, is dependent on the capacitive load,

, and the current load, i

, on the output pin. It can be ap-

proximated by the following equation:

DECAY

× 0 5

from which

DIS

= t

MEASURED

 t

DECAY

is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.

1.5V

OUTPUT

INPUT

1.5V

2.0V

0.8V

Figure 19. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start

driving. The output enable time (t

ENA

) is the interval from when

a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.

2.0V

1.0V

ENA

REFERENCE

SIGNAL

OUTPUT

DECAY

(MEASURED)

OUTPUT STOPS

DRIVING

OUTPUT

STARTS

DRIVING

DIS

MEASURED

(MEASURED)

(MEASURED) 0.5V

(MEASURED) +0.5V

HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE

THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.

(MEASURED)

Figure 20. Output Enable/Disable

OUTPUT

PIN

50pF

+1.5V

Figure 21. Equivalent Device Loading for AC Measure-
ments (Including All Fixtures)

REV. A

ADSP-2189M

Parameter

Min

Max

Unit

Interrupts and Flags
Timing Requirements:
t

IFS

IRQx, FI, or PFx Setup before CLKOUT Low

1, 2, 3, 4

0.25t

+ 10

IFH

IRQx, FI, or PFx Hold after CLKOUT High

1, 2, 3, 4

0.25t

Switching Characteristics:
t

FOH

Flag Output Hold after CLKOUT Low

0.5t

FOD

Flag Output Delay from CLKOUT Low

0.5t

+ 4

NOTES

IRQx and FI inputs meet

IFS

and t

IFH

setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on

the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User's Manual, Third Edition, for further
information on interrupt servicing.)

Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.

IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.

PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.

Flag Outputs = PFx, FL0, FL1, FL2, Flag_out4.

FOD

FOH

IFH

IFS

CLKOUT

FLAG

OUTPUTS

IRQx

PFx

Figure 23. Interrupts and Flags

REV. A

ADSP-2189M

Parameter

Min

Max

Unit

Serial Ports
Timing Requirements:
t

SCK

SCLK Period

26.67

SCS

DR/TFS/RFS Setup before SCLK Low

SCH

DR/TFS/RFS Hold after SCLK Low

SCP

SCLKIN Width

Switching Characteristics:
t

CLKOUT High to SCLKOUT

0.25t

+ 6

SCDE

SCLK High to DT Enable

SCDV

SCLK High to DT Valid

TFS/RFS

OUT

Hold after SCLK High

TFS/RFS

OUT

Delay from SCLK High

SCDH

DT Hold after SCLK High

TDE

TFS (Alt) to DT Enable

TDV

TFS (Alt) to DT Valid

SCDD

SCLK High to DT Disable

RDV

RFS (Multichannel, Frame Delay Zero) to DT Valid

CLKOUT

SCLK

TFS

OUT

RFS

OUT

ALTERNATE

FRAME MODE

SCS

SCH

SCDE

SCDH

SCDD

TDE

RDV

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

TFS

RFS

OUT

TFS

OUT

TDV

SCDV

SCP

SCK

SCP

TFS

RFS

ALTERNATE

FRAME MODE

RDV

MULTICHANNEL

MODE,

FRAME DELAY 0

(MFD = 0)

TDV

TDE

Figure 27. Serial Ports

REV. A

ADSP-2189M

100-Lead LQFP Package Pinout

D19

D18

D17

D16

IRQE

+PF4

IRQL0

+PF5

GND

IRQL1

+PF6

DT0

TFS0

SCLK0

EXT

DT1

TFS1

RFS1

DR1

GND

SCLK1

ERESET

RESET

D15

D14

D13

D12

GND

D11

D10

DDEXT

GND

D7/

IWR

D6/

IRD

D5/IAL

D4/

GND
V

DD INT

D3/

IACK

D2/IAD15

D1/IAD14

D0/IAD13

EBG

BR
EBR

A4/IAD3

A5/IAD4

GND

A6/IAD5

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A11/IAD10

A12/IAD11

A13/IAD12

GND

CLKIN

XTAL

DDEXT

CLKOUT

GND

DDINT

BMS
DMS
PMS

IOMS

CMS

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

ADSP-2189M

IRQ2

+PF7

RFS0

DR0

EMS

ELOUT

ECLK

ELIN

EINT

A3/IAD2

A2/IAD1

A1/IAD0

PWDACK

BGH

FL0

FL1

FL2

D23

D22

D21

D20

GND

PF1 [MODE B]

GND

PWD

EXT

PF0 [MODE A]

PF2 [MODE C]

PF3

REV. A

ADSP-2189M

The ADSP-2189M package pinout appears in the following table. Pin names in bold text replace the plain text named functions
when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed
in brackets [ ] are state bits latched from the value of the pin at the deassertion of

RESET.

PIN CONFIGURATION

LQFP

Number

Pin Name

Number

Pin Name

Number

Pin Name

Number

Pin Name

A4/IAD3

IRQE + PF4

EBR

D16

A5/IAD4

IRQL0 + PF5

D17

GND

EBG

D18

A6/IAD5

IRQL1 + PF6

D19

A7/IAD6

IRQ2 + PF7

D0/IAD13

GND

A8/IAD7

DT0

D1/IAD14

D20

A9/IAD8

TFS0

D2/IAD15

D21

A10/IAD9

RFS0

D3/IACK

D22

A11/IAD10

DR0

DDINT

D23

A12/IAD11

SCLK0

GND

FL2

A13/IAD12

DDEXT

D4/IS

FL1

GND

DT1

D5/IAL

FL0

CLKIN

TFS1

D6/IRD

PF3 [Mode D]

XTAL

RFS1

D7/IWR

PF2 [Mode C]

DDEXT

DR1

DDEXT

CLKOUT

GND

PWD

GND

SCLK1

DDEXT

GND

DDINT

ERESET

PF1 [Mode B]

RESET

D10

PF0 [Mode A]

EMS

D11

BGH

BMS

GND

PWDACK

DMS

ECLK

D12

PMS

ELOUT

D13

A1/IAD0

IOMS

ELIN

D14

A2/IAD1

CMS

EINT

D15

100

A3/IAD2

REV. A

ADSP-2189M

C3605a

4/00 (rev. A)

PRINTED IN U.S.A.

ORDERING GUIDE

Part Number

Ambient Temperature Range

Instruction Rate

Package Description

Package Option

ADSP-2189MKST-300

°C to +70°C

75 MHz

100-Lead LQFP

ST-100

ADSP-2189MBST-266

°C to +85°C

66 MHz

100-Lead LQFP

ST-100

*In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages

(1.6 mm thick) are now designated as LQFP.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

100-Lead Metric Thin Plastic Quad Flatpack

(ST-100)

SEATING

PLANE

0.030 (0.75)

0.024 (0.60) TYP

0.020 (0.50)

0.063 (1.60) MAX

12
TYP

0.007 (0.177)

0.005 (0.127) TYP

0.003 (0.077)

6 ± 4

0 7

0.003

(0.08)

MAX LEAD

COPLANARITY

TOP VIEW

(PINS DOWN)

100

0.011 (0.27)

0.009 (0.22) TYP

0.007 (0.17)

0.638 (16.20)
0.630 (16.00) TYP SQ
0.622 (15.80)

0.020 (0.50)

BSC

LEAD PITCH

0.553 (14.05)
0.551 (14.00) TYP SQ
0.549 (13.95)

0.472 (12.00) BSC

LEAD WIDTH

NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08) 0.0032 FROM
ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED

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