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DSP Microcomputer

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may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

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Tel:781/329-4700 www.analog.com
Fax:781/326-8703

Analog Devices, Inc., 2002

REV. 0

ADSP-2191M

PERFORMANCE FEATURES
6.25 ns Instruction Cycle Time, for up to 160 MIPS

Sustained Performance

ADSP-218x Family Code Compatible with the Same

Easy to Use Algebraic Syntax

Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-

putation and Memory Instructions

Instruction Cache Allows Dual Operand Fetches in Every

Instruction Cycle

Multifunction Instructions
Pipelined Architecture Supports Efficient Code

Execution

Architectural Enhancements for Compiled C and C++

Code Efficiency

Architectural Enhancements beyond ADSP-218x Family

are Supported with Instruction Set Extensions for
Added Registers, and Peripherals

Flexible Power Management with User-Selectable

Power-Down and Idle Modes

FUNCTIONAL BLOCK DIAGRAM

DATA

ADDRESS

DATA

ADDRESS

SYSTEM INTERRUPT CONTROLLER

I/O DATA

SERIAL PORTS

(3)

SPI PORTS

(2)

I/O REGISTERS

(MEMORY-MAPPED)

CONTROL

STATUS

BUFFERS

I/O PROCESSOR

CACHE

24-BIT

JTAG

TEST &

EMULATION

ADDR BUS

MUX

DATA BUS

MUX

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

ADSP-219x
DSP CORE

PROGRAM

SEQUENCER

DATA

REGISTER

FILE

MULT

BARREL

SHIFTER

ALU

UART PORT

(1)

DMA

CONTROLLER

INPUT

REGISTERS

RESULT

REGISTERS

16-BIT

HOST PORT

DAG1

DAG2

INTERNAL MEMORY

ADDRESS

DATA

ADDRESS

24 BIT

16 BIT

FOUR INDEPENDENT BLOCKS

PROGRAMMABLE

FLAGS (16)

TIMERS (3)

DMA

CONNECT

DMA ADDRESS

EXTERNAL PORT

24 BIT

I/O ADDRESS

DMA DATA

ADSP-2191M

REV. 0

INTEGRATION FEATURES
160 K Bytes On-Chip RAM Configured as 32K Words 24-Bit

Memory RAM and 32K Words 16-Bit Memory RAM

Dual-Purpose 24-Bit Memory for Both Instruction and

Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units with Dual 40-bit
Accumulators

Unified Memory Space Allows Flexible Address Genera-

tion, Using Two Independent DAG Units

Powerful Program Sequencer Provides Zero-Overhead

Looping and Conditional Instruction Execution

Enhanced Interrupt Controller Enables Programming of

Interrupt Priorities and Nesting Modes

SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit

Host Interface

16-Bit External Memory Interface for up to 16M Words of

Addressable Memory Space

Three Full-Duplex Multichannel Serial Ports, with

Support for H.100 and up to 128 TDM Channels with
A-Law and -Law Companding Optimized for Telecom-
munications Systems

Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Inter-

rupt Support

Three Programmable Interval Timers with PWM

Generation, PWM Capture/Pulsewidth Measurement,
and External Event Counter Capabilities

Up to 11 DMA Channels Can Be Active at Any Given Time

for High I/O Throughput

On-Chip Boot ROM for Automatic Booting from External

8- or 16-Bit Host Device, SPI ROM, or UART with
Autobaud Detection

Programmable PLL Supports 1 to 32 Input Frequency

Multiplication and Can Be Altered during Runtime

IEEE JTAG Standard 1149.1 Test Access Port Supports

On-Chip Emulation and System Debugging

2.5 V Internal Operation and 3.3 V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages

TABLE OF CONTENTS

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3

DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .9
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . .10
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12
Instruction Set Description . . . . . . . . . . . . . . . . . . . .13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13
Additional Information . . . . . . . . . . . . . . . . . . . . . . .15

PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ABSOLUTE MAXIMUM RATINGS. . . . . . . . . . . 19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .41
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Environmental Conditions . . . . . . . . . . . . . . . . . . . .42
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .44
144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .46

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .48
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .49

REV. 0

ADSP-2191M

GENERAL DESCRIPTION

The ADSP-2191M DSP is a single-chip microcomputer
optimized for digital signal processing (DSP) and other high
speed numeric processing applications.

The ADSP-2191M combines the ADSP-219x family base
architecture (three computational units, two data address gener-
ators, and a program sequencer) with three serial ports, two
SPI-compatible ports, one UART port, a DMA controller, three
programmable timers, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.

The ADSP-2191M architecture is code-compatible with DSPs
of the ADSP-218x family. Although the architectures are
compatible, the ADSP-2191M architecture has a number of
enhancements over the ADSP-218x architecture. The enhance-
ments to computational units, data address generators, and
program sequencer make the ADSP-2191M more flexible and
even easier to program.

Indirect addressing options provide addressing flexibility--
premodify with no update, pre- and post-modify by an immediate
8-bit, two's-complement value and base address registers for
easier implementation of circular buffering.

The ADSP-2191M integrates 64K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also
provided to reduce power consumption. The ADSP-2191M is
available in 144-lead LQFP and 144-ball mini-BGA packages.

Fabricated in a high-speed, low-power, CMOS process, the
ADSP-2191M operates with a 6.25 ns instruction cycle time
(160 MIPS). All instructions, except single-word instructions,
execute in one processor.

The ADSP-2191M's flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, the ADSP-2191M can:

Generate an address for the next instruction fetch

Fetch the next instruction

Perform one or two data moves

Update one or two data address pointers

Perform a computational operation

These operations take place while the processor continues to:

Receive and transmit data through two serial ports

Receive and/or transmit data from a Host

Receive or transmit data through the UART

Receive or transmit data over two SPI ports

Access external memory through the external memory
interface

Decrement the timers

DSP Core Architecture

The ADSP-2191M instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every single-word instruction can be executed in a
single processor cycle. The ADSP-2191M assembly language

uses an algebraic syntax for ease of coding and readability. A
comprehensive set of development tools supports program
development.

The functional block diagram

on page 1

shows the architecture

of the ADSP-219x core. It contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data from the
register file and have provisions to support multiprecision com-
putations. The ALU performs a standard set of arithmetic and
logic operations; division primitives are also supported. The
MAC performs single-cycle multiply, multiply/add, and multi-
ply/subtract operations. The MAC has two 40-bit accumulators,
which help with overflow. The shifter performs logical and arith-
metic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control, including multiword and
block floating-point representations.

Register-usage rules influence placement of input and results
within the computational units. For most operations, the com-
putational units' data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
the next cycle. For conditional or multifunction instructions,
there are restrictions on which data registers may provide inputs
or receive results from each computational unit. For more infor-
mation, see the ADSP-219x DSP Instruction Set Reference.

A powerful program sequencer controls the flow of instruction
execution. The sequencer supports conditional jumps, subrou-
tine calls, and low interrupt overhead. With internal loop
counters and loop stacks, the ADSP-2191M executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.

Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
16-bit address pointers. Whenever the pointer is used to access
data (indirect addressing), it is pre- or post-modified by the value
of one of four possible modify registers. A length value and base
address may be associated with each pointer to implement
automatic modulo addressing for circular buffers. Page registers
in the DAGs allow circular addressing within 64K word bound-
aries of each of the 256 memory pages, but these buffers may not
cross page boundaries. Secondary registers duplicate all the
primary registers in the DAGs; switching between primary and
secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved with the use of
internal buses:

Program Memory Address (PMA) Bus

Program Memory Data (PMD) Bus

Data Memory Address (DMA) Bus

Data Memory Data (DMD) Bus

DMA Address Bus

DMA Data Bus

ADSP-2191M

REV. 0

The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Boot memory space and I/O memory space also share the
external buses.

Program memory can store both instructions and data, permit-
ting the ADSP-2191M to fetch two operands in a single cycle,
one from program memory and one from data memory. The
DSP's dual memory buses also let the ADSP-219x core fetch an
operand from data memory and the next instruction from
program memory in a single cycle.

DSP Peripherals Architecture

The functional block diagram

on page 1

shows the DSP's

on-chip peripherals, which include the external memory inter-
face, Host port, serial ports, SPI-compatible ports, UART port,
JTAG test and emulation port, timers, flags, and interrupt con-
troller. These on-chip peripherals can connect to off-chip devices
as shown in

Figure 1

The ADSP-2191M has a 16-bit Host port with DMA capability
that lets external Hosts access on-chip memory. This 24-pin
parallel port consists of a 16-pin multiplexed data/address bus
and provides a low-service overhead data move capability. Con-
figurable for 8 or 16 bits, this port provides a glueless interface
to a wide variety of 8- and 16-bit microcontrollers. Two
chip-selects provide Hosts access to the DSP's entire memory
map. The DSP is bootable through this port.

The ADSP-2191M also has an external memory interface that is
shared by the DSP's core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The external
port consists of a 16-bit data bus, a 22-bit address bus, and
control signals. The data bus is configurable to provide an 8 or
16 bit interface to external memory. Support for word packing
lets the DSP access 16- or 24-bit words from external memory
regardless of the external data bus width. When configured for
an 8-bit interface, the unused eight lines provide eight program-
mable, bidirectional general-purpose Programmable Flag lines,
six of which can be mapped to software condition signals.

The memory DMA controller lets the ADSP-2191M move data
and instructions from between memory spaces: internal-to-exter-
nal, internal-to-internal, and external-to- external. On-chip
peripherals can also use this controller for DMA transfers.

The ADSP-2191M can respond to up to seventeen interrupts at
any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. The programmer assigns a
peripheral to one of the 12 user-defined interrupts. The priority
of each peripheral for interrupt service is determined by these
assignments.

There are three serial ports on the ADSP-2191M that provide a
complete synchronous, full-duplex serial interface. This interface
includes optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of opera-

tion. Each serial port can transmit or receive an internal or
external, programmable serial clock and frame syncs. Each serial
port supports 128-channel Time Division Multiplexing.

The ADSP-2191M provides up to sixteen general-purpose I/O
pins, which are programmable as either inputs or outputs. Eight
of these pins are dedicated-general purpose Programmable Flag
pins. The other eight of them are multifunctional pins, acting as
general-purpose I/O pins when the DSP connects to an 8-bit
external data bus and acting as the upper eight data pins when
the DSP connects to a 16-bit external data bus. These Program-
mable Flag pins can implement edge- or level-sensitive
interrupts, some of which can be used to base the execution of
conditional instructions.

Figure 1. System Diagram

S ERIAL
DEVICE

( O P TI O N A L )

DAT A158

IOMS

ADSP-2191M

BMS

MS30

AC K

ADD R210

DAT A70

D ATA158

A DDR210

D ATA70

ACK

EXT ERN AL

ME MO RY

( O PT I O N A L )

D ATA158

A DDR210

D ATA70

ACK

BO OT

ME MO RY

( O PT I O N A L )

D ATA158

A DDR170

D ATA70

ACK

E XT ER NAL

I/O MEMOR Y

( O P TI O N A L )

ADDR16

A DDR150/
D ATA150

CS1

ACK

HOS T

PRO CESSO R

( O P TI O N A L )

CS0

ALE

H AD150

HA16

HCMS

HCIOMS

HRD

HWR

HA CK

H ALE

HACK_P

T CLK0

T FS0

DT 0

RC LK0

RF S0

DR 0

T CLK1

T FS1

DT 1

RC LK1

RF S1

DR 1

T CLK2/S CK0

T FS2/MOSI0

DT 2/MISO 0

RC LK2/S CK1

RF S2/ MO SI1

DR 2/MIS O 1

RX D

T XD

RE SE T

JT AG

SPO RT1

SPO RT2

SPO RT0

CL KIN

XTA L

MS EL60/P F60

DF /P F7

BY PASS

BMO DE10

O P MO DE

CL KOUT

T MR20

UART

SP I0

SP I1

S ERIAL
DEV ICE

( O P T I O N A L)

S ERIAL
DEV ICE

( O P T I O N A L)

U ART

DEV ICE

( O P T I O N A L)

CLO CK

O R

CRYS TAL

T IMER

OUT OR

CAPTURE

CLO CK

MULTIPL Y

AN D

RAN GE

BO OT

AND O P

MODE

BGH

REV. 0

ADSP-2191M

Three programmable interval timers generate periodic inter-
rupts. Each timer can be independently set to operate in one of
three modes:

Pulse Waveform Generation mode

Pulsewidth Count/Capture mode

External Event Watchdog mode

Each timer has one bidirectional pin and four registers that
implement its mode of operation: A 7-bit configuration register,
a 32-bit count register, a 32-bit period register, and a 32-bit
pulsewidth register. A single status register supports all three
timers. A bit in each timer's configuration register enables or
disables the corresponding timer independently of the others.

Memory Architecture

The ADSP-2191M DSP provides 64K words of on-chip SRAM
memory. This memory is divided into four 16K blocks located
on memory Page 0 in the DSP's memory map. In addition to the

internal and external memory space, the ADSP-2191M can
address two additional and separate off-chip memory spaces: I/O
space and boot space.

As shown in

Figure 2

, the DSP's two internal memory blocks

populate all of Page 0. The entire DSP memory map consists of
256 pages (Pages 0

255), and each page is 64K words long.

External memory space consists of four memory banks (banks
03) and supports a wide variety of SRAM memory devices. Each
bank is selectable using the memory select pins (

MS30) and has

configurable page boundaries, waitstates, and waitstate modes.
The 1K word of on-chip boot-ROM populates the top of
Page 255 while the remaining 254 pages are addressable off-chip.
I/O memory pages differ from external memory pages in that I/O
pages are 1K word long, and the external I/O pages have their
own select pin (

IOMS). Pages 07 of I/O memory space reside

on-chip and contain the configuration registers for the peripher-
als. Both the core and DMA-capable peripherals can access the
DSP's entire memory map.

Internal (On-Chip) Memory

The ADSP-2191M's unified program and data memory space
consists of 16M locations that are accessible through two 24-bit
address buses, the PMA and DMA buses. The DSP uses slightly

Figure 2. Memory Map

BANK3

(MS3)

BANK2

(MS2)

BANK1

(MS1)

BANK0

(MS0)

BLOCK0, 24-BIT

BLOCK2, 16-BIT

BLOCK1, 24-BIT

BLOCK3, 16-BIT

RESERVED

BOOT ROM, 24-BIT

0 00 4000

0 00 8000

0 01 0000

0 40 0000

0 80 0000

0 C0 0000

0 FF 0000

0 FF 0400

0 FF FFFF

LOGICAL

ADDRESS

64K WORD

MEMORY

PAGES

PAGE 0

PAGES 163

PAGES 64127

PAGES 128191

PAGES 192254

PAGE 255

INTERNAL

MEMORY

EXTERNAL

MEMORY

(16- BIT)

INTERNAL

MEMORY

MEMORY SELECTS

(MS)

FOR PORTIONS OF THE

MEMORY MAP APPEAR

WITH THE SELECTED

MEMORY.

PAGES 1254

0 01 0000

0 FE FFFF

I/O MEMORY

16- BIT

1K WORD

PAGES 8255

1K WORD

PAGES 07

LOWER PAGE BOUNDARIES

ARE CONFIGURABLE FOR

BANKS OF EXTERNAL MEMORY.

BOUNDARIES SHOWN ARE

BANK SIZES AT RESET.

0 07 3FF

0 08 000

0 FF 3FF

INTERNAL

EXTERNAL

(IOMS)

0 00 0000

0 00 C000

0 FF 03FF

0 00 000

8-BIT 10-BIT

BOOT MEMORY

16-BIT

(BMS)

64K WORD

LOGICAL

ADDRESS

LOGICAL

ADDRESS

ADSP-2191M

REV. 0

different mechanisms to generate a 24-bit address for each bus.
The DSP has three functions that support access to the full
memory map.

The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG's DMPGx register to the
appropriate memory page.

The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.

For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer's IJPG register to the
appropriate memory page.

The ADSP-2191M has 1K word of on-chip ROM that holds boot
routines. If peripheral booting is selected, the DSP starts
executing instructions from the on-chip boot ROM, which starts
the boot process from the selected peripheral.

For more informa-

tion, see "Booting Modes" on page 11.

The on-chip boot ROM

is located on Page 255 in the DSP's memory space map.

External (Off-Chip) Memory

Each of the ADSP-2191M's off-chip memory spaces has a
separate control register, so applications can configure unique
access parameters for each space. The access parameters include
read and write wait counts, waitstate completion mode, I/O clock
divide ratio, write hold time extension, strobe polarity, and data
bus width. The core clock and peripheral clock ratios influence
the external memory access strobe widths.

For more information,

see "Clock Signals" on page 11.

The off-chip memory spaces are:

External memory space (

MS30 pins)

I/O memory space (

IOMS pin)

Boot memory space (

BMS pin)

All of these off-chip memory spaces are accessible through the
External Port, which can be configured for data widths of
8 or 16 bits.

External Memory Space

External memory space consists of four memory banks. These
banks can contain a configurable number of 64K word pages. At
reset, the page boundaries for external memory have Bank0
containing pages 1

63, Bank1 containing pages 64

127, Bank2

containing pages 128

191, and Bank3 that contains pages

192

254. The

MS30 memory bank pins select Banks 30,

respectively. The external memory interface is byte-addressable
and decodes the 8 MSBs of the DSP program address to select
one of the four banks. Both the ADSP-219x core and DMA-capa-
ble peripherals can access the DSP's external memory space.

I/O Memory Space

The ADSP-2191M supports an additional external memory
called I/O memory space. This space is designed to support
simple connections to peripherals (such as data converters and
external registers) or to bus interface ASIC data registers. I/O
space supports a total of 256K locations. The first 8K addresses
are reserved for on-chip peripherals. The upper 248K addresses
are available for external peripheral devices. The DSP's instruc-
tion set provides instructions for accessing I/O space. These
instructions use an 18-bit address that is assembled from an
8-bit I/O page (IOPG) register and a 10-bit immediate value
supplied in the instruction. Both the ADSP-219x core and a Host
(through the Host Port Interface) can access I/O memory space.

Boot Memory Space

Boot memory space consists of one off-chip bank with 63 pages.
The

BMS memory bank pin selects boot memory space. Both

the ADSP-219x core and DMA-capable peripherals can access
the DSP's off-chip boot memory space. After reset, the DSP
always starts executing instructions from the on-chip boot ROM.
Depending on the boot configuration, the boot ROM code can
start booting the DSP from boot memory.

For more information,

see "Booting Modes" on page 11.

Interrupts

The interrupt controller lets the DSP respond to 17 interrupts
with minimum overhead. The controller implements an interrupt
priority scheme as shown in

Table 1

. Applications can use the

unassigned slots for software and peripheral interrupts.

Table 2

shows the ID and priority at reset of each of the periph-

eral interrupts. To assign the peripheral interrupts a different
priority, applications write the new priority to their correspond-
ing control bits (determined by their ID) in the Interrupt Priority
Control register. The peripheral interrupt's position in the
IMASK and IRPTL register and its vector address depend on its
priority level, as shown in

Table 1

. Because the IMASK and

IRPTL registers are limited to 16 bits, any peripheral interrupts

REV. 0

ADSP-2191M

assigned a priority level of 11 are aliased to the lowest priority bit
position (15) in these registers and share vector address
0x00 01E0.

Interrupt routines can either be nested with higher priority inter-
rupts taking precedence or processed sequentially. Interrupts can
be masked or unmasked with the IMASK register. Individual
interrupt requests are logically ANDed with the bits in IMASK;
the highest priority unmasked interrupt is then selected. The
emulation, power-down, and reset interrupts are nonmaskable
with the IMASK register, but software can use the DIS INT
instruction to mask the power-down interrupt.

The Interrupt Control (ICNTL) register controls interrupt
nesting and enables or disables interrupts globally.

The general-purpose Programmable Flag (PFx) pins can be con-
figured as outputs, can implement software interrupts, and (as
inputs) can implement hardware interrupts. Programmable Flag
pin interrupts can be configured for level-sensitive, single
edge-sensitive, or dual edge-sensitive operation.

The IRPTL register is used to force and clear interrupts. On-chip
stacks preserve the processor status and are automatically main-
tained during interrupt handling. To support interrupt, loop, and
subroutine nesting, the PC stack is 33 levels deep, the loop stack
is eight levels deep, and the status stack is 16 levels deep. To
prevent stack overflow, the PC stack can generate a stack-level
interrupt if the PC stack falls below three locations full or rises
above 28 locations full.

The following instructions globally enable or disable interrupt
servicing, regardless of the state of IMASK.

ENA INT;

DIS INT;

At reset, interrupt servicing is disabled.

For quick servicing of interrupts, a secondary set of DAG and
computational registers exist. Switching between the primary
and secondary registers lets programs quickly service interrupts,
while preserving the DSP's state.

DMA Controller

The ADSP-2191M has a DMA controller that supports
automated data transfers with minimal overhead for the DSP
core. Cycle stealing DMA transfers can occur between the
ADSP-2191M's internal memory and any of its DMA-capable
peripherals. Additionally, DMA transfers can be accomplished
between any of the DMA-capable peripherals and external
devices connected to the external memory interface. DMA-capa-
ble peripherals include the Host port, SPORTs, SPI ports, and
UART. Each individual DMA-capable peripheral has a dedicated
DMA channel. To describe each DMA sequence, the DMA con-
troller uses a set of parameters--called a DMA descriptor. When
successive DMA sequences are needed, these DMA descriptors
can be linked or chained together, so the completion of one DMA
sequence auto-initiates and starts the next sequence. DMA
sequences do not contend for bus access with the DSP core;
instead DMAs "steal" cycles to access memory.

Table 1. Interrupt Priorities/Addresses

Interrupt

IMASK/
IRPTL

Vector
Address

These interrupt vectors start at address 0x10000 when the DSP is in

"no-boot," run from external memory mode.

Emulator (NMI)--
Highest Priority

Reset (NMI)

0x00 0000

Power-Down (NMI)

0x00 0020

Loop and PC Stack

0x00 0040

Emulation Kernel

0x00 0060

User Assigned Interrupt

0x00 0080

User Assigned Interrupt

0x00 00A0

User Assigned Interrupt

0x00 00C0

User Assigned Interrupt

0x00 00E0

User Assigned Interrupt

0x00 0100

User Assigned Interrupt

0x00 0120

User Assigned Interrupt

0x00 0140

User Assigned Interrupt

0x00 0160

User Assigned Interrupt

0x00 0180

User Assigned Interrupt

0x00 01A0

User Assigned Interrupt

0x00 01C0

User Assigned Interrupt--
Lowest Priority

0x00 01E0

Table 2. Peripheral Interrupts and Priority at Reset

Interrupt

Reset
Priority

Slave DMA/Host Port Interface

SPORT0 Receive

SPORT0 Transmit

SPORT1 Receive

SPORT1 Transmit

SPORT2 Receive/SPI0

SPORT2 Transmit/SPI1

UART Receive

UART Transmit

Timer 0

Timer 1

Timer 2

Programmable Flag A (any PFx)

Programmable Flag B (any PFx)

Memory DMA port

Table 3. Interrupt Control (ICNTL) Register Bits

Bit

Description

Reserved

Interrupt Nesting Enable

Global Interrupt Enable

Reserved

MAC-Biased Rounding Enable

Reserved

PC Stack Interrupt Enable

Loop Stack Interrupt Enable

1215

Reserved

ADSP-2191M

REV. 0

All DMA transfers use the DMA bus shown in the functional
block diagram

on page 1

. Because all of the peripherals use the

same bus, arbitration for DMA bus access is needed. The arbi-
tration for DMA bus access appears in

Table 4

Host Port

The ADSP-2191M's Host port functions as a slave on the
external bus of an external Host. The Host port interface lets a
Host read from or write to the DSP's memory space, boot space,
or internal I/O space. Examples of Hosts include external micro-
controllers, microprocessors, or ASICs.

The Host port is a multiplexed address and data bus that provides
both an 8-bit and a 16-bit data path and operates using an asyn-
chronous transmission protocol. Through this port, an off-chip
Host can directly access the DSP's entire memory space map,
boot memory space, and internal I/O space. To access the DSP's
internal memory space, a Host steals one cycle per access from
the DSP. A Host access to the DSP's external memory uses the
external port interface and does not stall (or steal cycles from)
the DSP's core. Because a Host can access internal I/O memory
space, a Host can control any of the DSP's I/O mapped
peripherals.

The Host port is most efficient when using the DSP as a slave
and uses DMA to automate the incrementing of addresses for
these accesses. In this case, an address does not have to be trans-
ferred from the Host for every data transfer.

Host Port Acknowledge (HACK) Modes

The Host port supports a number of modes (or protocols) for
generating a HACK output for the host. The host selects ACK
or Ready Modes using the HACK_P and HACK pins. The Host
port also supports two modes for address control: Address Latch
Enable (ALE) and Address Cycle Control (ACC) modes. The
DSP auto-detects ALE versus ACC Mode from the HALE and
HWR inputs.

The Host port HACK signal polarity is selected (only at reset) as
active high or active low, depending on the value driven on the
HACK_P pin.The HACK polarity is stored into the Host port
configuration register as a read only bit.

The DSP uses HACK to indicate to the Host when to complete
an access. For a read transaction, a Host can proceed and
complete an access when valid data is present in the read buffer
and the Host port is not busy doing a write. For a write transac-
tions, a Host can complete an access when the write buffer is not
full and the Host port is not busy doing a write.

Two mode bits in the Host Port configuration register HPCR
[7:6] define the functionality of the HACK line. HPCR6 is ini-
tialized at reset based on the values driven on HACK and
HACK_P pins (shown in

Table 5

); HPCR7 is always cleared (0)

at reset. HPCR [7:6] can be modified after reset by a write access
to the Host port configuration register.

The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):

ACK Mode--Acknowledge is active on strobes; HACK
goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The Host port then removes the HACK.

Ready Mode--Ready active on strobes, goes low to insert
waitstate during the access.If the Host port cannot
complete the access, it deasserts the HACK/READY line.
In this case, the Host has to extend the access by keeping
the strobe asserted. When the Host samples the HACK
asserted, it can then proceed and complete the access by
deasserting the strobe.

While in Address Cycle Control (ACC) mode and the ACK or
Ready acknowledge modes, the HACK is returned active for any
address cycle.

Host Port Chip Selects

There are two chip-select signals associated with the Host port:
HCMS and HCIOMS. The Host Chip Memory Select (HCMS)
lets the Host select the DSP and directly access the DSP's inter-
nal/external memory space or boot memory space. The Host
Chip I/O Memory Select (

HCIOMS) lets the Host select the DSP

and directly access the DSP's internal I/O memory space.

Before starting a direct access, the Host configures Host port
interface registers, specifying the width of external data bus
(8- or 16-bit) and the target address page (in the IJPG register).
The DSP generates the needed memory select signals during the
access, based on the target address. The Host port interface
combines the data from one, two, or three consecutive Host
accesses (up to one 24-bit value) into a single DMA bus access
to prefetch Host direct reads or to post direct writes. During
assembly of larger words, the Host port interface asserts ACK for

Table 4. I/O Bus Arbitration Priority

DMA Bus Master

Arbitration Priority

SPORT0 Receive DMA

0--Highest

SPORT1 Receive DMA

SPORT2 Receive DMA

SPORT0 Transmit DMA

SPORT1 Transmit DMA

SPORT2 Transmit DMA

SPI0 Receive/Transmit DMA

SPI1 Receive/Transmit DMA

UART Receive DMA

UART Transmit DMA

Host Port DMA

Memory DMA

11--Lowest

Table 5. Host Port Acknowledge Mode Selection

Values Driven At
Reset

HPCR [7:6]
Initial Values

Acknowledge
Mode

HACK_P

HACK

Bit 7

Bit 6

Ready Mode

ACK Mode

Ready Mode

REV. 0

ADSP-2191M

each byte access that does not start a read or complete a write.
Otherwise, the Host port interface asserts ACK when it has
completed the memory access successfully.

DSP Serial Ports (SPORTs)

The ADSP-2191M incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial and
multiprocessor communications. The SPORTs support the
following features:

Bidirectional operation--each SPORT has independent
transmit and receive pins.

Double-buffered transmit and receive ports--each port
has a data register for transferring data words to and from
memory and shift registers for shifting data in and out of
the data registers.

Clocking--each transmit and receive port can either use
an external serial clock (

MHz) or generate its own, in

frequencies ranging from 19 Hz to 40 MHz.

Word length--each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.

Framing--each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active
high or low, and with either of two pulsewidths and early
or late frame sync.

Companding in hardware--each SPORT can perform
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.

DMA operations with single-cycle overhead--each
SPORT can automatically receive and transmit multiple
buffers of memory data, one data word each DSP cycle.
Either the DSP's core or a Host processor can link or chain
sequences of DMA transfers between a SPORT and
memory. The chained DMA can be dynamically allocated
and updated through the DMA descriptors (DMA
transfer parameters) that set up the chain.

Interrupts--each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.

Multichannel capability--each SPORT supports the
H.100 standard.

Serial Peripheral Interface (SPI) Ports

The DSP has two SPI-compatible ports that enable the DSP to
communicate with multiple SPI-compatible devices. These ports
are multiplexed with SPORT2, so either SPORT2 or the SPI
ports are active, depending on the state of the OPMODE pin
during hardware reset.

The SPI interface uses three pins for transferring data: two data
pins (Master Output-Slave Input, MOSIx, and Master
Input-Slave Output, MISOx) and a clock pin (Serial Clock,

SCKx). Two SPI chip select input pins (

SPISSx) let other SPI

devices select the DSP, and fourteen SPI chip select output pins
(SPIxSEL71) let the DSP select other SPI devices. The SPI
select pins are reconfigured Programmable Flag pins. Using these
pins, the SPI ports provide a full duplex, synchronous serial inter-
face, which supports both master and slave modes and
multimaster environments.

Each SPI port's baud rate and clock phase/polarities are program-
mable (see equation below for SPI clock rate calculation), and
each has an integrated DMA controller, configurable to support
both transmit and receive data streams. The SPI's DMA control-
ler can only service unidirectional accesses at any given time.

During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial data
lines. The serial clock line synchronizes the shifting and sampling
of data on the two serial data lines.

UART Port

The UART port provides a simplified UART interface to another
peripheral or Host. It performs full duplex, asynchronous
transfers of serial data. Options for the UART include support
for 58 data bits; 1 or 2 stop bits; and none, even, or odd parity.
The UART port supports two modes of operation:

Programmed I/O

The DSP's core sends or receives data by writing or
reading I/O-mapped THR or RBR registers, respectively.
The data is double-buffered on both transmit and receive.

DMA (direct memory access)

The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.

The UART's baud rate (see following equation for UART clock
rate calculation), serial data format, error code generation and
status, and interrupts are programmable:

Supported bit rates range from 9.5 bits to 5M bits per
second (80 MHz peripheral clock).

Supported data formats are 7- to 12-bit frames.

Transmit and receive status can be configured to generate
maskable interrupts to the DSP's core.

The timers can be used to provide a hardware-assisted autobaud
detection mechanism for the UART interface.

Where D is the programmable divisor = 1 to 65536.

SPI Clock Rate

HCLK

SPIBAUD

---------------------------------------

UART Clock Rate

HCLK

------------------

ADSP-2191M

REV. 0

Programmable Flag (PFx) Pins

The ADSP-2191M has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF150) pins. The PF70 pins are
dedicated to general-purpose I/O. The PF158 pins serve either
as general-purpose I/O pins (if the DSP is connected to an 8-bit
external data bus) or serve as DATA158 lines (if the DSP is
connected to a 16-bit external data bus). The Programmable Flag
pins have special functions for clock multiplier selection and for
SPI port operation. For more information, see

Serial Peripheral

Interface (SPI) Ports on page 9

and

Clock Signals on page 11

Ten memory-mapped registers control operation of the Program-
mable Flag pins:

Flag Direction register

Specifies the direction of each individual PFx pin as input
or output.

Flag Control and Status registers

Specify the value to drive on each individual PFx output
pin. As input, software can predicate instruction
execution on the value of individual PFx input pins
captured in this register. One register sets bits, and one
register clears bits.

Flag Interrupt Mask registers

Enable and disable each individual PFx pin to function
as an interrupt to the DSP's core. One register sets bits to
enable interrupt function, and one register clears bits to
disable interrupt function. Input PFx pins function as
hardware interrupts, and output PFx pins function as
software interrupts--latching in the IMASK and IRPTL
registers.

Flag Interrupt Polarity register

Specifies the polarity (active high or low) for interrupt
sensitivity on each individual PFx pin.

Flag Sensitivity registers

Specify whether individual PFx pins are level- or
edge-sensitive and specify--if edge-sensitive--whether
just the rising edge or both the rising and falling edges of
the signal are significant. One register selects the type of
sensitivity, and one register selects which edges are signif-
icant for edge-sensitivity.

Low Power Operation

The ADSP-2191M has four low-power options that significantly
reduce the power dissipation when the device operates under
standby conditions. To enter any of these modes, the DSP
executes an IDLE instruction. The ADSP-2191M uses configu-
ration of the PDWN, STOPCK, and STOPALL bits in the
PLLCTL register to select between the low-power modes as the
DSP executes the IDLE. Depending on the mode, an IDLE shuts
off clocks to different parts of the DSP in the different modes.
The low power modes are:

Idle

Power-Down Core

Power-Down Core/Peripherals

Power-Down All

Idle Mode

When the ADSP-2191M is in Idle mode, the DSP core stops
executing instructions, retains the contents of the instruction
pipeline, and waits for an interrupt. The core clock and peripheral
clock continue running.

To enter Idle mode, the DSP can execute the IDLE instruction
anywhere in code. To exit Idle mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.

Power-Down Core Mode

When the ADSP-2191M is in Power-Down Core mode, the DSP
core clock is off, but the DSP retains the contents of the pipeline
and keeps the PLL running. The peripheral bus keeps running,
letting the peripherals receive data.

To enter Power-Down Core mode, the DSP executes an IDLE
instruction after performing the following tasks:

Enter a power-down interrupt service routine

Check for pending interrupts and I/O service routines

Clear (= 0) the PDWN bit in the PLLCTL register

Clear (= 0) the STOPALL bit in the PLLCTL register

Set (= 1) the STOPCK bit in the PLLCTL register

To exit Power-Down Core mode, the DSP responds to an
interrupt and (after two cycles of latency) resumes executing
instructions with the instruction after the IDLE.

Power-Down Core/Peripherals Mode

When the ADSP-2191M is in Power-Down Core/Peripherals
mode, the DSP core clock and peripheral bus clock are off, but
the DSP keeps the PLL running. The DSP does not retain the
contents of the instruction pipeline.The peripheral bus is
stopped, so the peripherals cannot receive data.

To enter Power-Down Core/Peripherals mode, the DSP executes
an IDLE instruction after performing the following tasks:

Enter a power-down interrupt service routine

Check for pending interrupts and I/O service routines

Clear (= 0) the PDWN bit in the PLLCTL register

Set (= 1) the STOPALL bit in the PLLCTL register

To exit Power-Down Core/Peripherals mode, the DSP responds
to a wake-up event and (after five to six cycles of latency) resumes
executing instructions with the instruction after the IDLE.

Power-Down All Mode

When the ADSP-2191M is in Power-Down All mode, the DSP
core clock, the peripheral clock, and the PLL are all stopped. The
DSP does not retain the contents of the instruction pipeline. The
peripheral bus is stopped, so the peripherals cannot receive data.

To enter Power-Down All mode, the DSP executes an IDLE
instruction after performing the following tasks:

Enter a power-down interrupt service routine

Check for pending interrupts and I/O service routines

Set (= 1) the PDWN bit in the PLLCTL register

REV. 0

ADSP-2191M

To exit Power-Down Core/Peripherals mode, the DSP responds
to an interrupt and (after 500 cycles to restabilize the PLL)
resumes executing instructions with the instruction after the
IDLE.

Clock Signals

The ADSP-2191M can be clocked by a crystal oscillator or a
buffered, shaped clock derived from an external clock oscillator.
If a crystal oscillator is used, the crystal should be connected
across the CLKIN and XTAL pins, with two capacitors and a
1 M

shunt resistor connected as shown in

Figure 3

. Capacitor

values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre-
quency, microprocessor-grade crystal should be used for this
configuration.

If a buffered, shaped clock is used, this external clock connects
to the DSP's CLKIN pin. CLKIN input cannot be halted,
changed, or operated below the specified frequency during
normal operation. When an external clock is used, the XTAL
input must be left unconnected.

The DSP provides a user-programmable 1 to 32 multiplica-
tion of the input clock, including some fractional values, to
support 128 external to internal (DSP core) clock ratios. The
MSEL60, BYPASS, and DF pins decide the PLL multiplication
factor at reset. At runtime, the multiplication factor can be con-
trolled in software. The combination of pullup and pull-down
resistors in

Figure

sets up a core clock ratio of 6:1, which

produces a 150 MHz core clock from the 25 MHz input. For
other clock multiplier settings, see the ADSP-219x/2191 DSP
Hardware Reference.

The peripheral clock is supplied to the CLKOUT pin.

All on-chip peripherals for the ADSP-2191M operate at the rate
set by the peripheral clock. The peripheral clock is either equal
to the core clock rate or one-half the DSP core clock rate. This
selection is controlled by the IOSEL bit in the PLLCTL register.
The maximum core clock is 160 MHz and the maximum periph-
eral clock is 80 MHz--the combination of the input clock and
core/peripheral clock ratios may not exceed these limits.

Reset

The

RESET signal initiates a master reset of the ADSP-2191M.

The

RESET signal must be asserted during the powerup

sequence to assure proper initialization.

RESET during initial

powerup must be held long enough to allow the internal clock to
stabilize.

The powerup sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V

is applied

to the processor, and for the internal phase-locked loop (PLL) to
lock onto the specific crystal frequency. A minimum of 100 µs
ensures that the PLL has locked, but does not include the crystal
oscillator start-up time. During this powerup sequence the
RESET signal should be held low. On any subsequent resets, the
RESET signal must meet the minimum pulsewidth specifica-
tion, t

WRST

The

RESET input contains some hysteresis. If using an RC

circuit to generate your

RESET signal, the circuit should use an

external Schmidt trigger.

The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts, and resets all registers to their
default values (where applicable). When

RESET is released, if

there is no pending bus request and the chip is configured for
booting, the boot-loading sequence is performed. Program
control jumps to the location of the on-chip boot ROM
(0xFF 0000).

Power Supplies

The ADSP-2191M has separate power supply connections for
the internal (V

DDINT

) and external (V

DDEXT

) power supplies.

The internal supply must meet the 2.5 V requirement. The
external supply must be connected to a 3.3 V supply. All external
supply pins must be connected to the same supply.

Powerup Sequence

Power up together the two supplies V

DDEXT

and V

DDINT

. If

they cannot be powered up together, power up the internal (core)
supply first (powering up the core supply first reduces the risk of
latchup events.

Booting Modes

The ADSP-2191M has five mechanisms (listed in

Table 6

) for

automatically loading internal program memory after reset. Two
No-boot modes are also supported.

Figure 3. External Crystal Connections

CLKIN

CLKOUT

XTAL

ADSP-2191M

MSEL5 (PF5)

MSEL4 (PF4)

MSEL3 (PF3)

MSEL2 (PF2)

MSEL1 (PF1)

MSEL0 (PF0)

RESET

25MHz

MSEL6 (PF6)

DF (PF7)

BYPASS

RESET
SOURCE

RUNTIME
PF PIN I/O

THE PULL-UP/PULL-DOWN
RESISTORS ON THE MSEL,
DF, AND BYPASS PINS
SELECT THE CORE CLOCK
RATIO.

HERE, THE SELECTION (6:1)
AND 25MHz INPUT CLOCK
PRODUCE A 150MHz CORE
CLOCK.

ADSP-2191M

REV. 0

The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configuration
Register implement these modes:

Execute from memory external 16 bits--The memory
boot routine located in boot ROM memory space
executes a boot-stream-formatted program located at
address 0x010000 of boot memory space, packing 16-bit
external data into 24-bit internal data. The External Port
Interface is configured for the default clock multiplier
(128) and read waitstates (7).

Boot from EPROM--The EPROM boot routine located
in boot ROM memory space fetches a boot-stream-for-
matted program located at physical address 0x00 0000 of
boot memory space, packing 8- or 16-bit external data
into 24-bit internal data. The External Port Interface is
configured for the default clock multiplier (32) and read
waitstates (7).

Boot from Host--The (8- or 16-bit) Host downloads a
boot-stream-formatted program to internal or external
memory. The Host's boot routine is located in internal
ROM memory space and uses the top 16 locations of
Page 0 program memory and the top 272 locations of
Page 0 data memory.

The internal boot ROM sets semaphore A (an IO register
within the Host port) and then polls until the semaphore
is reset. Once detected, the internal boot ROM will remap
the interrupt vector table to Page 0 internal memory and
jump to address 0x00 0000 internal memory. From the
point of view of the host interface, an external host has
full control of the DSP's memory map. The Host has the
freedom to directly write internal memory, external
memory, and internal I/O memory space. The DSP core
execution is held off until the Host clears the semaphore
register. This strategy allows the maximum flexibility for
the Host to boot in the program and data code, by leaving
it up to the programmer.

Execute from memory external 8 bits (No Boot)--
Execution starts from Page 1 of external memory space,
packing either 8- or 16-bit external data into 24-bit
internal data. The External Port Interface is config-
ured for the default clock multiplier (128) and read
waitstates (7).

Boot from UART--The Host downloads
boot-stream-formatted program using an autobaud
handshake sequence. The Host agent selects a baud rate
within the UART's clocking capabilities. After a hardware
reset, the DSP's UART expects a 0xAA character (eight
bits data, one start bit, one stop bit, no parity bit) on the
RXD pin to determine the bit rate; and then replies with
an OK string. Once the host receives this OK it downloads
the boot stream without further handshake.The UART
boot routine is located in internal ROM memory space
and uses the top 16 locations of Page 0 program memory
and the top 272 locations of Page 0 data memory.

Boot from SPI, up to 4K bits--The SPI0 port uses the
SPI0SEL1 (reconfigured PF2) output pin to select a
single serial EEPROM device, submits a read command
at address 0x00, and begins clocking consecutive data into
internal or external memory. Use only SPI-compatible
EEPROMs of

4K bit (12-bit address range). The SPI0

boot routine located in internal ROM memory space
executes a boot-stream-formatted program, using the top
16 locations of Page 0 program memory and the top 272
locations of Page 0 data memory. The SPI boot configu-
ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,
8-bit data, and MSB first.

Boot from SPI, from >4K bits to 512K bits--The SPI0
port uses the SPI0SEL1 (re-configured PF2) output pin
to select a single serial EEPROM device, submits a read
command at address 0x00, and begins clocking consecu-
tive data into internal or external memory. Use only
SPI-compatible EEPROMs of

4K bit (16-bit address

range). The SPI0 boot routine, located in internal ROM
memory space, executes a boot-stream-formatted
program, using the top 16 locations of Page 0 program
memory and the top 272 locations of Page 0 data memory.

As indicated in

Table 6

, the OPMODE pin has a dual role, acting

as a boot mode select during reset and determining SPORT or
SPI operation at runtime. If the OPMODE pin at reset is the
opposite of what is needed in an application during runtime, the
application needs to set the OPMODE bit appropriately during
runtime prior to using the corresponding peripheral.

Bus Request and Bus Grant

The ADSP-2191M can relinquish control of the data and address
buses to an external device. When the external device requires
access to the bus, it asserts the bus request (

BR) signal. The (BR)

signal is arbitrated with core and peripheral requests. External
Bus requests have the lowest priority. If no other internal request
is pending, the external bus request will be granted. Because of

Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)

OPMODE

BMO

Function

Execute from external memory 16 bits
(No Boot)

Boot from EPROM

Boot from Host

Reserved

Execute from external memory 8 bits
(No Boot)

Boot from UART

Boot from SPI, up to 4K bits

Boot from SPI, >4K bits up to
512K bits

REV. 0

ADSP-2191M

synchronizer and arbitration delays, bus grants will be provided
with a minimum of three peripheral clock delays. ADSP-2191M
DSPs will respond to the bus grant by:

Three-stating the data and address buses and the

MS30,

BMS, IOMS, RD, and WR output drivers.

Asserting the bus grant (

BG) signal.

The ADSP-2191M will halt program execution if the bus is
granted to an external device and an instruction fetch or data
read/write request is made to external general-purpose or periph-
eral memory spaces. If an instruction requires two external
memory read accesses, bus requests will not be granted between
the two accesses. If an instruction requires an external memory
read and an external memory write access, the bus may be
granted between the two accesses. The external memory
interface can be configured so that the core will have exclusive
use of the interface. DMA and Bus Requests will be granted.
When the external device releases

BR, the DSP releases BG and

continues program execution from the point at which it stopped.

The bus request feature operates at all times, even while the DSP
is booting and

RESET is active.

The ADSP-2191M asserts the

BGH pin when it is ready to start

another external port access, but is held off because the bus was
previously granted. This mechanism can be extended to define
more complex arbitration protocols for implementing more
elaborate multimaster systems.

Instruction Set Description

The ADSP-2191M assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
processor's unique architecture, offers the following benefits:

ADSP-219x assembly language syntax is a superset of and
source-code-compatible (except for two data registers
and DAG base address registers) with ADSP-218x family
syntax. It may be necessary to restructure ADSP-218x
programs to accommodate the ADSP-2191M's unified
memory space and to conform to its interrupt vector map.

The algebraic syntax eliminates the need to remember
cryptic assembler mnemonics. For example, a typical
arithmetic add instruction, such as AR = AX0 + AY0,
resembles a simple equation.

Every instruction, but two, assembles into a single, 24-bit
word that can execute in a single instruction cycle. The
exceptions are two dual word instructions. One writes 16-
or 24-bit immediate data to memory, and the other is an
absolute jump/call with the 24-bit address specified in the
instruction.

Multifunction instructions allow parallel execution of an
arithmetic, MAC, or shift instruction with up to two
fetches or one write to processor memory space during a
single instruction cycle.

Program flow instructions support a wider variety of con-
ditional and unconditional jumps/calls and a larger set of
conditions on which to base execution of conditional
instructions.

Development Tools

The ADSP-2191M is supported with a complete set of software
and hardware development tools, including Analog Devices
emulators and VisualDSP++® development environment. The
same emulator hardware that supports other ADSP-219x DSPs,
also fully emulates the ADSP-2191M.

The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy-to-use assembler that is based on an algebraic
syntax; an archiver (librarian/library builder), a linker, a loader,
a cycle-accurate instruction-level simulator, a C/C++ compiler,
and a C/C++ run-time library that includes DSP and mathemat-
ical functions. Two key points for these tools are:

Compiled ADSP-219x C/C++ code efficiency--the
compiler has been developed for efficient translation of
C/C++ code to ADSP-219x assembly. The DSP has
architectural features that improve the efficiency of
compiled C/C++ code.

ADSP-218x family code compatibility--The assembler
has legacy features to ease the conversion of existing
ADSP-218x applications to the ADSP-219x.

Debugging both C/C++ and assembly programs with the Visu-
alDSP++ debugger, programmers can:

View mixed C/C++ and assembly code (interleaved
source and object information)

Insert break points

Set conditional breakpoints on registers, memory, and
stacks

Trace instruction execution

Perform linear or statistical profiling of program
execution

Fill, dump, and graphically plot the contents of memory

Source level debugging

Create custom debugger windows

The VisualDSP++ IDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the ADSP-219x
development tools, including the syntax highlighting in the Visu-
alDSP++ editor. This capability permits:

Control how the development tools process inputs and
generate outputs.

Maintain a one-to-one correspondence with the tool's
command line switches.

Analog Devices DSP emulators use the IEEE 1149.1 JTAG test
access port of the ADSP-2191M processor to monitor and
control the target board processor during emulation. The
emulator provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonin-
trusive in-circuit emulation is assured by the use of the processor's
JTAG interface--the emulator does not affect target system
loading or timing.

ADSP-2191M

REV. 0

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide range
of tools supporting the ADSP-219x processor family. Hardware
tools include ADSP-219x PC plug-in cards. Third party software
tools include DSP libraries, real-time operating systems, and
block diagram design tools.

Designing an Emulator-Compatible DSP Board
(Target)

The White Mountain DSP (Product Line of Analog Devices,
Inc.) family of emulators are tools that every DSP developer
needs to test and debug hardware and software systems. Analog
Devices has supplied an IEEE 1149.1 JTAG Test Access Port
(TAP) on each JTAG DSP. The emulator uses the TAP to access
the internal features of the DSP, allowing the developer to load
code, set breakpoints, observe variables, observe memory, and
examine registers. The DSP must be halted to send data and
commands, but once an operation has been completed by the
emulator, the DSP system is set running at full speed with no
impact on system timing.

To use these emulators, the target's design must include the
interface between an Analog Devices JTAG DSP and the
emulation header on a custom DSP target board.

Target Board Header

The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in

Figure 4

. The customer must supply

this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
square post header, set on 0.1"

0.1" spacing, with a minimum

post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.

Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.

As can be seen in

Figure 4

, there are two sets of signals on the

header. There are the standard JTAG signals TMS, TCK, TDI,
TDO,

TRST, and EMU used for emulation purposes (via an

emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and

BTRST that are optionally used for

board-level (boundary scan) testing.

When the emulator is not connected to this header, place jumpers
across BTMS, BTCK,

BTRST, and BTDI as shown in

Figure 5

This holds the JTAG signals in the correct state to allow the DSP
to run free. Remove all the jumpers when connecting the
emulator to the JTAG header.

JTAG Emulator Pod Connector

Figure 6

details the dimensions of the JTAG pod connector at the

14-pin target end.

Figure 7

displays the keep-out area for a target

board header. The keep-out area allows the pod connector to
properly seat onto the target board header. This board area
should contain no components (chips, resistors, capacitors, etc.).
The dimensions are referenced to the center of the 0.25" square
post pin.

Figure 4. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in
Place)

TOP VIEW

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

Figure 5. JTAG Target Board Connector with No Local

Boundary Scan

Figure 6. JTAG Pod Connector Dimensions

TOP VIEW

EMU

GND

TMS

TCK

TRST

TDI

TDO

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

0.64"

0.88"

0.24"

REV. 0

ADSP-2191M

Design-for-Emulation Circuit Information

For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the EE-68:
Analog Devices JTAG Emulation Technical Reference on the Analog
Devices website (www.analog.com)--use site search on
"EE-68." This document is updated regularly to keep pace with
improvements to emulator support.

Additional Information

This data sheet provides a general overview of the ADSP-2191M
architecture and functionality. For detailed information on the
core architecture of the ADSP-219x family, refer to the
ADSP-219x/2191 DSP Hardware Reference. For details on the
instruction set, refer to the ADSP-219x Instruction Set Reference.

PIN FUNCTION DESCRIPTIONS

ADSP-2191M pin definitions are listed in

Table 7

. All

ADSP-2191M inputs are asynchronous and can be asserted
asynchronously to CLKIN (or to TCK for

TRST).

Tie or pull unused inputs to V

DDEXT

or GND, except for

ADDR210, DATA150, PF7-0, and inputs that have internal
pull-up or pull-down resistors (

TRST, BMODE0, BMODE1,

OPMODE, BYPASS, TCK, TMS, TDI, and

RESET)--these

pins can be left floating. These pins have a logic-level hold circuit
that prevents input from floating internally.

The following symbols appear in the Type column of

Table

: G

= Ground, I = Input, O = Output, P = Power Supply, and T =
Three-State.

Figure 7. JTAG Pod Connector Keep-Out Area

0.10"

0.15"

Table 7. Pin Function Descriptions

Pin Type

Function

A210

O/T

External Port Address Bus

D70

I/O/T

External Port Data Bus, least significant 8 bits

D15
/PF15
/SPI1SEL7

I/O/T
I/O
I

Data 15 (if 16-bit external bus)/Programmable Flags 15 (if 8-bit external bus)/SPI1 Slave
Select output 7 (if 8-bit external bus, when SPI1 enabled)

D14
/PF14
/SPI0SEL7

I/O/T
I/O
I

Data 14 (if 16-bit external bus)/Programmable Flags 14 (if 8-bit external bus)/SPI0 Slave
Select output 7 (if 8-bit external bus, when SPI0 enabled)

D13
/PF12
/SPI1SEL6

I/O/T
I/O
I

Data 13 (if 16-bit external bus)/Programmable Flags 13 (if 8-bit external bus)/SPI1 Slave
Select output 6 (if 8-bit external bus, when SPI1 enabled)

D12
/PF12
/SPI0SEL6

I/O/T
I/O
I

Data 12 (if 16-bit external bus)/Programmable Flags 12 (if 8-bit external bus)/SPI0 Slave
Select output 6 (if 8-bit external bus, when SPI0 enabled)

D11
/PF11
/SPI1SEL5

I/O/T
I/O
I

Data 11 (if 16-bit external bus)/Programmable Flags 11 (if 8-bit external bus)/SPI1 Slave
Select output 5 (if 8-bit external bus, when SPI1 enabled)

D10
/PF10
/SPI0SEL5

I/O/T
I/O
I

Data 10 (if 16-bit external bus)/Programmable Flags 10 (if 8-bit external bus)/SPI0 Slave
Select output 5 (if 8-bit external bus, when SPI0 enabled)

D9
/PF9
/SPI1SEL4

I/O/T
I/O
I

Data 9 (if 16-bit external bus)/Programmable Flags 9 (if 8-bit external bus)/SPI1 Slave Select
output 4 (if 8-bit external bus, when SPI1 enabled)

D8
/PF8
/SPI0SEL4

I/O/T
I/O
I

Data 8 (if 16-bit external bus)/Programmable Flags 8 (if 8-bit external bus)/SPI0 Slave Select
output 4 (if 8-bit external bus, when SPI0 enabled)

PF7
/SPI1SEL3
/DF

I/O/T
I
I

Programmable Flags 7/SPI1 Slave Select output 3 (when SPI0 enabled)/Divisor Frequency
(divisor select for PLL input during boot)

PF6
/SPI0SEL3
/MSEL6

I/O/T
I
I

Programmable Flags 6/SPI0 Slave Select output 3 (when SPI0 enabled)/Multiplier Select 6
(during boot)

ADSP-2191M

REV. 0

PF5
/SPI1SEL2
/MSEL5

I/O/T
I
I

Programmable Flags 5/SPI1 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 5
(during boot)

PF4
/SPI0SEL2
/MSEL4

I/O/T
I
I

Programmable Flags 4/SPI0 Slave Select output 2 (when SPI0 enabled)/Multiplier Select 4
(during boot)

PF3
/SPI1SEL1
/MSEL3

I/O/T
I
I

Programmable Flags 3/SPI1 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 3
(during boot)

PF2
/SPI0SEL1
/MSEL2

I/O/T
I
I

Programmable Flags 2/SPI0 Slave Select output 1 (when SPI0 enabled)/Multiplier Select 2
(during boot)

PF1
/SPISS1
/MSEL1

I/O/T
I
I

Programmable Flags 1/SPI1 Slave Select input (when SPI1 enabled)/Multiplier Select 1
(during boot)

PF0
/SPISS0
/MSEL0

I/O/T
I
I

Programmable Flags 0/SPI0 Slave Select input (when SPI0 enabled)/Multiplier Select 0
(during boot)

O/T

External Port Read Strobe

O/T

External Port Write Strobe

ACK

External Port Access Ready Acknowledge

BMS

O/T

External Port Boot Space Select

IOMS

O/T

External Port IO Space Select

MS30

O/T

External Port Memory Space Selects

External Port Bus Request

External Port Bus Grant

BGH

External Port Bus Grant Hang

HAD150

I/O/T

Host Port Multiplexed Address and Data Bus

HA16

Host Port MSB of Address Bus

HACK_P

Host Port ACK Polarity

HRD

Host Port Read Strobe

HWR

Host Port Write Strobe

HACK

Host Port Access Ready Acknowledge

HALE

Host Port Address Latch Strobe or Address Cycle Control

HCMS

Host Port Internal MemoryInternal I/O MemoryBoot Memory Select

HCIOMS

Host Port Internal I/O Memory Select

CLKIN

Clock Input/Oscillator input

XTAL

Oscillator output

BMODE10

Boot Mode 10. The BMODE1 and BMODE0 pins have 85 k

internal pull-up resistors.

OPMODE

Operating Mode. The OPMODE pin has a 85 k

internal pull-up resistor.

CLKOUT

Clock Output

BYPASS

Phase-Lock-Loop (PLL) Bypass mode. The BYPASS pin has a 85 k

internal pull-up resistor.

RCLK10

I/O/T

SPORT10 Receive Clock

RCLK2/SCK1

I/O/T

SPORT2 Receive Clock/SPI1 Serial Clock

RFS10

I/O/T

SPORT10 Receive Frame Sync

RFS2/MOSI1

I/O/T

SPORT2 Receive Frame Sync/SPI1 Master-Output, Slave-Input data

TCLK10

I/O/T

SPORT10 Transmit Clock

TCLK2/SCK0

I/O/T

SPORT2 Transmit Clock/SPI0 Serial Clock

TFS10

I/O/T

SPORT10 Transmit Frame Sync

TFS2/MOSI0

I/O/T

SPORT2 Transmit Frame Sync/SPI0 Master-Output, Slave-Input data

DR10

I/T

SPORT10 Serial Data Receive

DR2/MISO1

I/O/T

SPORT2 Serial Data Receive/SPI1 Master-Input, Slave-Output data

DT10

O/T

SPORT10 Serial Data Transmit

DT2/MISO0

I/O/T

SPORT2 Serial Data Transmit/SPI0 Master-Input, Slave-Output data

TMR20

I/O/T

Timer output or capture

Table 7. Pin Function Descriptions (continued)

Pin Type

Function

REV. 0

ADSP-2191M

RXD

UART Serial Receive Data

TXD

UART Serial Transmit Data

RESET

Processor Reset. Resets the ADSP-2191M to a known state and begins execution at the
program memory location specified by the hardware reset vector address. The

RESET input

must be asserted (low) at powerup. The RESET pin has an 85 k

internal pull-up resistor.

TCK

Test Clock (JTAG). Provides a clock for JTAG boundary scan. The TCK pin has an 85 k

internal pull-up resistor.

TMS

Test Mode Select (JTAG). Used to control the test state machine. The TMS pin has an 85 k

internal pull-up resistor.

TDI

Test Data Input (JTAG). Provides serial data for the boundary scan logic. The TDI pin has a
85 k

internal pull-up resistor.

TDO

Test Data Output (JTAG). Serial scan output of the boundary scan path.

TRST

Test Reset (JTAG). Resets the test state machine.

TRST must be asserted (pulsed low) after

powerup or held low for proper operation of the ADSP-2191M. The

TRST pin has a 65 k

internal pull-down resistor.

EMU

Emulation Status (JTAG). Must be connected to the ADSP-2191M emulator target board
connector only.

DDINT

Core Power Supply. Nominally 2.5 V dc and supplies the DSP's core processor. (four pins)

DDEXT

I/O Power Supply. Nominally 3.3 V dc. (nine pins)

GND

Power Supply Return. (twelve pins)

Do Not Connect. Reserved pins that must be left open and unconnected.

Table 7. Pin Function Descriptions (continued)

Pin Type

Function

ADSP-2191M

REV. 0

SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter

Specifications subject to change without notice.

Test Conditions

K Grade (Commercial)
Min Max

B Grade (Industrial)
Min Max

Unit

DDINT

Internal (Core) Supply
Voltage

2.37

2.63

2.37

2.63

DDEXT

External (I/O) Supply
Voltage

2.97

3.6

2.97

3.6

High Level Input Voltage

@ V

DDINT

= max,

DDEXT

= max

2.0

DDEXT

+ 0.3 2.0

DDEXT

+ 0.3 V

Low Level Input Voltage

@ V

DDINT

= min,

DDEXT

= min

0.3

0.8

0.3

0.8

AMB

Ambient Operating
Temperature

+ 85

ºC

ELECTRICAL CHARACTERISTICS

Parameter

Specifications subject to change without notice.

Test Conditions

K and B Grades
Min Typ

Max

Unit

High Level Output Voltage

Applies to output and bidirectional pins: DATA150, ADDR210, HAD150,

MS30, IOMS, RD, WR, CLKOUT, HACK, PF70, TMR20, BGH,

BG, DT0, DT1, DT2/MISO0, TCLK0, TCLK1, TCLK2/SCK0, RCLK0, RCLK1, RCLK2/SCK1, TFS0, TFS1, TFS2/MOSI0, RFS0, RFS1,
RFS2/MOSI1,

BMS, TDO, TXD, EMU, DR2/MISO1.

@ V

DDEXT

= min,

= 0.5 mA

2.4

Low Level Output Voltage

@ V

DDEXT

= min,

= 2.0 mA

0.4

High Level Input Current

3, 4

Applies to input pins: ACK,

BR, HCMS, HCIOMS, HA16, HALE, HRD, HWR, CLKIN, DR0, DR1, RXD, HACK_P.

Applies to input pins with internal pull-ups: BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS, TDI,

RESET.

@ V

DDEXT

= max,

= V

max

µA

Low Level Input Current

3, 5

Applies to input pin with internal pull-down: TRST.

@ V

DDEXT

= max,

= 0 V

µA

IHP

High Level Input Current

@ V

DDEXT

= max,

= V

max

100

µA

ILP

Low Level Input Current

@ V

DDEXT

= max,

= 0 V

µA

OZH

Three-State Leakage Current

Applies to three-statable pins: DATA150, ADDR210,

MS30, RD, WR, PF70, BMS, IOMS, TFSx, RFSx, TDO, EMU, TCLKx, RCLKx, DTx,

HAD150, TMR20.

@ V

DDEXT

= max,

= V

max

µA

OZL

Three-State Leakage Current

@ V

DDEXT

= max,

= 0 V

µA

Input Capacitance

7, 8

Applies to all signal pins.

Guaranteed, but not tested.

= 1 MHz,

CASE

= 25°C,

= 2.5 V

REV. 0

ADSP-2191M

ABSOLUTE MAXIMUM RATINGS

ESD SENSITIVITY

Power Dissipation

Using the operation-versus-current information in

Table 8

, designers can estimate the ADSP-2191M's internal power supply

DDINT

) input current for a specific application, according to the formula for I

DDINT

calculation beneath

Table 8

. For calculation

of external supply current and total supply current,

see Power Dissipation on page 41.

DDINT

Internal (Core) Supply Voltage

1,2

. . 0.3 V to 3.0 V

Specifications subject to change without notice.

Stresses greater than those listed above may cause permanent damage to the device.

These are stress ratings only; functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

DDEXT

External (I/O) Supply Voltage . . . . 0.3 V to 4.6 V

Input Voltage . . . . . . . . 0.5 V to V

DDEXT

+ 0.5 V

Output Voltage Swing . 0.5 V to V

DDEXT

+ 0.5 V

STORE

Storage Temperature Range . . . . . . 65ºC to 150ºC

LEAD

Lead Temperature of ST-144 (5 seconds) . . . . 185ºC

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-2191M features proprietary ESD protection circuitry,
permanent damage may occur on devices subjected to high-energy electrostatic
discharges. Therefore, proper ESD precautions are recommended to avoid perfor-
mance degradation or loss of functionality.

Table 8. Operation Types Versus Input Current

K-Grade
I

DDINT

(mA) CCLK = 160 MHz

B-Grade
I

DDINT

(mA)

CCLK = 140 MHz

Core

Peripheral

Core

Peripheral

Activity

Typ

Test conditions: VDDINT= 2.50 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25ºC.

Max

Test conditions: VDDINT= 2.65 V; HCLK (peripheral clock) frequency = CCLK/2 (core clock/2) frequency; TAMB = 25ºC.

Typ

Max

Typ

Max

Typ

Max

Power Down

PLL, Core, peripheral clocks, and CLKIN are disabled.

100µA

600µA

50µA

100µA

500µA

50µA

Idle 1

PLL is enabled and Core and peripheral clocks are disabled.

Idle 2

Core CLK is disabled and peripheral clock is enabled.

Typical

All instructions execute from internal memory. 50% of the instructions are repeat MACs with dual operand addressing, with changing data fetched using

a linear address sequence. 50% of the instructions are type 3 instructions.

184

210

165

185

Peak

All instructions execute from internal memory. 100% of the instructions are MACs with dual operand addressing, with changing data fetched using a linear

address sequence.

215

240

195

210

DDINT

%Typical

DDINT-TYPICAL

(

)

%Idle

DDINT-IDLE

(

)

%Power Down

DDINT-PWRDWN

(

)

ADSP-2191M

REV. 0

TIMING SPECIFICATIONS

This section contains timing information for the DSP's external signals. Use the exact information given. Do not attempt to derive
parameters from the addition or subtraction of other information. While addition or subtraction would yield meaningful results for an
individual device, the values given in this datasheet reflect statistical variations and worst cases. Consequently, parameters cannot be
added meaningfully to derive longer times.

Switching characteristics specify how the processor changes its signals. No control is possible over this timing; circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics indicate what the processor
will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected
to the processor (such as memory) is satisfied.

Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation.Timing requirements guarantee that the processor operates correctly with other devices.

Clock In and Clock Out Cycle Timing

Table 9

and

Figure 8

describe clock and reset operations. Combinations of CLKIN and clock multipliers must not select core/periph-

eral clocks in excess of 160/80 MHz for commercial grade and 140/70 MHz for industrial grade, when the peripheral clock rate is
one-half the core clock rate. If the peripheral clock rate is equal to the core clock rate, the maximum peripheral clock rate is 80 MHz
for both commercial and industrial grade parts. The peripheral clock is supplied to the CLKOUT pins.

When changing from bypass mode to PLL mode, allow 512 HCLK cycles for the PLL to stabilize.

Table 9. Clock In and Clock Out Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

CKOD

CLKOUT Delay from CLKIN

5.8

CKO

CLKOUT Period

CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.

12.5

Timing Requirements
t

CLKIN Period

In clock multiplier mode and MSEL60 set for 1:1 (or CLKIN = CCLK), t

= tCCLK.

In bypass mode, t

= t

CCLK

200

CKL

CLKIN Low Pulse

4.5

CKH

CLKIN High Pulse

4.5

WRST

RESET Asserted Pulsewidth Low

200t

CLKOUT

MSS

MSELx/BYPASS Stable Before

RESET Deasserted Setup

µs

MSH

MSELx/BYPASS Stable After

RESET Deasserted Hold

1000

MSD

MSELx/BYPASS Stable After

RESET Asserted

200

PFD

Flag Output Disable Time After

RESET Asserted

ADSP-2191M

REV. 0

Programmable Flags Cycle Timing

Table 10

and

Figure 9

describe Programmable Flag operations.

Timer PWM_OUT Cycle Timing

Table 11

and

Figure 10

describe timer expired operations. The input signal is asynchronous in "width capture mode" and has an

absolute maximum input frequency of 40 MHz.

Table 10. Programmable Flags Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

DFO

Flag Output Delay with Respect to CLKOUT

HFO

Flag Output Hold After CLKOUT High

Timing Requirement
t

HFI

Flag Input Hold is asynchronous

Figure 9. Programmable Flags Cycle Timing

Table 11. Timer PWM_OUT Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristic
t

HTO

Timer Pulsewidth Output

The minimum time for t

HTO

is one cycle, and the maximum time for t

HTO

equals (2

1) cycles.

12.5

1) cycles

Figure 10. Timer PWM_OUT Cycle Timing

FLAG INPUT

(INPUT)

HFI

(OUTPUT)

CLKOUT

FLAG OUTPUT

DFO

HFO

HCLK

P W M _OUT

H T O

REV. 0

ADSP-2191M

External Port Write Cycle Timing

Table 12

and

Figure 11

describe external port write operations.

The external port lets systems extend read/write accesses in three ways: waitstates, ACK input, and combined waitstates and ACK.
To add waits with ACK, the DSP must see ACK low at the rising edge of EMI clock. ACK low causes the DSP to wait, and the DSP
requires two EMI clock cycles after ACK goes high to finish the access. For more information, see the External Port chapter in the
ADSP-219x/2191 DSP Hardware Reference.

Table 12. External Port Write Cycle Timing

Parameter

1, 2

HCLK

is the peripheral clock period.

These are timing parameters that are based on worst-case operating conditions.

Min

Max

Unit

Switching Characteristics
t

CSWS

Chip Select Asserted to

WR Asserted Delay

0.5t

HCLK

AWS

Address Valid to

WR Setup and Delay

0.5t

HCLK

WSCS

WR Deasserted to Chip Select Deasserted

0.5t

HCLK

WSA

WR Deasserted to Address Invalid

0.5t

HCLK

WR Strobe Pulsewidth

HCLK

2 + W

W = (number of waitstates specified in wait register) t

HCLK.

CDA

WR to Data Enable Access Delay

CDD

WR to Data Disable Access Delay

0.5t

HCLK

0.5t

HCLK

+ 4

DSW

Data Valid to

WR Deasserted Setup

HCLK

+ 1 +W

HCLK

+ 7 + W

DHW

WR Deasserted to Data Invalid Hold Time; E_WHC

Write hold cyclememory select control registers (MS

CTL).

3.4

DHW

WR Deasserted to Data Invalid Hold Time; E_WHC

HCLK

+ 3.4

WWR

WR Deasserted to WR, RD Asserted

HCLK

Timing Requirements
t

AKW

ACK Strobe Pulsewidth

12.5

DWSAK

ACK Delay from

WR Low

Figure 11. External Port Write Cycle Timing

D 1 5 0

A W S

W W

A K W

D S W

D H W

C D D

A C K

W R

A 2 1 0

M S 3 0

IO M S

B M S

C S W S

W S A

W S C S

C D A

D W S A K

W W R

R D

ADSP-2191M

REV. 0

External Port Read Cycle Timing

Table 13

and

Figure 12

describe external port read operations. For additional information on the ACK signal, see the discussion

on page 23

Table 13. External Port Read Cycle Timing

Parameter

1, 2

HCLK

is the peripheral clock period.

These are timing parameters that are based on worst-case operating conditions.

Min

Max

Unit

Switching Characteristics
t

CSRS

Chip Select Asserted to

RD Asserted Delay

0.5t

HCLK

ARS

Address Valid to

RD Setup and Delay

0.5t

HCLK

RSCS

RD Deasserted to Chip Select Deasserted Setup

0.5t

HCLK

RD Strobe Pulsewidth

HCLK

2 + W

W = (number of waitstates specified in wait register) t

HCLK

RSA

RD Deasserted to Address Invalid Setup

0.5t

HCLK

RWR

RD Deasserted to WR, RD Asserted

HCLK

Timing Requirements
t

AKW

ACK Strobe Pulsewidth

HCLK

RDA

RD Asserted to Data Access Setup

HCLK

4 +W

ADA

Address Valid to Data Access Setup

HCLK

+ W

SDA

Chip Select Asserted to Data Access Setup

HCLK

+ W

Data Valid to

RD Deasserted Setup

HRD

RD Deasserted to Data Invalid Hold

DRSAK

ACK Delay from

RD Low

Figure 12. External Port Read Cycle Timing

D 1 5 0

A R S

R W

A K W

C D A

R D A

A D A

S D A

S D

H R D

A C K

R D

A 2 1 0

MS30

IOMS

BMS

C S R S

R S A

R S C S

D R S A K

R W R

REV. 0

ADSP-2191M

External Port Bus Request and Grant Cycle Timing

Table 14

and

Figure 13

describe external port bus request and bus grant operations.

Table 14. External Port Bus Request and Grant Cycle Timing

Parameter

1, 2

HCLK

is the peripheral clock period.

These are timing parameters that are based on worst-case operating conditions.

Min

Max

Unit

Switching Characteristics
t

CLKOUT High to

xMS, Address, and RD/WR Disable

0.5t

HCLK

CLKOUT Low to

xMS, Address, and RD/WR Enable

DBG

CLKOUT High to

BG Asserted Setup

EBG

CLKOUT High to

BG Deasserted Hold Time

DBH

CLKOUT High to

BGH Asserted Setup

EBH

CLKOUT High to

BGH Deasserted Hold Time

Timing Requirements
t

BR Asserted to CLKOUT High Setup

4.6

CLKOUT High to

BR Deasserted Hold Time

Figure 13. External Port Bus Request and Grant Cycle Timing

B H

A 210

MS30

IOMS

BMS

CLK OUT

B S

S D

D B G

D B H

S E

E B G

E B H

BGH

ADSP-2191M

REV. 0

Host Port ALE Mode Write Cycle Timing

Table 15

and

Figure 14

describe Host port write operations in Address Latch Enable (ALE) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description

on page 8

Table 15. Host Port ALE Mode Write Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

WHKS1

HWR Asserted to HACK Asserted (Setup, ACK Mode) First
Byte

HCLK

are peripheral bus latencies (n

HCLK

); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

at the same time.

WHKS2

HWR Asserted to HACK Asserted (Setup, ACK Mode)

Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

WHKH

HWR Deasserted to HACK Deasserted (Hold, ACK Mode)

WHS

HWR Asserted to HACK Asserted (Setup, Ready Mode)

WHH

HWR Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte

HCLK

Timing Requirements

CSAL

HCMS or HCIOMS Asserted to HALE Asserted

ALPW

HALE Asserted Pulsewidth

ALCSW

HALE Deasserted to

HCMS or HCIOMS Deasserted

WCSW

HWR Deasserted to HCMS or HCIOMS Deasserted

ALW

HALE Deasserted to

HWR Asserted

WCS

HWR Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Write)

HKWD

HACK Asserted to

HWR Deasserted (Hold, ACK Mode)

1.5

AALS

Address Valid to HALE Deasserted (Setup)

ALAH

HALE Deasserted to Address Invalid (Hold)

DWS

Data Valid to

HWR Deasserted (Setup)

WDH

HWR Deasserted to Data Invalid (Hold)

ADSP-2191M

REV. 0

Host Port ACC Mode Write Cycle Timing

Table 16

and

Figure 15

describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description

on page 8

Table 16. Host Port ACC Mode Write Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

WHKS1

HWR Asserted to HACK Asserted (ACK Mode) First Byte

HCLK

are peripheral bus latencies (n

HCLK

); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

at the same time.

WHKS2

HWR Asserted to HACK Asserted (Setup, ACK Mode)

Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent

on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

WHKH

HWR Deasserted to HACK Deasserted (Hold, ACK Mode)

WHS

HWR Asserted to HACK Asserted (Setup, Ready Mode)

WHH

HWR Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte

HCLK

WSHKS

HWR Asserted to HACK Asserted (Setup) During Address
Latch

WHHKH

HWR Deasserted to HACK Deasserted (Hold) During
Address Latch

Timing Requirements
t

WAL

HWR Asserted to HALE Deasserted (Delay)

1.5

CSAL

HCMS or HCIOMS Asserted to HALE Asserted (Delay)

ALCS

HALE Deasserted to Optional

HCMS or HCIOMS

Deasserted

WCSW

HWR Deasserted to HCMS or HCIOMS Deasserted

ALW

HALE Asserted to HWR Asserted

0.5

CSW

HCMS or HCIOMS Asserted to HWR Asserted

WCS

HWR Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Write)

ALEW

HALE Deasserted to HWR Asserted

HKWD

HACK Asserted to

HWR Deasserted (Hold, ACK Mode)

1.5

ADW

Address Valid to

HWR Asserted (Setup)

WAD

HWR Deasserted to Address Invalid (Hold)

DWS

Data Valid to

HWR Deasserted (Setup)

WDH

HWR Deasserted to Data Invalid (Hold)

HKWAL

HACK Asserted to

HWR Deasserted (Hold) During Address

Latch

ADSP-2191M

REV. 0

Host Port ALE Mode Read Cycle Timing

Table 17

and

Figure 16

describe Host port read operations in Address Latch Enable (ALE) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description

on page 8

Table 17. Host Port ALE Mode Read Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

RHKS1

HRD Asserted to HACK Asserted (ACK Mode) First Byte

12t

HCLK

15t

HCLK

are peripheral bus latencies (n

HCLK

); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

the same time.

RHKS2

HRD Asserted to HACK Asserted (Setup, ACK Mode)

Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

RHKH

HRD Deasserted to HACK Deasserted (Hold, ACK Mode)

RHS

HRD Asserted to HACK Asserted (Setup, Ready Mode)

RHH

HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte

12t

HCLK

15t

HCLK

RDH

HRD Deasserted to Data Invalid (Hold)

RDD

HRD Deasserted to Data Disable

Timing Requirements
t

CSAL

HCMS or HCIOMS Asserted to HALE Asserted (Delay)

ALCS

HALE Deasserted to Optional

HCMS or HCIOMS

Deasserted

RCSW

HRD Deasserted to HCMS or HCIOMS Deasserted

ALR

HALE Deasserted to

HRD Asserted

RCS

HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)

ALPW

HALE Asserted Pulsewidth

HKRD

HACK Asserted to

HRD Deasserted (Hold, ACK Mode)

1.5

AALS

Address Valid to HALE Deasserted (Setup)

ALAH

HALE Deasserted to Address Invalid (Hold)

ADSP-2191M

REV. 0

Host Port ACC Mode Read Cycle Timing

Table 18

and

Figure 17

describe Host port read operations in Address Cycle Control (ACC) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description

on page 8

Table 18. Host Port ACC Mode Read Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

RHKS1

HRD Asserted to HACK Asserted (ACK Mode) First Byte

12t

HCLK

15t

HCLK

are peripheral bus latencies (n

HCLK

); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at

the same time.

RHKS2

HRD Asserted to HACK Asserted (Setup, ACK Mode)

Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on

the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

RHKH

HRD Deasserted to HACK Deasserted (Hold, ACK Mode)

RHS

HRD Asserted to HACK Asserted (Setup, Ready Mode)

RHH

HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte

12t

HCLK

15t

HCLK

RDH

HRD Deasserted to Data Invalid (Hold)

WSHKS

HWR Asserted to HACK Asserted (Setup) During Address
Latch

WHHKH

HWR Deasserted to HACK Deasserted (Hold) During
Address Latch

RDD

HRD Deasserted to Data Disable

Timing Requirements
t

CSAL

HCMS or HCIOMS Asserted to HALE Asserted (Delay)

ALCS

HALE Deasserted to Optional

HCMS or HCIOMS

Deasserted

RCSW

HRD Deasserted to HCMS or HCIOMS Deasserted

ALW

HALE Asserted to HWR Asserted

0.5

ALER

HALE Deasserted to HWR Asserted

CSR

HCMS or HCIOMS Asserted to HRD Asserted

RCS

HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)

WAL

HWR Deasserted to HALE Deasserted (Delay)

2.5

HKRD

HACK Asserted to

HRD Deasserted (Hold, ACK Mode)

1.5

ADW

Address Valid to

HWR Deasserted (Setup)

WAD

HWR Deasserted to Address Invalid (Hold)

HKWAL

HACK Asserted to

HWR Deasserted (Hold) During Address

Latch

ADSP-2191M

REV. 0

Serial Ports

Table 19

and

Figure 18

describe SPORT transmit and receive operations, while

Figure 19

and

Figure 20

describe SPORT Frame

Sync operations.

Table 19. Serial Ports

1, 2

To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay

and frame sync setup-and-hold, 2) data delay and data setup-and-hold, and 3) SCLK width.

Word selected timing for I

S mode is the same as TFS/RFS timing (normal framing only).

Parameter

Min

Max

Unit

External Clock
Timing Requirements
t

SFSE

TFS/RFS Setup Before TCLK/RCLK

Referenced to sample edge.

HFSE

TFS/RFS Hold After TCLK/RCLK

SDRE

Receive Data Setup Before RCLK

1.5

HDRE

Receive Data Hold After RCLK

SCLKW

TCLK/RCLK Width

0.5t

HCLK

SCLK

TCLK/RCLK Period

HCLK

Internal Clock
Timing Requirements
t

SFSI

TFS Setup Before TCLK

; RFS Setup Before RCLK

Referenced to drive edge.

HFSI

TFS/RFS Hold After TCLK/RCLK

SDRI

Receive Data Setup Before RCLK

HDRI

Receive Data Hold After RCLK

External or Internal Clock

Switching Characteristics
t

DFSE

TFS/RFS Delay After TCLK/RCLK (Internally
Generated FS)

HOFSE

TFS/RFS Hold After TCLK/RCLK (Internally
Generated FS)

External Clock

Switching Characteristics
t

DDTE

Transmit Data Delay After TCLK

13.4

HDTE

Transmit Data Hold After TCLK

Internal Clock

Switching Characteristics
t

DDTI

Transmit Data Delay After TCLK

13.4

HDTI

Transmit Data Hold After TCLK

SCLKIW

TCLK/RCLK Width

0.5t

HCLK

3.5

0.5t

HCLK

+ 2.5

Enable and Three-State

Only applies to SPORT0/1.

Switching Characteristics
t

DTENE

Data Enable from External TCLK

12.1

DDTTE

Data Disable from External TCLK

DTENI

Data Enable from Internal TCLK

DDTTI

Data Disable from External TCLK

External Late Frame Sync

Switching Characteristics
t

DDTLFSE

Data Delay from Late External TFS with MCE = 1, MFD = 0

6, 7

MCE = 1, TFS enable, and TFS valid follow t

DDTENFS

and t

DDTLFSE

If external RFSD/TFS setup to RCLK/TCLK > 0.5t

LSCK

, t

DDTLSCK

and t

DTENLSCK

apply; otherwise t

DDTLFSE

and t

DTENLFS

apply.

10.5

DTENLFSE

Data Enable from Late FS or MCE = 1, MFD = 0

6, 7

3.5

REV. 0

ADSP-2191M

Figure 18. Serial Ports

DDTTE

DDTEN

DDTTI

DDTIN

DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

DRIVE

EDGE

TCLK / RCLK

TCLK (EXT)

TFS ("LATE," EXT.)

SDRI

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRI

SFSI

HFSI

DFSE

HOFSE

SCLKIW

DATA RECEIVE-INTERNAL CLOCK

SDRE

DATA RECEIVE-EXTERNAL CLOCK

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

HDRE

SFSE

HFSE

DFSE

SCLKW

HOFSE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DDTI

HDTI

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

SFSI

HFSI

SCLKIW

DFSE

HOFSE

DATA TRANSMIT-INTERNAL CLOCK

DDTE

HDTE

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

SFSE

HFSE

DFSE

SCLKW

HOFSE

DATA TRANSMIT-EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

TCLK (INT)

TFS ("LATE," INT.)

REV. 0

ADSP-2191M

Serial Peripheral Interface (SPI) Port--Master Timing

Table 20

and

Figure 21

describe SPI port master operations.

Table 20. Serial Peripheral Interface (SPI) Port--Master Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

SDSCIM

SPIxSEL Low to First SCLK edge (x=0 or 1)

HCLK

SPICHM

Serial Clock High Period

HCLK

SPICLM

Serial Clock Low Period

HCLK

SPICLK

Serial Clock Period

HCLK

HDSM

Last SCLK Edge to

SPIxSEL High (x=0 or 1)

HCLK

SPITDM

Sequential Transfer Delay

HCLK

DDSPID

SCLK Edge to Data Output Valid (Data Out Delay)

HDSPID

SCLK Edge to Data Output Invalid (Data Out Hold)

Timing Requirements
t

SSPID

Data Input Valid to SCLK Edge (Data Input Setup)

HSPID

SCLK Sampling Edge to Data Input Invalid (Data In Hold)

Figure 21. Serial Peripheral Interface (SPI) Port--Master Timing

S S P I D

H S P I D

H D S P I D

L S B

M S B

H S P I D

D D S P I D

M OS I

( OU T PU T )

MI S O

(I N P U T)

SPIxSEL

( O U T PU T )

(x = 0 o r 1 )

SC LK

(C P O L = 0 )

(O U T P U T )

SC L K

(C P OL = 1 )

(O U T P U T )

S P I C H M

S P I C L M

S P I C L K

S P I C H M

H D S M

S P I T D M

H D S P I D

L S B

V A L I D

L S B

MS B

M S B

V A L I D

H S P I D

D D S P I D

M O S I

( OU T P U T )

M I S O

(I N PU T )

S S P I D

CPHA = 0

M S B

V A L I D

S D S C I M

S S P I D

L S B

V A L I D

CPHA = 1

ADSP-2191M

REV. 0

Serial Peripheral Interface (SPI) Port--Slave Timing

Table 21

and

Figure 22

describe SPI port slave operations.

Table 21. Serial Peripheral Interface (SPI) Port--Slave Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

DSOE

SPISS Assertion to Data Out Active

DSDHI

SPISS Deassertion to Data High Impedance

DDSPID

SCLK Edge to Data Out Valid (Data Out Delay)

HDSPID

SCLK Edge to Data Out Invalid (Data Out Hold)

Timing Requirements
t

SPICHS

Serial Clock High Period

HCLK

SPICLS

Serial Clock Low Period

HCLK

SPICLK

Serial Clock Period

HCLK

HDS

Last SPICLK Edge to

SPISS Not Asserted

HCLK

SPITDS

Sequential Transfer Delay

HCLK

+ 4

SDSCI

SPISS Assertion to First SPICLK Edge

HCLK

SSPID

Data Input Valid to SCLK Edge (Data Input Setup)

1.6

HSPID

SCLK Sampling Edge to Data Input Invalid (Data In Hold)

2.4

Figure 22. Serial Peripheral Interface (SPI) Port--Slave Timing

HSPID

DDSPID

DSDHI

LSB

MSB

VALID

HSPID

DSOE

DDSPID

HDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

SPISS

(INPUT)

SCLK

(CPOL = 0)

(INPUT)

SCLK

(CPOL = 1)

(INPUT)

SDSCI

SPICHS

SPICLS

SPICLK

HDS

SPICHS

SSPID

HSPID

DSDHI

LSB

VALID

MSB

VALID

DSOE

DDSPID

MISO

(OUTPUT)

MOSI

(INPUT)

SSPID

LSB

VALID

LSB

SPITDS

CPHA = 0

CPHA = 1

ADSP-2191M

REV. 0

JTAG Test And Emulation Port Timing

Table 22

and

Figure 24

describe JTAG port operations.

Table 22. JTAG Port Timing

Parameter

Min

Max

Unit

Switching Characteristics
t

DTDO

TDO Delay from TCK Low

DSYS

System Outputs Delay After TCK Low

Timing Requirements
t

TCK

TCK Period

STAP

TDI, TMS Setup Before TCK High

HTAP

TDI, TMS Hold After TCK High

SSYS

System Inputs Setup Before TCK Low

HSYS

System Inputs Hold After TCK Low

TRSTW

TRST Pulsewidth

TCK

System Outputs = DATA150, ADDR210,

MS30, RD, WR, ACK, CLKOUT, BG, PF70, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1,

TFS0, TFS1, RFS0, RFS1,

BMS.

System Inputs = DATA150, ADDR210,

RD, WR, ACK, BR, BG, PF70, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1,

CLKIN,

RESET.

50 MHz max.

Figure 24. JTAG Port Timing

TMS

TDI

TD O

S YSTE M

INPUTS

S YSTE M

O UTPUTS

TCK

T C K

H T A P

S T A P

D T D O

SS Y S

H S Y S

D S Y S

REV. 0

ADSP-2191M

Output Drive Currents

Figure 25

shows typical I-V characteristics for the output drivers

of the ADSP-2191M. The curves represent the current drive
capability of the output drivers as a function of output voltage.

Power Dissipation

Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.

The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:

Number of output pins that switch during each cycle (O)

The maximum frequency at which they can switch (f)

Their load capacitance (C)

Their voltage swing (V

)

and is calculated by the formula below.

The load capacitance includes the processor's package capaci-
tance (C

). The switching frequency includes driving the load

high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2t

). The write strobe can switch

every cycle at a frequency of 1/t

. Select pins switch at 1/(2t

but selects can switch on each cycle. For example, estimate P

EXT

with the following assumptions:

A system with one bank of external data memory--asyn-
chronous RAM (16-bit)

One 64K 16 RAM chip is used with a load of 10 pF

Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz

External data memory writes occur every other cycle, a
rate of 1/(4t

HCLK

), with 50% of the pins switching

The bus cycle time is 80 MHz (t

HCLK

= 12.5 nsec)

The P

EXT

equation is calculated for each class of pins that can

drive as shown in

Table 23

A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.

Where:

EXT

is from

Table 23

INT

is I

DDINT

2.5 V, using the calculation I

DDINT

listed in

Power Dissipation on page 41

Note that the conditions causing a worst-case P

EXT

are different

from those causing a worst-case P

INT

. Maximum P

INT

cannot

occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.

Test Conditions

The DSP is tested for output enable, disable, and hold time.

Output Disable Time

Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C

and the

load current, I

. This decay time can be approximated by the

equation below.

Figure 25. Typical Drive Currents

SOURCE (

VDDEXT

) VOLTAGE V

3.5

0.5

1.0

1.5

2.0

2.5

3.0

(
V

)

100

80

60

40

20

4.0

DDEXT

= 3.65V @

 40°C

DDEXT

= 3.3V @

+ 25°C

DDEXT

= 3.0V @

+ 85°C

DDEXT

= 3.0V @

+ 85°C

DDEXT

= 3.3V @

+ 25°C

DDEXT

= 3.65V @

 40°C

INPUT CURRENT

OUTPUT CURRENT

EXT

Table 23. P

EXT

Calculation Example

Pin Type

# of Pins

% Switching

= P

EXT

Address

10 pF

20 MHz

10.9 V

= .01635 W

MSx

10 pF

20 MHz

10.9 V

= 0 W

10 pF

40 MHz

10.9 V

= .00436 W

Data

10 pF

20 MHz

10.9 V

= .01744 W

CLKOUT

10 pF

80 MHz

10.9 V

= .00872 W
P

EXT

= .04687 W

TOTAL

EXT

INT

DECAY

---------------

ADSP-2191M

REV. 0

The output disable time t

DIS

is the difference between

MEASURED

and t

DECAY

as shown in

Figure 26

. The time

MEASURED

is the interval from when the reference signal

switches to when the output voltage decays V from the measured
output high or output low voltage. The t

DECAY

is calculated with

test loads C

and I

, and with V equal to 0.5 V.

Output Enable Time

Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start
driving. The output enable time t

ENA

is the interval from when

a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram (

Figure 26

). If multiple

pins (such as the data bus) are enabled, the measurement value
is that of the first pin to start driving.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,
first calculate t

DECAY

using the equation at

Output Disable Time

on page 41

. Choose V to be the difference between the

ADSP-2191M's output voltage and the input threshold for the
device requiring the hold time. A typical V will be 0.4 V. C

the total bus capacitance (per data line), and I

is the total leakage

or three-state current (per data line). The hold time will be
t

DECAY

plus the minimum disable time (i.e., t

DATRWH

for the

write cycle).

Capacitive Loading

Output delays and holds are based on standard capacitive loads:
50 pF on all pins (see

Figure 30

). The delay and hold specifica-

tions given should be derated by a factor of 1.5 ns/50 pF for loads
other than the nominal value of 50 pF.

Figure 28

and

Figure 29

show how output rise time varies with capacitance. These figures
also show graphically how output delays and holds vary with load
capacitance. (Note that this graph or derating does not apply to
output disable delays; see

Output Disable Time on page 41

.) The

graphs in these figures may not be linear outside the ranges
shown.

Environmental Conditions

The thermal characteristics in which the DSP is operating
influence performance.

Thermal Characteristics

The ADSP-2191M comes in a 144-lead LQFP or 144-lead Ball
Grid Array (mini-BGA) package. The ADSP-2191M is specified
for an ambient temperature (T

AMB

) as calculated using the

formula below.

To ensure that the T

AMB

data sheet specification is not exceeded,

a heatsink and/or an air flow source may be used. A heatsink
should be attached to the ground plane (as close as possible to
the thermal pathways) with a thermal adhesive.

Figure 26. Output Enable/Disable

Figure 27. Equivalent Device Loading for AC

Measurements (Includes All Fixtures)

Figure 28. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

REFERENCE

SIGNAL

DIS

OUTPUT STARTS

DRIVING

OH (MEASURED)

OL (MEASURED)

MEASURED

OH (MEASURED)

OL (MEASURED)

2.0V

1.0V

HIGH-IMPEDANCE STATE.

TEST CONDITIONS CAUSE THIS VOLTAGE

TO BE APPROXIMATELY 1.5V

OUTPUT STOPS

DRIVING

DECAY

ENA

+1.5V

50pF

OUTPUT

PIN

INPUT

OUTPUT

1.5V

Figure 29. Typical Output Rise Time (10%-90%,

DDEXT

= Minimum at Maximum Ambient

Operating Temperature) vs. Load Capacitance

LOAD CAPACITANCE pF

250

100

150

200

I
S

I
M

(
1

)

RISE TIME

AMB

CASE

ADSP-2191M

REV. 0

144-Lead LQFP Pinout

Table 25

lists the LQFP pinout by signal name.

Table 26

lists

the LQFP pinout by pin.

Table 25. 144-Lead LQFP Pins (Alphabetically by Signal)

Signal

Pin
No.

Signal

Pin
No.

Signal

Pin
No.

Signal

Pin
No.

Signal

Pin
No.

BYPASS

GND

HCMS

TCLK1

CLKIN

132

GND

HCIOMS

TCLK2

CLKOUT

130

GND

HRD

TDI

123

GND

HWR

TDO

124

GND

IOMS

114

TFS0

125

GND

MS0

115

TFS1

126

GND

105

MS1

116

TFS2

128

GND

129

MS2

117

TMR0

135

GND

134

MS3

119

TMR1

136

HA16

OPMODE

TMR2

A10

137

HACK

PF0

TMS

A11

138

HACK_P

PF1

TRST

A12

139

HAD0

PF2

TXD

A13

D10

140

HAD1

PF3

DDEXT

A14

101

D11

141

HAD2

PF4

DDEXT

A15

102

D12

142

HAD3

PF5

DDEXT

A16

103

D13

144

HAD4

PF6

DDEXT

A17

104

D14

HAD5

PF7

DDEXT

A18

106

D15

HAD6

RCLK0

DDEXT

100

A19

107

DR0

HAD7

RCLK1

DDEXT

118

A20

108

DR1

HAD8

RCLK2

DDEXT

131

A21

109

DR2

HAD9

122

DDEXT

143

ACK

120

DT0

HAD10

RESET

DDINT

111

DT1

HAD11

RFS0

DDINT

BGH

110

DT2

HAD12

RFS1

DDINT

BMODE0

EMU

HAD13

RFS2

DDINT

127

BMODE1

GND

HAD14

RXD

121

BMS

113

GND

HAD15

TCK

XTAL

133

112

GND

HALE

TCLK0

REV. 0

ADSP-2191M

Table 26. 144-Lead LQFP Pins (Numerically by Pin Number)

Pin
No.

Signal

Pin
No.

Signal

Pin
No.

Signal

Pin
No.

Signal

Pin
No.

Signal

D14

HALE

TFS0

117

MS2

D15

HRD

DR0

118

DDEXT

HAD0

HWR

RCLK0

DDEXT

119

MS3

HAD1

GND

RFS0

120

ACK

GND

PF0

DDEXT

121

HAD2

PF1

DT1

122

HAD3

PF2

TCLK1

GND

123

HAD4

PF3

TFS1

124

HAD5

PF4

DR1

A10

125

HAD6

PF5

RCLK1

A11

126

HAD7

DDEXT

RFS1

A12

127

DDINT

HAD8

PF6

BMODE0

A13

128

DDEXT

PF7

BMODE1

100

DDEXT

129

GND

HAD9

TMR0

BYPASS

101

A14

130

CLKOUT

HAD10

TMR1

RESET

102

A15

131

DDEXT

GND

TMR2

TDO

103

A16

132

CLKIN

HAD11

DT2

TDI

104

A17

133

XTAL

HAD12

TCLK2

TMS

105

GND

134

GND

DDINT

TFS2

GND

106

A18

135

HAD13

DR2

TCK

107

A19

136

HAD14

RCLK2

TRST

108

A20

137

HAD15

RFS2

GND

109

A21

138

HA16

RXD

EMU

110

BGH

139

HACK_P

TXD

DDINT

111

140

D10

DDEXT

GND

OPMODE

112

141

D11

HACK

GND

113

BMS

142

D12

HCMS

DT0

114

IOMS

143

DDEXT

HCIOMS

TCLK0

115

MS0

144

D13

GND

DDINT

116

MS1

ADSP-2191M

REV. 0

144-Lead Mini-BGA Pinout

Table 27

lists the mini-BGA pinout by signal name.

Table 28

lists the mini-BGA pinout by ball number.

Table 27. 144-Lead Mini-BGA Pins (Alphabetically by Signal)

Signal

Ball
No.

Signal

Ball
No.

Signal

Ball
No.

Signal

Ball
No.

Signal

Ball
No.

J11

BYPASS

M11

GND

HALE

TCLK0

CLKIN

GND

HCIOMS

TCLK1

H10

CLKOUT

GND

HCMS

TCLK2

G12

GND

HRD

TDI

K12

H11

GND

HWR

TDO

L11

G10

GND

IOMS

TFS0

F12

GND

MS0

TFS1

G11

GND

MS1

TFS2

F10

GND

MS2

TMR0

F11

GND

M12

MS3

TMR1

A10

E12

HACK

OPMODE

H12

TMR2

A11

E11

HACK_P

PF0

TMS

K10

A12

E10

HAD0

PF1

TRST

J12

A13

D10

HAD1

PF2

TXD

A14

D11

HAD2

PF3

DDEXT

A15

D10

D12

HAD3

PF4

DDEXT

A16

D12

D13

HAD4

PF5

DDEXT

A17

C11

D14

HAD5

PF6

DDEXT

A18

C12

D15

HAD6

PF7

DDEXT

A19

B12

DR0

HAD7

RCLK0

DDEXT

A20

B11

DR1

HAD8

RCLK1

DDEXT

A21

A11

DR2

HAD9

RCLK2

DDEXT

ACK

DT0

HAD10

DDINT

C10

DT1

HAD11

RESET

L12

DDINT

BGH

B10

DT2

HAD12

RFS0

DDINT

BMODE0

L10

EMU

J10

HAD13

RFS1

M10

DDINT

BMODE1

GND

HAD14

RFS2

BMS

A10

GND

A12

HAD15

RXD

XTAL

GND

HA16

TCK

K11

REV. 0

ADSP-2191M

Table 28. 144-Lead Mini-BGA Pins (Numerically by Ball Number)

Ball
No.

Signal

Ball
No.

Signal

Ball
No.

Signal

Ball
No.

Signal

Ball
No.

Signal

GND

CLKOUT

E11

A11

DT2

DR1

D13

E12

A10

GND

K10

TMS

HAD10

DT0

K11

TCK

MS2

HAD12

DDEXT

K12

TDI

CLKIN

C10

HAD14

DDEXT

PF1

C11

A17

DDINT

PF3

C12

A18

DDEXT

H10

PF5

ACK

HAD3

DDEXT

H11

TMR1

MS1

HAD6

GND

H12

OPMODE

DR2

A10

BMS

HAD5

GND

HALE

GND

A11

A21

HAD4

GND

HRD

DR0

A12

GND

F10

HCIOMS

DT1

D14

DDINT

F11

TMR2

BMODE1

D15

F12

RCLK2

L10

BMODE0

HAD1

MS3

HACK_P

TCLK0

L11

TDO

D11

MS0

HAD13

DDINT

L12

RESET

D10

A15

HAD15

TFS1

GND

XTAL

D11

A14

GND

RCLK1

PF2

D12

A16

GND

J10

EMU

PF4

HAD7

GND

J11

PF7

HAD9

DDEXT

J12

TRST

TFS2

B10

BGH

HAD11

DDEXT

PF0

RFS2

B11

A20

HAD8

DDINT

HWR

TXD

B12

A19

DDEXT

G10

PF6

TFS0

HAD0

DDEXT

G11

TMR0

TCLK1

HAD2

GND

G12

TCLK2

M10

RFS1

D12

IOMS

HCMS

RXD

M11

BYPASS

D10

A13

HA16

RCLK0

M12

GND

E10

A12

HACK

RFS0

ADSP-2191M

REV. 0

OUTLINE DIMENSIONS

144-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-144)

144-BALL MINI-BGA (CA-144A)

SEATING

PLANE

1.60 MAX

0.15
0.05

0.08 MAX LEAD

COPLANARITY

0.75
0.60
0.45

1.45
1.40
1.35

3 6

108

144

109

TOP VIEW (PINS DOWN)

22.00 BSC SQ

20.00 BSC SQ

0.50 BSC
LEAD PITCH

0.27
0.22
0.17

TYP

DIMENSIONS IN MILLIMETERS.

ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS
IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION.

CENTER DIMENSIONS ARE NOMINAL.

NOTES:

DETAIL A

SEATING
PLANE

0.85
MIN

0.25
MIN

DIMENSIONS IN MILLIMETERS.

ACTUAL POSITION OF THE BALL GRID IS
WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE TO
THE PACKAGE EDGES.

ACTUAL POSITION OF EACH BALL IS WITHIN 0.08
OF ITS IDEAL POSITION, RELATIVE TO THE BALL
GRID.

CENTER DIMENSIONS ARE NOMINAL.

NOTES:

DETAIL A

0.55
0.50
0.45

BALL

DIAMETER

0.10 MAX BALL
COPLANARITY

1.70

MAX

DETAIL A

8.80

BSC

0.80

BSC

BALL

PITCH

A
B
C
D
E
F
G
H
J
K
L
M

12 11 10 9 8 7 6 5 4 3 2 1

10.10
10.00 SQ

9.90

BOTTOM VIEW

TOP VIEW

A1 COR NER INDE X

T RIANG LE

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-2191

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADSP-2191