REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DAC8043A

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

12-Bit Serial Input

Multiplying D/A Converter

FUNCTIONAL BLOCK DIAGRAM

12-BIT SHIFT

REGISTER

DAC REG

DAC

DAC8043A

REF

CLK

SRI

GND

OUT

FEATURES
Compact SO-8 and TSSOP Packages
True 12-Bit Accuracy
+5 V Operation @ <10

Fast 3-Wire Serial Input
Fast 1 s Settling Time
2.4 MHz 4-Quadrant Multiply BW
Pin-for-Pin Upgrade for DAC8043
Standard and Rotated Pinout

APPLICATIONS
Ideal for PLC Applications in Industrial Control
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration and Filters
Motion Control Systems

GENERAL DESCRIPTION

The DAC8043A is an improved high accuracy 12-bit multiply-
ing digital-to-analog converter in space-saving 8-lead packages.
Featuring serial input, double buffering and excellent analog
performance, the DAC8043A is ideal for applications where PC
board space is at a premium. Improved linearity and gain error
performance permit reduced parts count through the elimina-
tion of trimming components. Separate input clock and load
DAC control lines allow full user control of data loading and
analog output.

The circuit consists of a 12-bit serial-in/parallel-out shift regis-
ter, a 12-bit DAC register, a 12-bit CMOS DAC and control
logic. Serial data is clocked into the input register on the rising
edge of the CLOCK pulse. When the new data word has been
clocked in, it is loaded into the DAC register with the

LD input

pin. Data in the DAC register is converted to an output current
by the D/A converter.

Consuming only 10

A from a single +5 V power supply, the

DAC8043A is the ideal low power, small size, high performance
solution to many application problems.

The DAC8043A is specified over the extended industrial
(40

C to +85

C) temperature range. DAC8043A is available

in plastic DIP, and the low profile 1.75 mm height SO-8 surface
mount packages. The DAC8043AFRU is available for ultra-
compact applications in a thin 1.1 mm TSSOP-8 package.

CODE

INL LSB

0.1

1024

2048

3072

4096

0.5

0.4

0.3

0.2

0.3

0.4

512

1536

2560

3584

= +25 C, +85 C, 40 C

= +5V

REF

= 10V

Figure 1. Integral Nonlinearity Error vs. Code

REV. 0

DAC8043ASPECIFICATIONS

Parameter

Symbol

Condition

E Grade

F Grade

Units

STATIC PERFORMANCE

Resolution

Bits

Relative Accuracy

INL

0.5

1.0

LSB max

Differential Nonlinearity

DNL

All Grades Monotonic to 12 Bits

0.5

1.0

LSB max

Gain Error

FSE

= +25

C, Data = FFF

1.0

2.0

LSB max

= 40

C, +85

C, Data = FFF

2.0

LSB max

Gain Tempco

TCG

OUT

Pin Measured

ppm/

C max

Output Leakage Current

LKG

Data = 000

, I

OUT

Pin Measured

nA max

= 40

C, +85

C, Data = 000

, I

OUT

Pin Measured

nA max

Zero-Scale Error

ZSE

Data = 000

0.03

LSB max

= 40

C, +85

C, Data = 000

0.15

LSB max

REFERENCE INPUT

Input Resistance

REF

Absolute Tempco < 50 ppm/

7/15

min/max

Input Capacitance

REF

pF typ

ANALOG OUTPUT

Output Capacitance

OUT

Data = 000

pF typ

Data = FFF

pF typ

DIGITAL INPUTS

Digital Input Low

0.8

V max

Digital Input High

2.4

V min

Input Leakage Current

LOGIC

= 0 V to +5 V

0.001/

A typ/max

Input Capacitance

LOGIC

= 0 V

pF max

INTERFACE TIMING

2, 4

Data Setup

ns min

Data Hold

ns min

Clock Width High

ns min

Clock Width Low

ns min

Load Pulsewidth

ns min

LSB CLK to

LD DAC

ASB

ns min

AC CHARACTERISTICS

1, 2

Output Current Settling Time

0.01% of Full Scale, Ext Op Amp OP42

s max

DAC Glitch

Data = 000

to FFF

to 000

, V

REF

= 0 V

nVs max

Feedthrough (V

OUT

REF

)

REF

= 20 V p-p, Data = 000

, f = 10 kHz

mV p-p

Total Harmonic Distortion

THD

REF

= 6 V rms, Data = FFF

, f = 1 kHz

dB typ

Output Noise Density

10 Hz to 100 kHz Between R

and I

OUT

nV/

Hz max

Multiplying Bandwidth

3 dB, V

OUT

REF

, V

REF

= 100 mV rms, Data = FFF

2.4

MHz typ

SUPPLY CHARACTERISTICS

Power Supply Range

DD RANGE

4.5/5.5

V min/max

Positive Supply Current

LOGIC

= 0 V or V

A max

Power Dissipation

DISS

LOGIC

= 0 V or V

W max

Power Supply Sensitivity

PSS

0.002

%/% max

NOTES

Using internal feedback resistor R

, see Figure 19 test circuit with V

REF

= +10 V.

These parameters are guaranteed by design and not subject to production testing.

Calculated from worst case R

REF

: I

ZSE

(LSB) = (R

REF

LKG

4096)/V

REF

All input control signals are specified with t

= t

= 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

Calculation from e

4KTRB where: K = Boltzmann Constant (J/

K), R = Resistance (

), T = Resistor Temperature (

K), B = 1 Hz Bandwidth.

Specifications subject to change without notice.

ELECTRICAL CHARACTERISTICS

(@ V

= +5 V, V

REF

= +10 V, 40 C < T

< +85 C, unless otherwise noted.)

REV. 0

DAC8043A

ABSOLUTE MAXIMUM RATINGS*

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +8 V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

18 V

Logic Inputs to GND . . . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

OUT

to GND . . . . . . . . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

OUT

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . 50 mA

Package Power Dissipation . . . . . . . . . . . . . (T

max T

Thermal Resistance

8-Lead Plastic DIP Package (N-8) . . . . . . . . . . . . 103

C/W

8-Lead SOIC Package (SO-8) . . . . . . . . . . . . . . . 158

C/W

TSSOP-8 Package (RU-8) . . . . . . . . . . . . . . . . . . 240

C/W

Maximum Junction Temperature (T

max) . . . . . . . . +150

Operating Temperature Range . . . . . . . . . . 40

C to +85

Storage Temperature Range . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN FUNCTION DESCRIPTIONS

#(*)

Name Function

1(7)

REF

DAC Reference Input Pin. Establishes DAC full-
scale voltage. Constant input resistance versus
code.

2 (8) R

Internal Matching Feedback Resistor. Connect
to external op amp output.

3 (1) I

OUT

DAC Current Output, full-scale output 1 LSB
less than reference input voltage V

REF

4 (2) GND

Analog and Digital Ground.

5 (3)

Load Strobe, Level-Sensitive Digital Input.
Transfers shift-register data to DAC register
while active low. See truth table for operation.

6 (4) SRI

12-Bit Serial Register Input, data loads directly
into the shift register MSB first. Extra leading
bits are ignored.

7 (5) CLK

Clock Input, positive-edge clocks data into shift
register.

8 (6) V

Positive Power Supply Input. Specified range of
operation +5 V

10%.

*Note Pin numbers in parenthesis represent the rotated pinout of the

DAC8043A1ES and DAC8043A1FS models.

DAC8043AE/F PIN CONFIGURATIONS

SO-8

DAC8043A

ES/FS

TSSOP-8

DAC8043A

FRU

TOP VIEW

(Not to Scale)

OUT

GND

REF

CLK

SRI

PDIP-8

DAC8043A

EP/FP

DAC8043A1E AND DAC8043A1F PIN CONFIGURATION

(Rotated Pinout)

TOP VIEW

(Not to Scale)

OUT

GND

REF

CLK

SRI

SO-8

DAC8043A1ES
DAC8043A1FS

ORDERING GUIDE

INL

Package

Model

(LSB) Temp

Description

Option

DAC8043AEP

0.5

40/+85

8-Lead P-DIP

N-8

DAC8043AES

0.5

40/+85

8-Lead SOIC

SO-8

DAC8043A1ES

0.5

40/+85

8-Lead SOIC

SO-8

DAC8043AFP

1.0

40/+85

8-Lead P-DIP

N-8

DAC8043AFS

1.0

40/+85

8-Lead SOIC

SO-8

DAC8043A1FS

1.0

40/+85

8-Lead SOIC*

SO-8

DAC8043AFRU

1.0

40/+85

TSSOP-8

RU-8

NOTES
The DAC8043A contains 346 transistors. The die size measures 70.3 mil

57.1 mil, 4014 sq mil.
*The DAC8043A1ES and DAC8043A1FS have a rotated pinout.
TSSOP-8 Package Branding:
Line 1: yww (data code: year, work week).
Line 2: 8043A.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8043A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0

DAC8043A

SRI

CLK

SRI

CLK

OUT

DATA LOADED MSB(D11) FIRST

DAC REGISTER LOAD

D11

D10

LD1

1 LSB

ERROR BAND

Dxx

ASB

Figure 2. Timing Diagram

Table I. Control-Logic Truth Table

CLK

Serial Shift Register Function

DAC Register Function

Shift-Register-Data Advanced One Bit

Latched

No Effect

Updated with Current Shift Register Contents

No Effect

Latched All Zeros

NOTES
u positive logic transition.
The DAC Register

LD input is level-sensitive. Any time LD is logic-low data in the serial register will directly control the

switches in the R-2R DAC ladder.

TOTAL UNADJUSTED ERROR LSB

FREQUENCY

1.0

0.5

0.0

0.5

SS = 200 UNITS
T

= +25 C

= +5V

REF

= +10V

Figure 3. Total Unadjusted Error Histogram

Typical Performance Characteristics

FULL SCALE TEMPCO ppm/ C

FREQUENCY

SS = 200 UNITS
T

= 40 C TO +85 C

= +5V

REF

= +10V

Figure 4. Full-Scale Output Tempco Histogram

REV. 0

DAC8043A

LOGIC INPUT VOLTAGE Volts

SUPPLY CURRENT I

 mA

0.1

0.2

0.5

= +25 C

= +5V

0.5

1.5

2.5

3.5

4.5

0.3

0.4

Figure 5. Supply Current vs. Logic Input Voltage

TEMPERATURE C

0.01

0.001

55

0.1

= +5V

LOGIC

= 0V OR V

35

15

105

125

Figure 6. Supply Current vs. Temperature

FREQUENCY Hz

500

10k

1000

= +5V

REF

= +10V

= +25 C

100k

10M

100M

1500

2000

3000

3500

2500

CODE = F55H

CODE = 800H

CODE = FFFH

Figure 7. Supply Current vs. Clock Frequency

FREQUENCY Hz

PSRR dB

10k

= +5V 10%

100k

10M

100

Figure 8. Power Supply Rejection vs. Frequency

CODE Decimal

DNL LSB

0.5

1024

2048

3072

4096

0.4

0.3

0.2

0.1

0.2

0.4

0.5

= +5V

REF

= +10V

SUPERIMPOSED: T

= 40 C, +25 C, +85 C

512

1536

2560

3584

0.1

0.3

Figure 9. Linearity Error vs. Digital Code

OPAMP OFFSET V

 V

INL LSB

1000

2000

= +5V

REF

= +10V

= +25 C

Figure 10. Linearity Error vs. External Op Amp V

REV. 0

DAC8043A

20mV

= +5V

REF

= +10V

CLK

= 2.5MHz

CODE: 7FF

TO 800

OUT

(10mV/DIV)

TIME 200ns/DIV

(5V/DIV)

Figure 11. Midscale Transition Performance

= +5V

REF

= +10V

= +25 C

CLK

(5V/DIV)

TIME 1 s/DIV

OUT

(5V/DIV)

Figure 12. Large Signal Settling Time

FREQUENCY Hz

10k

100k

10M

ALL BITS ON

DATA BITS "ON"

(ALL OTHER DATA BITS "OFF")

(MSB) B

(LSB) B

ATTENUATION dB

108

100

Figure 13. Reference Multiplying Bandwidth vs. Fre-
quency and Code

REF

 Volts

INL LSB

0.5

0.25

0.5

0.25

= +5V

= +25 C

Figure 14. Linearity Error vs. Reference Voltage

HOURS OF OPERATION AT +150 C

NOMINAL CHANGE IN VOLTAGE mV

1.0

CODE = 000

CODE = FFF

SAMPLE SIZE = 50

0.2

0.4

0.6

0.8

1.2

100

200

300

400

500

600

Figure 15. Long-Term Drift Accelerated by Burn-In

95

0.0018

10k

100k

THD %

100

0.0032

0.0056

0.010

0.018

0.032

90

85

80

75

70

REF

= 4V p-p

OUTPUT OP AMP: OP42

THD dB

FREQUENCY Hz

Figure 16. THD vs. Frequency

REV. 0

DAC8043A

PARAMETER DEFINITIONS

INTEGRAL NONLINEARITY (INL)

This is the single most important DAC specification. ADI mea-
sures INL as the maximum deviation of the analog output (from
the ideal) from a straight line drawn between the end points. It
is expressed as a percent of full-scale range or in terms of LSBs.
Refer to Analog Devices Data Reference Manual for additional
digital-to-analog converter definitions.

INTERFACE LOGIC INFORMATION

The DAC8043A has been designed for ease of operation. The
timing diagram, Figure 2, illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is trans-
ferred to the DAC register by taking

LD momentarily low.

DIGITAL SECTION

The DAC8043A's digital inputs, SRI,

LD, and CLK, are TTL

compatible. The input voltage levels affect the amount of cur-
rent drawn from the supply; peak supply current occurs as the
digital input (VIN) passes through the transition region. See the
Supply Current vs. Logic Input Voltage graph located in the
typical performance characteristics curves. Maintaining the
digital input voltage levels as close as possible to the supplies,
VDD and GND, minimizes supply current consumption. The
DAC8043A's digital inputs have been designed with ESD resis-
tance incorporated through careful layout and the inclusion of
input protection circuitry. Figure 17 shows the input protection
diodes and series resistor; this input structure is duplicated on
each digital input. High voltage static charges applied to the
inputs are shunted to the supply and ground rails through for-
ward biased diodes. These protection diodes were designed to
clamp the inputs to well below dangerous levels during static
discharge conditions.

, CLK, SRI

GND

Figure 17. Digital Input Protection

GENERAL CIRCUIT INFORMATION

The DAC8043A is a 12-bit multiplying D/A converter with a
very low temperature coefficient. It contains an R-2R resistor
ladder network, data input and control logic, and two data
registers.

The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift regis-
ter and then transferred, in parallel, to the 12-bit DAC register.

The analog portion of the DAC8043A contains an inverted
R-2R ladder network consisting of silicon-chrome, highly-stable
(+50 ppm/

C) thin-film resistors, and twelve pairs of NMOS

current-steering switches, see Figure 18. These switches steer
binarily weighted currents into either I

OUT

or GND; this yields a

constant current in each ladder leg, regardless of digital input

code. This constant current results in a constant input resis-
tance at V

REF

equal to R. The V

REF

input may be driven by any

reference voltage or current, ac or dc that is within the limits
stated in the Absolute Maximum Ratings.

10k

20k

10k

20k

10k

S12

20k

10k

BIT 1 (MSB)

BIT 2

BIT 3

BIT 12 (LSB)

FEEDBACK

REF

OUT

GND

DIGITAL INPUTS

(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")

*THESE SWITCHES PERMANENTLY "ON"

Figure 18. Simplified DAC Circuit

The twelve output current steering NMOS FET switches are in
series with each R-2R resistor.

To further ensure accuracy across the full temperature range,
permanently "ON" MOS switches were included in series with
the feedback resistor and the R-2R ladder's terminating resistor.
Figure 18 shows the location of the series switches. During any
testing of the resistor ladder or R

FEEDBACK

(such as incoming

inspection), V

must be present to turn "ON" these series

switches.

DYNAMIC PERFORMANCE

OUTPUT IMPEDANCE

The DAC8043A's output resistance, as in the case of the output
capacitance, varies with the digital input code. This resistance,
looking back into the I

OUT

terminal, may be between 10 k

(the

feedback resistor alone when all digital inputs are LOW) and
7.5 k

(the feedback resistor in parallel with approximate 30 k

of the R-2R ladder network resistance when any single bit logic
is HIGH). Static accuracy and dynamic performance will be
affected by these variations.

APPLICATIONS INFORMATION

In most applications, linearity depends upon the potential of the
I

OUT

and GND pins being at the same voltage potential. The

DAC is connected to an external precision op amp inverting
input. The external amplifiers noninverting input should be tied
directly to ground without the usual bias current compensating
resistor. (See Figures 19 and 20.) The selected amplifier should
have a low input bias current and low drift over temperature.
The amplifiers input offset voltage should be nulled to less than
200 microvolts (less than 10% of 1 LSB). All grounded pins
should tie to a single common ground point to avoid ground loops.
The V

power supply should have a low noise level with ad-

equate bypassing. It is best to operate the DAC8043A from the
analog power supply and grounds.

REV. 0

DAC8043A

C349981/99

PRINTED IN U.S.A.

UNIPOLAR 2-QUADRANT MULTIPLYING

The most straightforward application of the DAC8043A is in
the 2-quadrant multiplying configuration shown in Figure 19. If
the reference input signal is replaced with a fixed dc voltage
reference, the DAC output will provide a proportional dc volt-
age output according to the transfer equation:

OUT

= D/4096

REF

where D is the decimal data loaded into the DAC register and
V

REF

is the externally applied reference voltage source.

REF

OUT

GND

OP77

10V

OUT

DIGITAL INPUTS OMITTED FOR CLARITY

10pF

Figure 19. Unipolar (2-Quadrant) Operation

BIPOLAR 4-QUADRANT MULTIPLYING

Figure 20 shows a suggested circuit to achieve 4-quadrant mul-
tiplying operation. The summing amplifier multiplies V

OUT1

2, and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places V

OUT2

at zero volts.

The negative full-scale voltage will be V

REF

when the DAC is

loaded with all zeros. The positive full-scale output will be
(V

REF

1 LSB) when the DAC is loaded with all ones. Thus

the digital coding is offset binary. The voltage output transfer
equation for various input data and reference (or signal) values
follows:

OUT2

= (D/2048 1)

REF

where D is the decimal data loaded into the DAC register and
V

REF

is the externally applied reference voltage source.

Precision resistors will be necessary to avoid ratio errors. Other-
wise trimming will be required to achieve full accuracy specifica-
tions available from the DAC8043A device. See the various
Analog Devices Digital Potentiometer products for automated
trimming solutions (e.g., the AD5204 for low voltage applica-
tions or the AD7376 for high voltage applications).

(0V TO V

REF

)

REF

OUT

GND

10V

OUT1

DIGITAL INPUTS OMITTED FOR CLARITY

OP213

10k

OP213

OUT2

20k

10pF

Figure 20. Bipolar (4-Quadrant) Operation

8-Lead SOIC (SO-8)

0.1968 (5.00)

0.1890 (4.80)

0.2440 (6.20)

0.2284 (5.80)

PIN 1

0.1574 (4.00)

0.1497 (3.80)

0.0688 (1.75)

0.0532 (1.35)

SEATING

PLANE

0.0098 (0.25)

0.0040 (0.10)

0.0192 (0.49)

0.0138 (0.35)

0.0500

(1.27)

BSC

0.0098 (0.25)

0.0075 (0.19)

0.0500 (1.27)

0.0160 (0.41)

8°
0°

0.0196 (0.50)

0.0099 (0.25)

x 45°

8-Lead Plastic DIP (N-8)

0.430 (10.92)

0.348 (8.84)

0.280 (7.11)
0.240 (6.10)

PIN 1

SEATING
PLANE

0.022 (0.558)
0.014 (0.356)

0.060 (1.52)
0.015 (0.38)

0.210 (5.33)

MAX

0.130
(3.30)
MIN

0.070 (1.77)
0.045 (1.15)

0.100

(2.54)

BSC

0.160 (4.06)
0.115 (2.93)

0.325 (8.25)
0.300 (7.62)

0.015 (0.381)
0.008 (0.204)

0.195 (4.95)
0.115 (2.93)

8-Lead TSSOP (RU-8)

0.122 (3.10)

0.114 (2.90)

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.0256 (0.65)

BSC

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0433
(1.10)
MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

8
0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

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