REV. C

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

12-Bit Serial Daisy-Chain

CMOS D/A Converter

DAC8143

FUNCTIONAL BLOCK DIAGRAM

INPUT 12-BIT

SHIFT REGISTER

DAC REGISTER

12-BIT

D/A CONVERTER

DAC8143

LOAD

OUT

CLK

OUT1

OUT2

AGND

SRO

DGND

SRI

STB

REF

CLR

ADDRESS BUS

ADDRESS

DECODER

STROBE

LOAD

SRI

SRO

DAC8143

STROBE

LOAD

SRI

SRO

DAC8143

STROBE

LOAD

SRI

SRO

DAC8143

STROBE

LOAD

SRI

SRO

DAC8143

Figure 1. Multiple DAC8143s with Three-Wire Interface

FEATURES
Fast, Flexible, Microprocessor Interfacing in Serially

Controlled Systems

Buffered Digital Output Pin for Daisy-Chaining

Multiple DACs

Minimizes Address-Decoding in Multiple DAC

Systems--Three-Wire Interface for Any Number of DACs

One Data Line
One CLK Line
One Load Line

Improved Resistance to ESD
40 C to +85 C for the Extended Industrial Temperature

Range

APPLICATIONS
Multiple-Channel Data Acquisition Systems
Process Control and Industrial Automation
Test Equipment
Remote Microprocessor-Controlled Systems

GENERAL INFORMATION

The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A
converter that features serial data input and buffered serial data
output. It was designed for multiple serial DAC systems, where
serially daisy-chaining one DAC after another is greatly simplified.

The DAC8143 also minimizes address decoding lines enabling
simpler logic interfacing. It allows three-wire interface for any
number of DACs: one data line, one CLK line and one load line.

Serial data in the input register (MSB first) is sequentially
clocked out to the SRO pin as the new data word (MSB first) is
simultaneously clocked in from the SRI pin. The strobe inputs
are used to clock in/out data on the rising or falling (user
selected) strobe edges (STB

, STB

STB3, STB

When the shift register's data has been updated, the new data
word is transferred to the DAC register with use of

LD1 and

LD2 inputs.

Separate LOAD control inputs allow simultaneous output up-
dating of multiple DACs. An asynchronous CLEAR input
resets the DAC register without altering data in the input
register.

Improved linearity and gain error performance permits reduced
circuit parts count through the elimination of trimming compo-
nents. Fast interface timing reduces timing design considerations
while minimizing microprocessor wait states.

The DAC8143 is available in plastic packages that are compat-
ible with autoinsertion equipment.

Plastic packaged devices come in the extended industrial tem-
perature range of 40

C to +85

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 1999

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Conditions

Min

Typ

Max

Units

STATIC ACCURACY

Resolution

Bits

Nonlinearity

INL

LSB

Differential Nonlinearity

DNL

LSB

Gain Error

FSE

LSB

Gain Tempco (

Gain/

Temp)

GFS

ppm/

Power Supply Rejection Ratio

(

Gain/

)

PSRR

0.0006

0.002

%/%

Output Leakage Current

LKG

= +25

= Full Temperature Range

Zero Scale Error

5, 6

ZSE

= +25

0.002

0.03

LSB

= Full Temperature Range

0.01

0.15

LSB

Input Resistance

REF

AC PERFORMANCE

Output Current Settling Time

3, 8

0.380

AC Feedthrough Error

REF

to I

OUT1

)

3, 9

REF

= 20 V p-p @ f = 10 kHz, T

= +25

2.0

mV p-p

Digital-to-Analog Glitch Energy

3, 10

REF

= 0 V, I

OUT

Load = 100

, C

EXT

= 13 pF

nVs

Total Harmonic Distortion

THD

REF

= 6 V rms @ 1 kHz

DAC Register Loaded with All 1s

Output Noise Voltage Density

3, 11

10 Hz to 100 kHz Between R

and I

OUT

nV/

DIGITAL INPUTS/OUTPUT

Digital Input HIGH

2.4

Digital Input LOW

0.8

Input Leakage Current

= 0 V to +5 V

Input Capacitance

= 0 V

Digital Output High

= 200

Digital Output Low

= 1.6 mA

0.4

ANALOG OUTPUTS

Output Capacitance

OUT1

Digital Inputs = All 1s

OUT2

Digital Inputs = All 0s

Output Capacitance

OUT1

Digital Inputs = All 0s

OUT2

Digital Inputs = All 1s

TIMING CHARACTERISTICS

Serial Input to Strobe Setup Times

DS1

STB

Used as the Strobe

STB

= 80 ns)

DS2

STB

Used as the Strobe

DS3

STB

Used as the Strobe T

= +25

= Full Temperature Range

DS4

STB

Used as the Strobe

DH1

STB

Used as the Strobe T

= +25

= Full Temperature Range

DH2

STB

Used as the Strobe T

= +25

= Full Temperature Range

Serial Input to Strobe Hold Times

STB

= 80 ns)

DH3

STB

Used as the Strobe

DH4

STB

Used as the Strobe

REV. C

(@ V

= +5 V; V

REF

= +10 V; V

OUT1

= V

OUT2

= V

AGND

= V

DGND

= 0 V; T

= Full Temperature

Range specified under Absolute Maximum Ratings, unless otherwise noted.)

DAC8143SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

DAC8143

Parameter

Symbol

Conditions

Min

Typ

Max

Units

STB to SRO Propagation Delay

= +25

220

= Full Temperature Range

300

SRI Data Pulsewidth

SRI

100

STB

Pulsewidth (

STB1 = 80 ns)

STB1

STB

Pulsewidth (

STB2 = 100 ns)

STB2

STB

Pulsewidth (

STB3 = 80 ns)

STB3

STB

Pulsewidth (

STB4 = 80 ns)

STB4

Load Pulsewidth

LD1

, t

LD2

= +25

140

= Full Temperature Range

180

LSB Strobe into Input Register

to Load DAC Register Time

ASB

CLR Pulsewidth

CLR

POWER SUPPLY

Supply Voltage

4.75

5.25

Supply Current

All Digital Inputs = V

or V

All Digital Inputs = 0 V or V

0.1

Power Dissipation

Digital Inputs = 0 V or V

0.5

5 V

0.1 mA

Digital Inputs = V

or V

5 V

2 mA

NOTES

All grades are monotonic to 12 bits over temperature.

Using internal feedback resistor.

Guaranteed by design and not tested.

Applies to I

OUT1

; all digital inputs = V

, V

REF

= +10 V; specification also applies for I

OUT2

when all digital inputs = V

REF

= +10 V, all digital inputs = 0 V.

Calculated from worst case R

REF

: I

ZSE

(in LSBs) = (R

REF

LKG

4096) /V

REF

Absolute temperature coefficient is less than +300 ppm/

OUT

, Load = 100

. C

EXT

= 13 pF, digital input = 0 V to V

or V

to 0 V. Extrapolated to 1/2 LSB: t

= propagation delay (t

) +9

, where

equals measured

time constant of the final RC decay.

All digital inputs = 0 V.

REF

= 0 V, all digital inputs = 0 V to V

or V

to 0 V.

Calculations from e

4K TRB where:

K = Boltzmann constant, J/KR = resistance

T = resistor temperature, K B = bandwidth, Hz

Digital inputs are CMOS gates; I

typically 1 nA at +25

Measured from active strobe edge (STB) to new data output at SRO; C

= 50 pF.

Minimum low time pulsewidth for STB

, STB

, and STB

, and minimum high time pulsewidth for STB

Specifications subject to change without notice.

(@ V

= +5 V; V

REF

= +10 V; V

OUT1

= V

0UT2

= V

AGND

= V

DGND

= 0 V; T

= Full

Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)

DAC8143

REV. C

DAC8143

REV. C

PIN CONNECTIONS

16-Lead Epoxy Plastic DIP

16-Lead SOIC

TOP VIEW

(Not to Scale)

OUT1

DAC8143

OUT2

REF

AGND

STB

CLR

DGND

SRO

STB

SRI

STB

ABSOLUTE MAXIMUM RATINGS

= +25

C, unless otherwise noted.)

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

REF

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

RFB

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . V

+ 0.3 V

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . V

+ 0.3 V

Digital Input Voltage Range . . . . . . . . . . . . . . . 0.3 V to V

Output Voltage (Pin 1, Pin 2) . . . . . . . . . . . . . . 0.3 V to V

Operating Temperature Range

FP/FS Versions . . . . . . . . . . . . . . . . . . . . . 40

C to +85

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150

Storage Temperature . . . . . . . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300

Package Type

Units

16-Lead Plastic DIP

C/W

16-Lead SOIC

C/W

is specified for worst case mounting conditions, i.e.,

is specified for

device in socket for P-DIP package;

is specified for device soldered to

printed circuit board for SOIC package.

CAUTION

1. Do not apply voltage higher than V

or less than DGND po-

tential on any terminal except V

REF

(Pin 15) and R

(Pin 16).

2. The digital control inputs are Zener-protected; however,

permanent damage may occur on unprotected units from
high energy electrostatic fields. Keep units in conductive
foam at all times until ready to use.

3. Use proper antistatic handling procedures.

4. Absolute Maximum Ratings apply to packaged devices.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device.

ORDERING GUIDE

Gain

Temperature

Package

Model

Nonlinearity

Error

Range

Descriptions

Options

DAC8143FP

1 LSB

2 LSB

C to +85

16-Lead Plastic DIP

N-16

DAC8143FS

1 LSB

2 LSB

C to +85

16-Lead SOIC

R-16W

Die Size: 99

107 mil, 10,543 sq. mils.

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8143 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

DAC8143

REV. C

FREQUENCY Hz

THD dB

90

0.032

THD %

0.010

85

80

75

70

95

0.018

0.0056

0.0032

0.0018

100

10k

100k

= 5V rms

OUTPUT OP AMP: OP-42

Figure 3. Multiplying Mode Total Harmonic
Distortion vs. Frequency

Typical Performance Characteristics

ALL BITS ON

100

FREQUENCY Hz

B10

ATTENUATION dB

(MSB) B11

B9
B8
B7
B6
B5
B4
B3
B2
B1

(LSB) B0

DATA BITS "ON"

(ALL OTHER

DATA BITS "OFF")

10k

100k

10M

108

Figure 2. Multiplying Mode Frequency
Response vs. Digital Code

 Volts

 mA

Figure 4. Supply Current vs. Logic

Input Voltage

 Volts

THRESHOLD VOLTAGE Volts

2.4

0.8

Figure 7. Logic Threshold Voltage
vs. Supply Voltage

0.5

DIGITAL INPUT CODE Decimal

LINEARITY ERROR LSB

0.4

0.3

0.2

0.1

0.0

0.1

0.2

0.3

0.4

0.5

1024

2048

3072

4095

1536

2560

3584

512

Figure 5. Linearity Error vs. Digital

Code

0.5

REF

 Volts

DNL LSB

0.25

0.5

Figure 8. DNL Error vs. Reference
Voltage

0.5

REF

 Volts

INL LSB

0.25

0.5

Figure 6. Linearity Error vs. Refer-

ence Voltage

SRO VOLTAGE OUT Volts

SINK

10

20

30

40

SOURCE

OUTPUT CURRENT mA

= +25 C

LOGIC 1

LOGIC 0

Figure 9. Digital Output Voltage vs.
Output Current

DAC8143

REV. C

DEFINITION OF SPECIFICATIONS

RESOLUTION

The resolution of a DAC is the number of states (2

) into which

the full-scale range (FSR) is divided (or resolved), where "n" is
equal to the number of bits.

SETTLING TIME

Time required for the analog output of the DAC to settle to
within 1/2 LSB of its final value for a given digital input stimu-
lus; i.e., zero to full-scale.

GAIN

Ratio of the DAC's external operational amplifier output voltage
to the V

REF

input voltage when all digital inputs are HIGH.

FEEDTHROUGH ERROR

Error caused by capacitive coupling from V

REF

to output.

Feedthrough error limits are specified with all switches off.

OUTPUT CAPACITANCE

Capacitance from I

OUT1

to ground.

OUTPUT LEAKAGE CURRENT

Current appearing at I

OUT1

when all digital inputs are LOW, or

at I

OUT2

terminal when all inputs are HIGH.

GENERAL CIRCUIT INFORMATION

The DAC8143 is a 12-bit serial-input, buffered serial-output,
multiplying CMOS D/A converter. It has an R-2R resistor lad-
der network, a 12-bit input shift register, 12-bit DAC register,
control logic circuitry, and a buffered digital output stage.

The control logic forms an interface in which serial data is
loaded, under microprocessor control, into the input shift regis-
ter and then transferred, in parallel, to the DAC register. In
addition, buffered serial output data is present at the SRO pin
when input data is loaded into the input register. This buffered
data follows the digital input data (SRI) by 12 clock cycles and
is available for daisy-chaining additional DACs.

An asynchronous CLEAR function allows resetting the DAC
register to a zero code (0000 0000 0000) without altering data
stored in the registers.

A simplified circuit of the DAC8143 is shown in Figure 10. An
inversed R-2R ladder network consisting of silicon-chrome,
thin-film resistors, and twelve pairs of NMOS current-steering
switches. These switches steer binarily weighted currents into
either I

OUT1

or I

OUT2

. Switching current to I

OUT1

or I

OUT2

yields

a constant current in each ladder leg, regardless of digital input
code. This constant current results in a constant input resis-
tance at V

REF

equal to R (typically 11 k

). The V

REF

input may

be driven by any reference voltage or current, ac or dc, that is
within the limits stated in the Absolute Maximum Ratings chart.

The twelve output current-steering switches are in series with
the R-2R resistor ladder, and therefore, can introduce bit errors.
It was essential to design these switches such that the switch
"ON" resistance be binarily scaled so that the voltage drop
across each switch remains constant. If, for example, Switch 1
of Figure 10 was designed with an "ON" resistance of 10

Switch 2 for 20

, etc., a constant 5 mV drop would then be

maintained across each switch.

To further ensure accuracy across the full temperature range,
permanently "ON" MOS switches were included in series with
the feedback resistor and the R-2R ladder's terminating resistor.
The Simplified DAC Circuit, Figure 10, shows the location of
these switches. These series switches are equivalently scaled to
two times Switch 1 (MSB) and top Switch 12 (LSB) to main-
tain constant relative voltage drops with varying temperature.
During any testing of the resistor ladder or R

FEEDBACK

(such as

incoming inspection), V

must be present to turn "ON" these

series switches.

REF

FEEDBACK

OUT2

OUT1

10k

20k

10k

BIT 1 (MSB)

BIT 12 (LSB)

BIT 3

BIT 2

DIGITAL INPUTS

(SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")

THESE SWITCHES

PERMANENTLY "ON"

Figure 10. Simplified DAC Circuit

DAC8143

REV. C

ESD PROTECTION

The DAC8143 digital inputs have been designed with ESD
resistance incorporated through careful layout and the inclusion
of input protection circuitry.

Figure 11 shows the input protection diodes. High voltage static
charges applied to the digital inputs are shunted to the supply
and ground rails through forward biased diodes.

These protection diodes were designed to clamp the inputs well
below dangerous levels during static discharge conditions.

DTL/TTL/CMOS

INPUTS

Figure 11. Digital Input Protection

EQUIVALENT CIRCUIT ANALYSIS

Figures 12 and 13 show equivalent circuits for the DAC8143's
internal DAC with all bits LOW and HIGH, respectively. The
reference current is switched to I

OUT2

when all data bits are LOW,

and to I

OUT1

when all bits are HIGH. The I

LEAKAGE

current

source is the combination of surface and junction leakages to the
substrate. The 1/4096 current source represents the constant
1-bit current drain through the ladder's terminating resistor.

Output capacitance is dependent upon the digital input code.
This is because the capacitance of a MOS transistor changes
with applied gate voltage. This output capacitance varies be-
tween the low and high values.

FEEDBACK

OUT1

OUT2

R = 10k

LEAKAGE

60pF

LEAKAGE

90pF

1/4096

R = 10k

REF

Figure 12. Equivalent Circuit (All Inputs LOW)

OUT2

LEAKAGE

60pF

FEEDBACK

OUT1

R = 10k

LEAKAGE

90pF

1/4096

R = 10k

REF

Figure 13. Equivalent Circuit (All Inputs HIGH)

DYNAMIC PERFORMANCE

ANALOG OUTPUT IMPEDANCE

The output resistance, as in the case of the output capacitance,
varies with the digital input code. This resistance, looking back
into the I

OUT1

terminal, varies between 11 k

(the feedback

resistor alone when all digital input are LOW) and 7.5 k

(the

feedback resistor in parallel with approximately 30 k

of the

R-2R ladder network resistance when any single bit logic is
HIGH). Static accuracy and dynamic performance will be af-
fected by these variations.

The gain and phase stability of the output amplifier, board
layout, and power supply decoupling will all affect the dynamic
performance of the DAC8143. The use of a small compensation
capacitor may be required when high speed operational amplifi-
ers are used. It may be connected across the amplifier's feed-
back resistor to provide the necessary phase compensation to
critically damp the output.

The considerations when using high speed amplifiers are:

1. Phase compensation (see Figures 16 and 17).
2. Power supply decoupling at the device socket and use of

proper grounding techniques.

OUTPUT AMPLIFIER CONSIDERATIONS

When using high speed op amps, a small feedback capacitor
(typically 5 pF30 pF) should be used across the amplifiers to
minimize overshoot and ringing. For low speed or static
applications, ac specifications of the amplifier are not very criti-
cal. In high speed applications, slew rate, settling time, open-
loop gain and gain/phase margin specifications of the amplifier
should be selected for the desired performance. It has already
been noted that an offset can be caused by including the usual
bias current compensation resistor in the amplifier's noninvert-
ing input terminal. This resistor should not be used. Instead, the
amplifier should have a bias current that is low over the tem-
perature range of interest.

Static accuracy is affected by the variation in the DAC's output
resistance. This variation is best illustrated by using the circuit
of Figure 14 and the equation:

ERROR

= V

REF

ETC

OP-77

Figure 14. Simplified Circuit

DAC8143

REV. C

Where R

is a function of the digital code, and:

= 10 k

for more than four bits of Logic 1,

= 30 k

for any single bit of Logic 1.

Therefore, the offset gain varies as follows:

at code 0011 1111 1111,

ERROR1

= V

10 k

= 2 V

at code 0100 0000 0000,

ERROR2

= V

10 k

30 k

= 4/3 V

The error difference is 2/3 V

Since one LSB has a weight (for V

REF

= +10 V) of 2.4 mV for

the DAC8143, it is clearly important that V

be minimized,

using either the amplifier's pulling pins, an external pulling
network, or by selection of an amplifier with inherently low V

Amplifiers with sufficiently low V

include OP77, OP97, OP07,

OP27, and OP42.

INTERFACE LOGIC OPERATION

The microprocessor interface of the DAC8143 has been design-
ed with multiple STROBE and LOAD inputs to maximize inter-
facing options. Control signals decoding may be done on chip or
with the use of external decoding circuitry (see Figure 21).

Serial data is clocked into the input register and buffered output
stage with STB

, STB

, or STB

. The strobe inputs are active

on the rising edge.

STB3 may be used with a falling edge clock

data.

WORD N

WORD N 1

WORD N 2

WORD N 1

WORD N

BIT 11

BIT 2

BIT 12

LSB

BIT 1

MSB

BIT 12

LSB

BIT 2

BIT 1

MSB

SRI

BIT 2

BIT 1

MSB

BIT 1

MSB

BIT 2

BIT 12

LSB

BIT 1

LSB

DS1

DS2

DS3

DS4

SRO

DH1

DH2

DH3

DH4

STB1

STB2

STB3

STB4

STB1

STB2

STB3

STB4

STROBE

(STB

, STB

)

LD1

LD2

SR1

ASB

AND LD

LOAD NEW 12-BIT WORD INTO

INPUT REGISTER AND SHIFT

OUT PREVIOUS WORD

LOAD INPUT REGISTER'S
DATA INTO DAC REGISTER

NOTES:

STROBE WAVEFORM IS INVERTED IF

STB

IS USED TO STROBE SERIAL DATA

BITS INTO INPUT REGISTER.

DATA IS STROBED INTO AND OUT OF

THE INPUT SHIFT REGISTER MSB FIRST.

Figure 15. Timing Diagram

Serial data output (SRO) follows the serial data input (SRI) by
12 clocked bits.

Holding any STROBE input at its selected state (i.e., STB

STB

or STB

at logic HIGH or STB

at logic LOW) will act to

prevent any further data input.

When a new data word has been entered into the input register,
it is transferred to the DAC register by asserting both LOAD
inputs.

The

CLR input allows asynchronous resetting of the DAC regis-

ter to 0000 0000 0000. This reset does not affect data held in
the input registers. While in unipolar mode, a CLEAR will
result in the analog output going to 0 V. In bipolar mode, the
output will go to V

REF

INTERFACE INPUT DESCRIPTION

STB

(Pin 4), STB

(Pin 8), STB

(Pin 11)--Input Register

and Buffered Output Strobe. Inputs Active on Rising
Edge. Selected to load serial data into input register and buff-
ered output stage. See Table I for details.

STB

3 (Pin 10)--Input Register and Buffered Output

Strobe Input. Active on Falling Edge. Selected to load serial
data into input register and buffered output stage. See Table I
for details.

1 (Pin 5), LD2

(Pin 9)--Load DAC Register Inputs.

Active Low. Selected together to load contents of input register
into DAC register.

CLR (Pin 13)--Clear Input. Active Low. Asynchronous.
When LOW, 12-bit DAC register is forced to a zero code (0000
0000 0000) regardless of other interface inputs.

DAC8143

REV. C

Table I. Truth Table

DAC8143 Logic Inputs
Input Register/
Digital Output

Control Inputs

DAC Register

Control Inputs

STB

CLR

DAC8143 Operation

Notes

Serial Data Bit Loaded from SRI

into Input Register and Digital Output

2, 3

(SRO Pin) after 12 Clocked Bits.

No Operation (Input Register and SRO)

Reset DAC Register to Zero Code

(Code: 0000 0000 0000)

1, 3

(Asynchronous Operation)

No Operation (DAC Register and SRO)

Load DAC Register with the Contents

of Input Register

NOTES

CLR = 0 asynchronously resets DAC Register to 0000 0000 0000, but has no effect on Input Register.

Serial data is loaded into Input Register MSB first, on edges shown.

g is positive edge, f is negative edge.

0 = Logic LOW, 1 = Logic HIGH, X = Don't Care.

APPLICATIONS INFORMATION

UNIPOLAR OPERATION (2-QUADRANT)

The circuit shown in Figures 16 and 17 may be used with an ac
or dc reference voltage. The circuit's output will range between
0 V and +10(4095/4096) V depending upon the digital input
code. The relationship between the digital input and the analog
output is shown in Table II. The V

REF

voltage range is the maxi-

mum input voltage range of the op amp or

25 V, whichever is

lowest.

Table II. Unipolar Code Table

Digital Input

Nominal Analog Output
(V

OUT

as Shown

MSB

LSB

in Figures 16 and 17)

1 1 1 1 1 1 1 1 1 1 1 1

REF

4095

4096

1 0 0 0 0 0 0 0 0 0 0 1

REF

2049

4096

1 0 0 0 0 0 0 0 0 0 0 0

REF

2048

4096

REF

0 1 1 1 1 1 1 1 1 1 1 1

REF

2047

4096

0 0 0 0 0 0 0 0 0 0 0 1

REF

4096

0 0 0 0 0 0 0 0 0 0 0 0

REF

4096

= 0

NOTES

Nominal full scale for the circuits of Figures 16 and 17 is given by

FS = V

REF

4095
4096

Nominal LSB magnitude for the circuits of Figures 16 and 17 is given by

LSB = V

REF

4096

or V

REF

OP-77

+5V

REF

FEEDBACK

OUT1

OUT2

AGND

DGND

SRO
(BUFFERED
DIGITAL
DATA OUT)

15pF

+15V

15V

OUT

4, 5

811

DAC8143

CONTROL

INPUTS

SRI

(SERIAL

DATA IN)

REF

10V

CLR

Figure 16. Unipolar Operation with High Accuracy Op
Amp (2-Quadrant)

OP-42

+5V

REF

FEEDBACK

OUT1

OUT2

AGND

DGND

SRO
(BUFFERED
DIGITAL
DATA OUT)

15pF

+15V

15V

OUT

4, 5

811

DAC8143

CONTROL

INPUTS

SRI

(SERIAL

DATA IN)

REF

10V

100

CLR

Figure 17. Unipolar Operation with Fast Op Amp and
Gain Error Trimming (2-Quadrant)

DAC8143

REV. C

In many applications, the DAC8143's zero scale error and low
gain error, permit the elimination of external trimming compo-
nents without adverse effects on circuit performance.

For applications requiring a tighter gain error than 0.024% at
25

C for the top grade part, or 0.048% for the lower grade part,

the circuit in Figure 17 may be used. Gain error may be trimmed
by adjusting R1.

The DAC register must first be loaded with all 1s. R1 is then
adjusted until V

OUT

= V

REF

(4095/4096). In the case of an

adjustable V

REF

, R1 and R

FEEDBACK

may be omitted, with V

REF

adjusted to yield the desired full-scale output.

BIPOLAR OPERATION (4-QUADRANT)

Figure 18 details a suggested circuit for bipolar, or offset binary,
operation. Table III shows the digital input-to-analog output
relationship. The circuit uses offset binary coding. Twos comple-
ment code can be converted to offset binary by software inver-
sion of the MSB or by the addition of an external inverter to the
MSB input.

Resistor R3, R4 and R5 must be selected to match within 0.01%
and must all be of the same (preferably metal foil) type to assure
temperature coefficient match. Mismatching between R3 and
R4 causes offset and full-scale error.

Calibration is performed by loading the DAC register with
1000 0000 0000 and adjusting R1 until V

OUT

= 0 V. R1 and

R2 may be omitted by adjusting the ratio of R3 to R4 to yield
V

OUT

= 0 V. Full scale can be adjusted by loading the DAC

REF

or the value of R5 until the desired V

OUT

is achieved.

Table III. Bipolar (Offset Binary) Code Table

Digital Input

Nominal Analog Output

MSB

LSB

OUT

as Shown in Figure 18)

1 1 1 1 1 1 1 1 1 1 1 1

REF

2047

2048

1 0 0 0 0 0 0 0 0 0 0 1

REF

2048

1 0 0 0 0 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1 1 1 1 1

REF

2048

0 0 0 0 0 0 0 0 0 0 0 1

REF

2047

2048

0 0 0 0 0 0 0 0 0 0 0 0

REF

2048

NOTES

Nominal full scale for the circuits of Figure 18 is given by

FS = V

REF

2047

2048

Nominal LSB magnitude for the circuits of Figure 18 is given by

LSB = V

REF

2048

DAISY-CHAINING DAC8143s

Many applications use multiple serial input DACs that use
numerous interconnecting lines for address decoding and data
lines. In addition, they use some type of buffering to reduce
loading on the bus. The DAC8143 is ideal for just such an
application. It not only reduces the number of interconnecting
lines, but also reduces bus loading. The DAC8143 can be daisy-
chained with only three lines: one data line, one CLK line and
one load line, see Figure 19.

OUT

1/2 OP200

+5V

100

SERIAL

DATA INPUT

4, 5

8-11

DGND

REF

SRI

CONTROL

BITS

SRO

CONTROL

INPUTS

FROM

SYSTEM

RESET

BUFFERED SERIAL
DATA OUT

AGND

OUT2

OUT1

DAC8143

C1
10-33pF

COMMON GROUND

10k

R4
20k

20k

1/2 OP200

CLR

Figure 18. Bipolar Operation (4-Quadrant, Offset Binary)

DAC8143

REV. C

ANALOG/DIGITAL DIVISION

The transfer function for the DAC8143 connect in the multiply-
ing mode as shown in Figures 16 and 17 is:

= V

...

where A

assumes a value of 1 for an "ON" bit and 0 for an

"OFF" bit.

The transfer function is modified when the DAC is connected in
the feedback of an operational amplifier as shown in Figure 20
and is:

...

The above transfer function is the division of an analog voltage
(V

REF

) by a digital word. The amplifier goes to the rails with all

bits "OFF" since division by zero is infinity. With all bits "ON"
the gain is 1 (

1 LSB). The gain becomes 4096 with the LSB,

Bit 12, "ON".

BUFFERED DIGITAL
DATA OUT

+5V

SRO

REF

OUT1

DAC8143

AGND

DGND

2 12

OUT

DIGITAL

INPUTS

OP-42

Figure 20. Analog/Digital Divider

APPLICATION TIPS

In most applications, linearity depends on the potential of I

OUT1,

OUT2,

and AGND (Pins 1, 2 and 3) being exactly equal to each

other. In most applications, the DAC is connected to an exter-
nal op amp with its noninverting input tied to ground (see Fig-
ures 16 and 17). The amplifier selected should have a low input
bias current and low drift over temperature. The amplifier's
input offset voltage should be nulled to less than

200

V (less

than 10% of 1 LSB).

The operational amplifier's noninverting input should have a
minimum resistance connection to ground; the usual bias cur-
rent compensation resistor should not be used. This resistor can
cause a variable offset voltage appearing as a varying output
error. All grounded pins should tie to a single common ground
point, avoiding ground loops. The V

power supply should

have a low noise level with no transients greater than +17 V.

It is recommended that the digital inputs be taken to ground or
V

via a high value (1 M

) resistor; this will prevent the accu-

mulation of static charge if the PC card is disconnected from the
system.

Peak supply current flows as the digital input pass through the
transition region (see Figure 4). The supply current decreases as
the input voltage approaches the supply rails (V

or DGND),

i.e., rapidly slewing logic signals that settle very near the supply
rails will minimize supply current.

INTERFACING TO THE MC6800

As shown in Figure 21, the DAC8143 may be interfaced to the
6800 by successively executing memory WRITE instruction
while manipulating the data between WRITEs, so that each
WRITE presents the next bit.

In this example, the most significant bits are found in memory
locations 0000 and 0001. The four MSBs are found in the lower
half of 0000, the eight LSBs in 0001. The data is taken from the
DB

line.

The serial data loading is triggered by STB

which is asserted by

a decoded memory WRITE to a memory location, R/

W, and

2. A WRITE to another address location transfers data from

input register to DAC register.

STB

DAC8143*

SRI

SRO

STB

CLR

74LS138

ADDRESS

DECODER

MC6800

16-BIT ADDRESS BUS

8-BIT DATA BUS

+5V

FROM SYSTEM RESET

ANALOG CIRCUITRY OMITTED FOR SIMPLICITY

Figure 21. DAC8143--MC6800 Interface

ADDRESS

DECODER

STROBE

LOAD

DAC8143

SRI

SRO

ADDRESS BUS

STROBE

LOAD

DAC8143

SRI

SRO

STROBE

LOAD

DAC8143

SRI

SRO

STROBE

LOAD

DAC8143

SRI

SRO

Figure 19. Multiple DAC8143s with Three-Wire Interface

DAC8143

REV. C

DAC8143 INTERFACE TO THE 8085

The DAC8143's interface to the 8085 microprocessor is shown
in Figure 22. Note that the microprocessor's SOD line is used
to present data serially to the DAC.

Data is strobed into the DAC8143 by executing memory write
instructions. The strobe 2 input is generated by decoding an
address location and

WR. Data is loaded into the DAC register

with a memory write instruction to another address location.

Serial data supplied to the DAC8143 must be present in the
right-justified format in registers H and L of the microprocessor.

STB

DAC8143*

SRI

SRO

STB

CLR

74LS138

ADDRESS

DECODER

ALE

SOD

8085

ADDRESS BUS (16)

DATA

+5V

FROM SYSTEM RESET

ANALOG CIRCUITRY OMITTED FOR SIMPLICITY

+5V

8212

(8)

(8) AD

07

Figure 22. DAC8143--8085 Interface

DAC8143 INTERFACE TO THE 68000

Figure 23 shows the DAC8143 configured to the 68000 micro-
processor. Serial data input is similar to that of the 6800 in
Figure 21.

STB

DAC8143

SRI

STB

CLR

ADDRESS

DECODER

68000 P

ADDRESS BUS

DATA BUS

FROM SYSTEM RESET

VMA

VPA

UDS

+5V

1/4 74HC125

STB

Figure 23. DAC8143 to 68000

P Interface

OUTLINE DIMENSIONS

Dimensions are shown in inches and (mm).

16-Lead Plastic DIP

(N-16)

PIN 1

0.840 (21.34)
0.745 (18.92)

0.280 (7.11)
0.240 (6.10)

SEATING
PLANE

0.060 (1.52)
0.015 (0.38)

0.210 (5.33)

MAX

0.022 (0.558)
0.014 (0.356)

0.160 (4.06)
0.115 (2.93)

0.100

(2.54)

BSC

0.070 (1.77)
0.045 (1.15)

0.130
(3.30)
MIN

0.195 (4.95)
0.115 (2.93)

0.015 (0.381)
0.008 (0.204)

0.325 (8.25)
0.300 (7.62)

16-Lead SOIC

(R-16W)

SEATING
PLANE

0.0118 (0.30)
0.0040 (0.10)

0.0192 (0.49)
0.0138 (0.35)

0.1043 (2.65)
0.0926 (2.35)

0.050 (1.27)

BSC

0.4193 (10.65)
0.3937 (10.00)

0.2992 (7.60)
0.2914 (7.40)

PIN 1

0.4133 (10.50)

0.3977 (10.00)

0.0125 (0.32)
0.0091 (0.23)

8
0

0.0291 (0.74)
0.0098 (0.25)

0.0500 (1.27)
0.0157 (0.40)

C3114c23/99

PRINTED IN U.S.A.

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