FUNCTIONAL BLOCK DIAGRAM
REG
A
SHIFT
REGISTER
DECODE
VOUTA
VOUTB
VOUTC
VOUTD
2
3
6
7
8
15
16
9
GND
CLSEL
4
VREFLO
VSS
5
VREFHI
VDD
10
12
11
13
14
SDI
CLK
NC
CS
LD
REG
A
1
DAC A
REG
B
DAC B
REG
C
DAC C
REG
D
DAC D
CLR
12
4
2
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Quad 12-Bit Serial
Voltage Output DAC
DAC8420
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Guaranteed Monotonic Over Temperature
Excellent Matching Between DACs
Unipolar or Bipolar Operation
Buffered Voltage Outputs
High Speed Serial Digital Interface
Reset to Zero- or Center-Scale
Wide Supply Range, +5 V-Only to 15 V
Low Power Consumption (35 mW max)
Available in 16-Pin DIP and SOL Packages
APPLICATIONS
Software Controlled Calibration
Servo Controls
Process Control and Automation
ATE
The DAC8420 is available in 16-pin epoxy DIP, cerdip, and
wide-body SOL (small-outline surface mount) packages. Opera-
tion is specified with supplies ranging from +5 V-only to
15 V,
with references of +2.5 V to
10 V respectively. Power dissipa-
tion when operating from
15 V supplies is less than 255 mW
(max), and only 35 mW (max) with a +5 V supply.
For applications requiring product meeting MIL-STD-883,
contact your local sales office for the DAC8420/883 data sheet,
which specifies operation over the 55
C to +125
C tempera-
ture range.
GENERAL DESCRIPTION
The DAC8420 is a quad, 12-bit voltage-output DAC with serial
digital interface, in a 16-pin package. Utilizing BiCMOS tech-
nology, this monolithic device features unusually high circuit
density and low power consumption. The simple, easy-to-use
serial digital input and fully buffered analog voltage outputs
require no external components to achieve specified performance.
The three-wire serial digital input is easily interfaced to micro-
processors running at 10 MHz rates, with minimal additional
circuitry. Each DAC is addressed individually by a 16-bit serial
word consisting of a 12-bit data word and an address header.
The user-programmable reset control CLR forces all four DAC
outputs to either zero or midscale, asynchronously overriding
the current DAC register values. The output voltage range, de-
termined by the inputs VREFHI and VREFLO, is set by the
user for positive or negative unipolar or bipolar signal swings
within the supplies allowing considerable design flexibility.
DAC8420SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
REV. 0
2
(at V
DD
= +5.0 V 5%, V
SS
= 0.0 V, V
VREFHI
= +2.5 V, V
VREFLD
= 0.0 V, and
V
SS
= 5.0 V 5%, V
VREFLO
= 2.5 V, 40 C
T
A
+85 C unless otherwise noted. See Note 1 for supply variations.)
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC ACCURACY
Integral Linearity "E"
INL
1/4
1
LSB
Integral Linearity "E"
INL
Note 2, V
SS
= 0 V
1/2
3
LSB
Integral Linearity "F"
INL
3/4
2
LSB
Integral Linearity "F"
INL
Note 2, V
SS
= 0 V
1
4
LSB
Differential Linearity
DNL
Monotonic Over Temperature
1/4
1
LSB
Min-Scale Error
ZSE
R
L
= 2 k
, V
SS
= 5 V
4
LSB
Full-Scale Error
FSE
R
L
= 2 k
, V
SS
= 5 V
4
LSB
Min-Scale Error
ZSE
Note 2, R
L
= 2 k
, V
SS
= 0 V
8
LSB
Full-Scale Error
FSE
Note 2, R
L
= 2 k
, V
SS
= 0 V
8
LSB
Min-Scale Tempco
TC
ZSE
Note 3, R
L
= 2 k
, V
SS
= 5 V
10
ppm/
C
Full-Scale Tempco
TC
FSE
Note 3, R
L
= 2 k
, V
SS
= 5 V
10
ppm/
C
MATCHING PERFORMANCE
Linearity Matching
1
LSB
REFERENCE
Positive Reference Input Range
V
VREFHI
Note 4
V
VREFLO
+2.5
V
DD
2.5
V
Negative Reference Input Range
V
VREFLO
Note 4
V
SS
V
VREFHI
2.5
V
Negative Reference Input Range
V
VREFLO
Note 4, V
SS
= 0 V
0
V
VREFHI
2.5
V
Reference High Input Current
I
VREFHI
Codes 000
H
, 555
H
0.75
0.25
+0.75
mA
Reference Low Input Current
I
VREFLO
Codes 000
H
, 555
H
, V
SS
= 5 V
1.0
0.6
mA
AMPLIFIER CHARACTERISTICS
Output Current
I
OUT
V
SS
= 5 V
1.25
+1.25
mA
Settling Time
t
S
to 0.01%, Note 5
8
s
Slew Rate
SR
10% to 90%, Note 5
1.5
V/
s
LOGIC CHARACTERISTICS
Logic Input High Voltage
V
INH
2.4
V
Logic Input Low Voltage
V
INL
0.8
V
Logic Input Current
I
IN
10
A
Input Capacitance
C
IN
Note 3
13
pF
LOGIC TIMING CHARACTERISTICS
3, 6
Data Setup Time
t
DS
25
ns
Data Hold
t
DH
55
ns
Clock Pulse Width HIGH
t
CH
90
ns
Clock Pulse Width LOW
t
CL
120
ns
Select Time
t
CSS
90
ns
Deselect Delay
t
CSH
5
ns
Load Disable Time
t
LD1
130
ns
Load Delay
t
LD2
35
ns
Load Pulse Width
t
LDW
80
ns
Clear Pulse Width
t
CLRW
150
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
PSRR
0.002
0.01
%/%
Positive Supply Current
I
DD
4
7
mA
Negative Supply Current
I
SS
6
3
mA
Power Dissipation
P
DISS
V
SS
= 0 V
20
35
mW
NOTES
1
All supplies can be varied
5% and operation is guaranteed. Device is tested with V
DD
= +4.75 V.
2
For single-supply operation (V
VREFLO
= 0 V, V
SS
= 0 V), due to internal offset errors INL and DNL are measured beginning at code 003
H
.
3
Guaranteed but not tested.
4
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
5
V
OUT
swing between +2.5 V and 2.5 V with V
DD
= 5.0 V.
6
All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
7
Typical values indicate performance measured at +25
C.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC ACCURACY
Integral Linearity "E"
INL
1/4
1/2
LSB
Integral Linearity "F"
INL
1/2
1
LSB
Differential Linearity
DNL
Monotonic Over Temperature
1/4
1
LSB
Min-Scale Error
ZSE
R
L
= 2 k
2
LSB
Full-Scale Error
FSE
R
L
= 2 k
2
LSB
Min-Scale Tempco
TC
ZSE
Note 2, R
L
= 2 k
4
ppm/
C
Full-Scale Tempco
TC
FSE
Note 2, R
L
= 2 k
4
ppm/
C
MATCHING PERFORMANCE
Linearity Matching
1
LSB
REFERENCE
Positive Reference Input Range
V
VREFHI
Note 3
V
VREFLO
+2.5
V
DD
2.5
V
Negative Reference Input Range
V
VREFLO
Note 3
10
V
VREFHI
2.5
V
Reference High Input Current
I
VREFHI
Codes 000
H
, 555
H
2.0
1.0
+2.0
mA
Reference Low Input Current
I
VREFLO
Codes 000
H
, 555
H
3.5
2.0
mA
AMPLIFIER CHARACTERISTICS
Output Current
I
OUT
5
+5
mA
Settling Time
t
S
to 0.01%, Note 4
13
s
Slew Rate
SR
10% to 90%, Note 4
2
V/
s
DYNAMIC PERFORMANCE
Analog Crosstalk
Note 2
>64
dB
Digital Feedthrough
Note 2
>72
dB
Large Signal Bandwidth
3 dB, V
VREFHI
= 5 V + 10 V p-p,
90
kHz
V
VREFLO
= 10 V, Note 2
Glitch Impulse
Code Transition = 7FF
H
to 800
H
, Note 2
64
nV-s
LOGIC CHARACTERISTICS
Logic Input High Voltage
V
INH
2.4
V
Logic Input Low Voltage
V
INL
0.8
V
Logic Input Current
I
IN
10
A
Input Capacitance
C
IN
Note 2
13
pF
LOGIC TIMING CHARACTERISTICS
2, 5
Data Setup Time
t
DS
25
ns
Data Hold
t
DH
20
ns
Clock Pulse Width HIGH
t
CH
30
ns
Clock Pulse Width LOW
t
CL
50
ns
Select Time
t
CSS
55
ns
Deselect Delay
t
CSH
15
ns
Load Disable Time
t
LD1
40
ns
Load Delay
t
LD2
15
ns
Load Pulse Width
t
LDW
45
ns
Clear Pulse Width
t
CLRW
70
ns
SUPPLY CHARACTERISTICS
Power Supply Sensitivity
PSRR
0.002
0.01
%/%
Positive Supply Current
I
DD
6
9
mA
Negative Supply Current
I
SS
8
5
mA
Power Dissipation
P
DISS
255
mW
NOTES
1
All supplies can be varied
5% and operation is guaranteed.
2
Guaranteed but not tested.
3
Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed.
4
V
OUT
swing between +10 V and 10 V.
5
All input control signals are specified with tr = tf =5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
Typical values indicate performance measured at +25
C.
Specifications subject to change without notice.
DAC8420
REV. 0
3
(at V
DD
= +15.0 V 5%, V
SS
= 15.0 V 5%, V
VREFHI
= +10.0 V,
V
VREFLO
= 10.0 V, 40 C
T
A
+85 C unless otherwise noted. See Note 1 for supply variations.)
DAC8420
REV. 0
4
WAFER TEST LIMITS
DAC8420G
Parameter
Symbol
Conditions
Limit
Units
Integral Linearity
INL
1
LSB max
Differential Linearity
DNL
1
LSB max
Min-Scale Offset
1
LSB max
Max-Scale Offset
1
LSB max
Logic Input High Voltage
V
INH
2.4
V min
Logic Input Low Voltage
V
INL
0.8
V max
Logic Input Current
I
IN
1
A max
Positive Supply Current
I
DD
8
mA max
Negative Supply Current
I
SS
7
mA max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +18.0 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, 18.0 V
V
SS
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +36.0 V
V
SS
to V
VREFLO
. . . . . . . . . . . . . . . . . . . . . . 0.3 V, V
SS
2.0 V
V
VREFHI
to V
VREFLO
. . . . . . . . . . . . . . . . . . . +2.0 V, V
DD
V
SS
V
VREFHI
to V
DD
. . . . . . . . . . . . . . . . . . . . . . . +2.0 V, +33.0 V
I
VREFHI
, I
VREFLO
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Digital Input Voltage to GND . . . . . . . . . 0.3 V, V
DD
+ 0.3 V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Operating Temperature Range
EP, FP, ES, FS, EQ, FQ . . . . . . . . . . . . . . 40
C to +85
C
Dice Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150
C
Storage Temperature . . . . . . . . . . . . . . . . . . 65
C to +150
C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300
C
Thermal Resistance
Package Type
JA
JC
Units
16-Pin Plastic DIP (P)
70
1
27
C/W
16-Pin Hermetic DIP (Q)
82
1
9
C/W
16-Lead Small Outline
Surface Mount (S)
86
2
22
C/W
NOTES
1
JA
is specified for worst case mounting conditions, i.e.,
JA
is specified for
device in socket.
2
JA
is specified for device on board.
CAUTION
1. Stresses above those listed under "Absolute Maximum Rat-
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this
specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device
reliability.
2. Digital inputs and outputs are protected, however, permanent
damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam or packaging
at all times until ready to use. Use proper antistatic handling
procedures.
3. Remove power before inserting or removing units from their
sockets.
4. Analog Outputs are protected from short circuits to ground
or either supply.
DICE CHARACTERISTICS
10
SDI
9
GND
8
VSS
7
VOUTA
CLR
15
CLSEL
16
(SUBSTRATE)
VDD
1
VOUTD
2
VOUTC 3
VREFLO 4
VREFHI 5
VOUTB 6
11 CLK
12 CS
14 LD
13 NC
NC = NO CONNECT
Die Size 0.119
0.283 inch, 33,677 sq. mils
(3.023
7.188 mm, 21.73 sq. mm)
Transistor Count 2,207
For additional DICE ordering information, refer to databook.
(at V
DD
= +15.0 V, V
SS
= 15.0 V, V
REFHI
= +10.0 V, V
REFLO
= 10.0 V, T
A
= +25 C
unless otherwise noted)
DAC8420
REV. 0
5
t
CSH
t
LD2
t
CSS
t
LD1
A1
A0
X
X
D11
D10
D9
D8
D4
D3
D2
D1
D0
CS
SDI
CLK
LD
DATA LOAD SEQUENCE
t
DS
t
DH
1LSB
t
S
t
LDW
t
LD2
t
CL
t
CH
t
CSH
SDI
CLK
CS
LD
V
OUT
DATA LOAD TIMING
t
CLRW
1LSB
t
S
CLSEL
CLR
V
OUT
CLEAR TIMING
Timing Diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DUT
10F
0.1F
+
1N4001
10V
NC
NC
5k
10
10F
0.1F
+
1N4001
+10V
10
10F
0.1F
+
1N4001
+15V
10
10F
0.1F
+
1N4001
15V
10
NC
NC
NC
10k
5k
NC = NO CONNECT
Burn-In Diagram
ORDERING GUIDE
Temperature
INL
Package
Package
Model
1
Range
( LSB)
Description
Option
2
DAC8420EP
40
C to +85
C
0.5
Plastic DIP
P
DAC8420EQ
40
C to +85
C
0.5
Cerdip
Q
DAC8420ES
40
C to +85
C
0.5
SOIC
SOL
DAC8420FP
40
C to +85
C
1.0
Plastic DIP
P
DAC8420FQ
40
C to +85
C
1.0
Cerdip
Q
DAC8420FS
40
C to +85
C
1.0
SOIC
SOL
DAC8420QBC
40
C to +85
C
1.0
Dice
3
NOTES
1
A complete /883 data sheet is available. For availability and burn-in informa-
tion, contact your local sales office.
2
PMI division letter designator.
3
Dice tested at +25
C only.
DAC8420
REV. 0
6
PIN CONFIGURATIONS
PIN FUNCTION DESCRIPTION
Power Supplies
VDD: Positive Supply, +5 V to +15 V.
VSS: Negative Supply, 0 V to 15 V.
GND: Digital Ground.
Clock
CLK: System Serial Data Clock Input, TTL/CMOS levels. Data presented to the input SDI is shifted into
the internal serial-parallel input register on the rising edge of clock. This input is logically ORed with CS.
Control Inputs
(All are CMOS/TTL compatible.)
CLR
: Asynchronous Clear, active low. Sets internal data registers A-D to zero or midscale, depending on cur-
rent state of CLSEL. The data in the serial input shift register is unaffected by this control.
CLSEL: Determines action of CLR. If HIGH, a Clear command will set the internal DAC registers A-D to
midscale (800
H
). If LOW, the registers are set to zero (000
H
).
CS
: Device Chip Select, active low. This input is logically ORed with the clock and disables the serial data
register input when HIGH. When LOW, data input clocking is enabled, see the Control Function Table.
LD
: Asynchronous DAC Register Load Control, active low. The data currently contained in the serial input
shift register is shifted out to the DAC data registers on the falling edge of LD, independent of CS. Input data
must remain stable while LD is LOW.
Data Input
(All are CMOS/TTL compatible.)
SDI: Serial Data Input. Data presented to this pin is loaded into the internal serial-parallel shift register, which
shifts data in beginning with DAC address Bit A1. This input is ignored when CS is HIGH.
The format of the 16-bit serial word is:
(FIRST)
(LAST)
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
A1
A0
NC
NC
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
--Address Word--
(MSB)
--DAC Data Word--
(LSB)
NC = Don't Care.
Reference Inputs
VREFHI: Upper DAC ladder reference voltage input. Allowable range is (V
DD
2.5 V) to (V
VREFLO
+2.5 V).
VREFLO: Lower DAC ladder reference voltage input, equal to zero scale output. Allowable range is V
SS
to
(V
VREFHI
2.5 V).
Analog Outputs
VOUTA through VOUTD: Four buffered DAC voltage outputs.
DIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TOP VIEW
(Not to Scale)
DAC8420
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
CLSEL
NC
CLK
SDI
GND
CLR
LD
CS
NC = NO CONNECT
SOL
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
DAC-8420
TOP VIEW
(Not to Scale)
DAC-8420
9
16
15
14
13
12
11
10
NC = NO CONNECT
VDD
VOUTD
VOUTC
VREFLO
VREFHI
VOUTB
VOUTA
VSS
CLSEL
NC
CLK
SDI
GND
CLR
LD
CS
TOP VIEW
(Not to Scale)
DAC8420
DAC8420
REV. 0
7
Table I. Control Function Logic Table
CLK
1
CS
1
LD
CLR
CLSEL
Serial Input Shift Register
DAC Registers A-D
NC
H
H
L
H
No Change
Loads Midscale Value (800
H
)
NC
H
H
L
L
No Change
Loads Zero-Scale Value (000
H
)
NC
H
H
H/L
No Change
Latches Value
L
H
H
NC
Shifts Register One Bit
No Change
L
H
H
NC
Shifts Register One Bit
No Change
H
NC (
)
H
NC
No Change
Loads the Serial Data Word
2
H
NC
L
H
NC
No Change
Transparent
3
NC
H
H
H
NC
No Change
No Change
NC = Don't Care.
NOTES
1
CS
and CLK are interchangeable.
2
Returning CS HIGH while CLK is HIGH avoids an additional "false clock" of serial input data. See Note 1.
3
Do not clock in serial data while LD is LOW.
OPERATION
Introduction
The DAC8420 is a quad, voltage-output 12-bit DAC with serial
digital input, capable of operating from a single +5 V supply.
The straightforward serial interface can be connected directly to
most popular microprocessors and microcontrollers, and can ac-
cept data at a 10 MHz clock rate when operating from
15 V
supplies. A unique voltage reference structure assures maximum
utilization of DAC output resolution by allowing the user to set
the zero- and full-scale output levels within the supply rails. The
analog voltage outputs are fully buffered, and are capable of
driving a 2 k
load. Output glitch impulse during major code
transitions is a very low 64 nV-s (typ).
Digital Interface Operation
The serial input of the DAC-8420, consisting of CS, SDI, and
LD
, is easily interfaced to a wide variety of microprocessor serial
ports. As shown in Table I and the Timing Diagram, while CS
is LOW the data presented to the input SDI is shifted into the
internal serial/parallel shift register on the rising edge of the
clock, with the address MSB first, data LSB last. The data for-
mat, shown above, is two bits of DAC address and two "don't
care" fill bits, followed by the 12-bit DAC data word. Once all
16 bits of the serial data word have been input, the load control
LD
is strobed and the word is parallel-shifted out onto the inter-
nal data bus. The two address bits are decoded and used to
route the 12-bit data word to the appropriate DAC data regis-
ter, see the Applications Information.
Correct Operation of CS and CLK
As mentioned in Table I, the control pins CLK and CS require
some attention during a data load cycle. Since these two inputs
are fed to the same logical "OR" gate, their operation is in fact
identical. The user must take care to operate them accordingly
in order to avoid clocking in false data bits. As shown in the
Timing Diagram, CLK must be either halted HIGH, or CS
brought HIGH during the last HIGH portion of the CLK fol-
lowing the rising edge which latched in the last data bit. Other-
wise, an additional rising edge is generated by CS rising while
CLK is LOW, causing CS to act as the clock and allowing a
false data bit into the serial input register. The same issue must
be considered in the beginning of the data load sequence also.
Using CLR and CLSEL
The CLEAR (CLR) control allows the user to perform an asyn-
chronous reset function. Asserting CLR loads all four DAC data
word registers, forcing the DAC outputs to either zero-scale
(000
H
) or midscale (800
H
), depending on the state of CLSEL as
shown in the Digital Function Table. The CLEAR function is
asynchronous and is totally independent of CS. When CLR
returns HIGH, the DAC outputs remain latched at the reset
value until LD is strobed, reloading the individual DAC data word
registers with either the data held in the serial input register prior
to the reset, or new data loaded through the serial interface.
Table II. DAC Address Word Decode Table
A1
A0
DAC Addressed
0
0
DAC A
0
1
DAC B
1
0
DAC C
1
1
DAC D
Programming the Analog Outputs
The unique differential reference structure of the DAC8420
allows the user to tailor the output voltage range precisely to the
needs of the application. Instead of spending DAC resolution
on an unused region near the positive or negative rail, the
DAC8420 allows the user to determine both the upper and
lower limits of the analog output voltage range. Thus, as shown
in Table III and Figure 1, the outputs of DACs A through D
range between VREFHI and VREFLO, within the limits speci-
fied in the Electrical Characteristics tables. Note also that
VREFHI must be greater than VREFLO.
1 LSB
FFF
H
000
H
2.5V MIN
2.5V MIN
0V MIN
V
DD
V
VREFHI
V
VREFLO
V
SS
10V MIN
Figure 1. Output Voltage Range Programming
DAC8420
REV. 0
8
Table III. Analog Output Code
DAC Data Word (HEX)
V
OUT
Note
FFF
VREFLO
+
(VREFHI VREFLO )
4096
4095
Full-Scale Output
801
VREFLO
+
(VREFHI VREFLO )
4096
2049
Midscale + 1
800
VREFLO
+
(VREFHI VREFLO )
4096
2048
Midscale
7FF
VREFLO
+
(VREFHI VREFLO )
4096
2047
Midscale 1
000
VREFLO
+
(VREFHI VREFLO )
4096
0
Zero Scale
Typical Performance Characteristics
0.3
0.3
14
0
0.2
4
0.1
6
0.2
0.1
12
10
8
6
4
2
0
2
V
VREFHI
V
INL LSB
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFLO
= 10V
Figure 4. INL vs. VREFHI (
15 V)
0.3
0.3
14
0
0.2
4
0.1
6
0.2
0.1
12
10
8
6
4
2
0
2
V
VREFHI
V
DNL LSB
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFLO
= 10V
Figure 2. Differential Linearity vs.
VREFHI (
15 V)
0.10
0.30
0.20
0.25
1.5
0.10
0.15
0.05
0
0.05
3.5
3.0
2.5
2.0
V
VREFHI
V
DNL LSB
T
A
= +25C
V
DD
= +5V, V
SS
= 0V
V
VREFLO
= 0V
Figure 3. Differential Linearity vs.
VREFHI (+5 V)
0.4
0.4
0.2
0.3
1.5
0
0.1
0.1
0.2
0.3
3.5
3.0
2.5
2.0
V
VREFHI
V
INL LSB
T
A
= +25C
V
DD
= +5V, V
SS
= 0V
V
VREFLO
= 0V
Figure 5. INL vs. VREFHI (+5 V)
0.7
0.5
1000
0.1
0.3
200
0.1
0
0.5
0.3
800
600
400
T = HOURS OF OPERATION AT +125
C
FULL-SCALE ERROR WITH R
L
= 2k LSB
x + 3
x
x 3
CURVES NOT NORMALIZED
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
Figure 6. Full-Scale Error vs.
Time Accelerated by Burn-In
1.2
0
1000
0.6
0.2
200
0.4
0
1.0
0.8
800
600
400
T = HOURS OF OPERATION AT +125
C
ZERO-SCALE ERROR WITH R
L
= 2k LSB
x + 3
x
x 3
CURVES NOT NORMALIZED
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
Figure 7. Zero-Scale Error vs.
Time Accelerated by Burn-In
DAC8420
REV. 0
9
0.2
0.6
125
0.4
0.5
50
75
0.2
0.3
0.1
0
0.1
100
75
50
25
0
25
TEMPERATURE
C
FULL-SCALE ERROR LSB
DAC A
DAC D
DAC C
DAC B
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
Figure 8. Full-Scale Error vs.
Temperature
1.2
0.4
125
0
0.2
50
75
0.4
0.2
0.6
0.8
1.0
100
75
50
25
0
25
TEMPERATURE
C
ZERO-SCALE ERROR LSB
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
DAC C
DAC B
DAC D
DAC A
Figure 9. Zero-Scale Error vs.
Temperature
0.9
0.9
4500
0.5
0.7
500
0
0.1
0.3
0.1
0.3
0.5
0.7
4000
3500
3000
2500
2000
1500
1000
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
DIGITAL INPUT CODE
ERROR LSB
Figure 10. Channel-to-Channel
Matching
15/
10
+1.5
1.0
+0.5
0.5
500
0
0
+1.0
4000
3500
3000
2500
2000
1500
1000
I
VREFHI
mA
DIGITAL INPUT CODE
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
Figure 14. I
VREFHI
vs. Code
6.5mV
3.5mV
+45.1s
4.9s
+5s/DIV
t
SETT
8s
1.22mV
0mV
1 LSB
CLR
T
A
= +25C
V
DD
= +5V, V
SS
= 5V
V
VREFHI
= +2.5V
V
VREFLO
= 2.5V
Figure 16. Settling Time ()(
5 V)
250V
10.25mV
45.1s
4.9s
5s/DIV
LD
t
SETT
8s
1.22mV
0mV
1 LSB
T
A
= +25C
V
DD
= +5V, V
SS
= 5V
V
VREFHI
= +2.5V
V
VREFLO
= 2.5V
Figure 15. Settling Time (+)(
5 V)
0.5
1.5
500
1.0
0
+1.0
0
+0.5
4000
3500
3000
2500
2000
1500
1000
+1.5
T
A
= +25C
V
DD
= +5V, V
SS
= 0V
V
VREFHI
= +2.5V
V
VREFLO
= 0V
DIGITAL INPUT CODE
ERROR LSB
4500
Figure 11. Channel-to-Channel
Matching +5/+2.5
+0.8
0.2
0.4
500
0
+0.1
0.1
0
+0.2
+0.3
+0.4
+0.6
+0.5
+0.7
3500 4000
3000
2500
2000
1500
1000
T
A
= +25, 55, 125C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
DIGITAL INPUT CODE
INL LSB
0.3
4500
Figure 13. INL vs. Code
15/
10
13
4
13
6
5
5
7
8
7
9
10
11
12
11
9
7
5
3
1
1
3
0
I
DD
mA
V
VREFHI
V
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFLO
= 10V
Figure 12. I
DD
vs. V
VREFHI
, All
DACs HIGH
DAC8420
REV. 0
10
+31.25mV
18.75mV
+90.2s
9.8s
+10s/DIV
t
SETT
13s
LD
0mV
4.88mV
1 LSB
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
Figure 17. Settling Time (+)(
15 V)
+43.75mV
6.25mV
+90.2s
9.8s
+10s/DIV
t
SETT
13s
4.88mV
0mV
1 LSB
CLR
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
Figure 18. Settling Time ()(
15 V)
+5V
5V
152.4s
47.6s
+1V
/DIV
0
20s/DIV
SR
RISE
= 1.65
SR
FALL
= 1.17
V
s
V
s
T
A
= +25C
V
DD
= +5V, V
SS
= 5V
V
VREFHI
= +2.5V
V
VREFLO
= 2.5V
Figure 19. Slew Rate (
5 V)
20
10
100
10M
1M
100k
10k
1k
10
0
+10
30
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= 0 100mV
V
VREFLO
= 10V
ALL BITS HIGH 200mV p-p
GAIN dB
FREQUENCY Hz
Figure 21. Small-Signal Response
+25V
25V
166.4s
33.6s
+5V
/DIV
0
20s/DIV
SR
RISE
= 1.9
V
s
SR
FALL
= 2.02
V
s
LD
CLR
T
A
= +25C
V
DD
= +15V, V
SS
= 15V
V
VREFHI
= +10V, V
VREFLO
= 10V
Figure 20. Slew Rate (
15 V)
100
10
50
0
100
1k
10k
100k
1M
60
70
80
90
10
20
30
40
T
A
= +25C
DATA = 000
H
V
DD
= +15V 1V, V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
PSRR dB
FREQUENCY Hz
Figure 22. PSRR vs. Frequency
6
6
150
0
4
2
75
4
2
75
0
TEMPERATURE C
POWER SUPPLY CURRENT mA
I
DD
I
SS
V
DD
= +15V
V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
ALL DACS HIGH (FULL SCALE)
Figure 23. Power Supply Current
vs. Temperature
10mA/DIV
VOUTA THROUGH VOUTD
T
A
= +25
C
V
DD
= +15V
V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
DATA = 800
H
5V/DIV
Figure 24. DAC Output Current vs.
VOUTX
10
100
10k
1k
10
8
0
6
4
2
LOAD RESISTANCE
V
OUT
PEAK V
T
A
= +25
C
V
DD
= +15V
V
SS
= 15V
V
VREFHI
= +10V
V
VREFLO
= 10V
DATA = FFF
H
OR 000
H
Figure 25. Output Swing vs.
Load Resistance
DAC8420
REV. 0
11
VREFHI Input Requirements
The DAC8420 utilizes a unique, patented DAC switch driver
circuit which compensates for different supply, reference volt-
age, and digital code inputs. This ensures that all DAC ladder
switches are always biased equally, ensuring excellent linearity
under all conditions. Thus, as indicated in the specifications,
the VREFHI input of the DAC8420 will require both sourcing
and sinking current capability from the reference voltage source.
Many positive voltage references are intended as current sources
only, and offer little sinking capability. The user should consider
references such as the AD584, AD586, AD587, AD588, AD780,
and REF43 in this application.
APPLICATIONS
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The DAC8420 has a single ground pin
that is internally connected to the digital section as the logic
reference level. The first thought may be to connect this pin to
the digital ground; however, in large systems the digital ground
is often noisy because of the switching currents of other digital
circuitry. Any noise that is introduced at the ground pin could
couple into the analog output. Thus, to avoid error causing
digital noise in the sensitive analog circuitry, the ground pin
should be connected to the system analog ground. The ground
path (circuit board trace) should be as wide as possible to re-
duce any effects of parasitic inductance and ohmic drops. A
ground plane is recommended if possible. The noise immunity
of the onboard digital circuitry, typically in the hundreds of mil-
livolts, is well able to reject the common-mode noise typically
seen between system analog and digital grounds. Finally, the
analog and digital ground should be connected together at a
single point in the system to provide a common reference.
This is preferably done at the power supply.
Good grounding practice is essential to maintaining analog
performance in the surrounding analog support circuitry as well.
With two reference inputs, and four analog outputs capable of
moderate bandwidth and output current, there is a significant
potential for ground loops. Again, a ground plane is recom-
mended as the most effective solution to minimizing errors due
to noise and ground offsets.
1
8
9
VDD
VSS
GND
0.1F
10F
V
S
0.1F
10F
+V
S
10F = TANTALUM
0.1F = CERAMIC
Figure 26. Recommended Supply Bypassing Scheme
The DAC8420 should have ample supply bypassing, located as
close to the package as possible. Figure 26 shows the recom-
mended capacitor values of 10
F in parallel with 0.1
F. The
0.1
F cap should have low "Effective Series Resistance" (ESR)
and "Effective Series Inductance" (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching. In order to preserve the specified analog perfor-
mance of the device, the supply should be as noise free as pos-
sible. In the case of 5 V only systems it is desirable to use the
same 5 V supply for both the analog circuitry and the digital
portion of the circuit. Unfortunately, the typical 5 V supply is
extremely noisy due to the fast edge rates of the popular CMOS
logic families which induce large inductive voltage spikes, and
busy microcontroller or microprocessor busses which commonly
have large current spikes during bus activity. However, by prop-
erly filtering the supply as shown in Figure 27, the digital 5 V
supply can be used. The inductors and capacitors generate a fil-
ter that not only rejects noise due to the digital circuitry, but
also filters out the lower frequency noise of switch mode power
supplies. The analog supply should be connected as close as
possible to the origin of the digital supply to minimize noise
pickup from the digital section.
100F
ELECT.
1022F
TANT.
0.1F
CER.
TTL/CMOS
LOGIC
CIRCUITS
+5V
POWER SUPPLY
+5V
+5V
RETURN
FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301
Figure 27. Single-Supply Analog Supply Filter
Analog Outputs
The DAC8420 features buffered analog voltage outputs capable
of sourcing and sinking up to 5 mA when operating from
15 V
supplies, eliminating the need for external buffer amplifiers in
most applications while maintaining specified accuracy over the
rated operating conditions. The buffered outputs are simply an
op amp connected as a voltage follower, and thus have output
characteristics very similar to the typical operational amplifier.
These amplifiers are short-circuit protected. The designer
should verify that the output load meets the capabilities of the
device, in terms of both output current and load capacitance.
The DAC8420 is stable with capacitive loads up to 2 nF typical.
However, any capacitive load will increase the settling time, and
should be minimized if speed is a concern.
The output stage includes a p-channel MOSFET to pull the
output voltage down to the negative supply. This is very impor-
tant in single supply systems, where VREFLO usually has the
same potential as the negative supply. With no load, the
zero-scale output voltage in these applications will be less than
500
V typically, or less than 1 LSB when V
VREFHI
= 2.5 V.
However, when sinking current this voltage does increase
because of the finite impedance of the output stage. The effec-
tive value of the pull-down resistor in the output stage is
typically 320
. With a 100 k
resistor connected to +5 V, the
resulting zero-scale output voltage is 16 mV. Thus, the best
DAC8420
REV. 0
12
single supply operation is obtained with the output load
connected to ground, so the output stage does not have to sink
current.
Like all amplifiers, the DAC8420 output buffers do generate
voltage noise, 52 nV/
Hz
typically. This is easily reduced by
adding a simple RC low-pass filter on each output.
Reference Configuration
The two reference inputs of the DAC8420 allow a great deal of
flexibility in circuit design. The user must take care, however, to
observe the minimum voltage input levels on VREFHI and
VREFLO to maintain the accuracy shown in the data sheet.
These input voltages can be set anywhere across a wide range
within the supplies, but must be a minimum of 2.5 V apart in
any case. See Figure 1. A wide output voltage range can be
obtained with
5 V references, which can be provided by the
AD588 as shown in Figure 28. Many applications utilize the
DACs to synthesize symmetric bipolar wave forms, which
requires an accurate, low drift bipolar reference. The AD588
provides both voltages and needs no external components. Ad-
ditionally, the part is trimmed in production for 12-bit accuracy
over the full temperature range without user calibration. Per-
forming a Clear with the reset select CLSEL HIGH allows the
user to easily reset the DAC outputs to midscale, or zero volts in
these applications.
When driving the reference inputs VREFHI and VREFLO, it is
important to note that VREFHI both sinks and sources current,
and that the input currents of both are code dependent. Many
voltage reference products have limited current sinking capabil-
ity and must be buffered with an amplifier to drive VREFHI, in
order to maintain overall system accuracy. The input VREFLO,
however, has no such requirement.
15V SUPPLY
DAC-8420
DIGITAL
CONTROL
4
9
15 16
14
12
11
10
8
2
3
6
7
1
5
DAC A
DAC B
DAC C
DAC D
VOUTA
VOUTB
VOUTC
VOUTD
DIGITAL INPUTS
GND
VREFLO
5V
0.1F
0.1F
+15V SUPPLY
+5V
VREFHI
7
R5
R4
R6
6
R
B
R1
R2
R3
A2
A1
A3
A4
7
6
4
3
1
14
15
11
8
12
9
5
13
2
16
0.1F
0.1F
SYSTEM
GROUND
AD588
15V
SUPPLY
+15V
SUPPLY
+5V
5V
1F
10
+V
S
V
S
Figure 28.
10 V Bipolar Reference Configuration Using the AD588
DAC8420
REV. 0
13
For a single 5 V supply, V
VREFHI
is limited to at most 2.5 V, and
must always be at least 2.5 V less than the positive supply to
ensure linearity of the device. For these applications, the REF43
is an excellent low drift 2.5 V reference that consumes only
450
A (max). It works well with the DAC8420 in a single 5 V
system as shown in Figure 29.
DAC-8420
DIGITAL
CONTROL
4
9
15 16
14
12
11
10
8
2
3
6
7
1
5
DAC A
DAC B
DAC C
DAC D
VOUTA
VOUTB
VOUTC
VOUTD
DIGITAL INPUTS
GND
VREFLO
0.1F
+5V SUPPLY
VREFHI
REF-43
VOUT
GND
VIN
+5V SUPPLY
2.5V
0.1F
6
2
4
Figure 29. +5 V Single Supply Operation Using REF43
Isolated Digital Interface
Because the DAC8420 is ideal for generating accurate voltages
in process control and industrial applications, due to noise,
safety requirements, or distance, it may be necessary to isolate it
from the central controller. This can be easily achieved by using
opto-isolators, which are commonly used to provide electrical
isolation in excess of 3 kV. Figure 30 shows a simple 3-wire
interface scheme to control the clock, data, and load pulse. For
normal operation, CS is tied permanently LOW so that the
DAC8420 is always selected. The resistor and capacitor on the
CLR
pin provide a power-on reset with 10 ms time constant. The
three opto-isolators are used for the SDI, CLK, and LD lines.
One opto-isolated line (LD) can be eliminated from this circuit
by adding an inexpensive 4-bit TTL Counter to generate the
Load pulse for the DAC8420 after 16 clock cycles. The counter
is used to count of the number of clock cycles loading serial data
to the DAC8420. After all 16 bits have been clocked into the
converter, the counter resets, and a load pulse is generated on
clock 17. In either circuit, the DAC8420's serial interface pro-
vides a simple, low cost method of isolating the digital control.
10k
10k
+5V
10k
LD
SCLK
SDI
+5V
REG
+5V
POWER
HIGH VOLTAGE
ISOLATION
+5V
+5V
0.1F
+5V
CLR
CLSEL
CLK
SDI
LD
CS
4
5
VREFHI
VREFLO VSS GND
1F
10k
DAC-8420
VOUTA
VOUTB
VOUTC
VOUTD
REF-43
VOUT
GND
VIN
+5V
6
2
4
2.5V
9
8
1
6
7
3
2
11
10
14
16
15
12
VDD
Figure 30. Opto-lsolated 3-Wire Interface
Dual Window Comparator
Often a comparator is needed to signal an out-of-range warning.
Combining the DAC8420 with a quad comparator such as the
CMP04 provides a simple dual window comparator with adjust-
able trip points as shown in Figure 31. This circuit can be
operated with either a dual or a single supply. For the A input
channel, DAC B sets the low trip point and DAC A sets the up-
per trip point. The CMP04 has open-collector outputs that are
connected together in "Wired-OR" configuration to generate an
out-of-range signal. For example, when VINA goes below the
trip point set by DAC B, comparator C2 pulls the output down,
turning the red LED on. The output can also be used as a logic
signal for further processing.
DAC8420
REV. 0
14
DAC-8420
DIGITAL
CONTROL
4
9
15
16
14
12
11
10
8
2
3
6
7
1
5
DAC A
DAC B
DAC C
DAC D
VOUTA
VOUTB
VOUTC
VOUTD
DIGITAL INPUTS
GND
VREFLO
0.1F
+5V SUPPLY
VREFHI
VSS
5
4
6
9
8
11
10
2
1
14
3
12
CMP-04
13
0.1F
+5V
+5V
604
+5V
RED LED
604
OUT
A
OUT B
VINA
VINB
RED LED
REF-43
V
OUT
GND
VIN
+5V SUPPLY
2.5V
0.1F
6
2
4
7
C1
C2
C3
C4
Figure 31. Dual Programmable Window Comparator
MC68HC11 Microcontroller Interfacing
Figure 32 shows a serial interface between the DAC8420 and
the MC68HC11 8-bit microcontroller. The SCK output of the
68HC11 drives the CLK input of the DAC, and the MOSI port
outputs the serial data to load into the SDI input of the DAC.
The port lines PD5, PC0, PC1, and PC2 provide the controls to
the DAC as shown.
PC2
PC1
PC0
(PD5) SS
SCK
MOSI
MC68HC11*
CLSEL
CLR
CS
LD
CLK
SDI
DAC-8420*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 32. MC68HC11 Microcontroller Interface
For correct operation, the 68HC11 should be configured such
that its CPOL bit and CPHA bit are both set to 1. In this con-
figuration, serial data on MOSI of the 68HC11 is valid on the
rising edge of the clock, which is the required timing for the
DAC8420 Data is transmitted in 8-bit bytes (MSB first), with
only eight rising clock edges occurring in the transmit cycle. To
load data to the DAC8420's input register, PC0 is taken low
and held low during the entire loading cycle. The first 8 bits are
shifted in address first, immediately followed by another 8 bits
in the second least-significant byte to load the complete 16-bit
word. At the end of the second byte load, PC0 is then taken
high. To prevent an additional advancing of the internal shift
register, SCK must already be asserted before PC0 is taken
high. To transfer the contents of the input shift register to the
DAC register, PD5 is then taken low, asserting the LD input of
the DAC and completing the loading process. PD5 should re-
turn high before the next load cycle begins. The DAC8420's
CLR
input, controlled by the output PC1, provides an asyn-
chronous clear function.
DAC8420
REV. 0
15
DAC8420 to M68HC11 Interface Assembly Program
*
M68HC11 Register Definitions
PORTC EQU $1003 Port C control register
*
"0,0,0,0;0,CLSEL,CLR,CS"
DDRC EQU $1007 Port C data direction
PORTD EQU $1008 Port D data register
*
"0,0,LD,SCLK;SDI,0,0,0"
DDRD EQU $1009 Port D data direction
SPCR EQU $1028 SPI control register
*
"SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0"
SPSR EQU $1029 SPI status register
*
"SPIF,WCOL,0,MODF;0,0,0,0"
SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables: SDI1 is encoded from 0 (Hex) to CF (Hex)
* To select: DAC A Set SDI1 to $0X
DAC B Set SDI1 to $4X
DAC C Set SDI1 to $8X
DAC D Set SDI1 to $CX
SDI2 is encoded from 00 (Hex) to FF (Hex)
*
DAC requires two 8-bit loads Address + 12 bits
SDI1 EQU $00 SDI packed byte 1 "A1,A0,0,0;MSB,DB10,DB9,DB8"
SDI2 EQU $01 SDI packed byte 2
"DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0"
* Main Program
ORG $C000 Start of user's RAM in EVB
INIT LDS #$CFFF Top of C page RAM
* Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
*
CLSEL-Hi, CLR-Hi, CS-Hi
*
To reset DAC to ZERO-SCALE, set CLSEL-Lo ($03)
*
To reset DAC to MID-SCALE, set CLSEL-Hi ($07)
STAA PORTC Initialize Port C Outputs
LDAA #$07 0,0,0,0;0,1,1,1
STAA DDRC CLSEL, CLR, and CS are now enabled as outputs
* Initialize Port D Outputs
LDAA #$30 0,0,1,1;0,0,0,0
*
LD
-Hi,SCLK-Hi,SDI-Lo
STAA PORTD Initialize Port D Outputs
LDAA #$38 0,0,1,1;1,0,0,0
STAA DDRD LD,SCLK, and SDI are now enabled as outputs
* Initialize SPI Interface
LDAA #$5F
STAA SPCR SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32
* Call update subroutine
BSR UPDATE Xfer 2 8-bit words to DAC-8420
JMP $E000 Restart BUFFALO
* Subroutine UPDATE
UPDATE PSHX
Save registers X, Y, and A
PSHY
PSHA
* Enter Contents of SDI1 Data Register (DAC# and 4 MSBs)
LDAA #$80 1,0,0,0;0,0,0,0
STAA SDI1 SDI1 is set to 80 (Hex)
* Enter Contents of SDI2 Data Register
LDAA #$00 0,0,0,0;0,0,0,0
STAA SDI2 SDI2 is set to 00 (Hex)
LDX #SDI1 Stack pointer at 1st byte to send via SDI
LDY #$1000 Stack pointer at on-chip registers
* Clear DAC output to zero
BCLR PORTC,Y $02 Assert CLR
BSET PORTC,Y $02 Deassert CLR
* Get DAC ready for data input
BCLR PORTC,Y $01 Assert CS
TFRLP LDAA 0,X Get a byte to transfer via SPI
STAA SPDR Write SDI data reg to start xfer
WAIT LDAA SPSR Loop to wait for SPIF
BPL WAIT SPIF is the MSB of SPSR
* (when SPIF is set, SPSR is negated)
INX
Increment counter to next byte for xfer
CPX #SDI2+ 1 Are we done yet ?
BNE TFRLP If not, xfer the second byte
* Update DAC output with contents of DAC register
BCLR PORTD,Y 520 Assert LD
BSET PORTD,Y $20 Latch DAC register
BSET PORTC,Y $01 De-assert CS
PULA When done, restore registers X, Y & A
PULY
PULX
RTS
** Return to Main Program **
DAC8420
REV. 0
16
C1836189/93
PRINTED IN U.S.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Epoxy DIP
(P Suffix)
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
PIN 1
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.840 (21.33)
0.745 (18.93)
9
16
1
8
16-Pin Wide-Body SOL
(SOL)
PIN 1
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
16
9
8
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
x 45
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.4133 (10.50)
0.3977 (10.00)
0.0118 (0.30)
0.0040 (0.10)
16-Pin Cerdip
(Q Suffix)
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
0
0.005 (0.13) MIN
PIN 1
0.080 (2.03) MAX
0.310 (7.87)
0.220 (5.59)
1
8
9
0.840 (21.34) MAX
0.200
(5.08)
MAX
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
SEATING
PLANE
16
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