REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

+5 V, Serial Input

Complete 12-Bit DAC

DAC8512

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

World Wide Web Site: http://www.analog.com

Fax: 617/326-8703

© Analog Devices, Inc., 1996

FUNCTIONAL BLOCK DIAGRAM

REF

12-BIT DAC

DAC REGISTER

OUT

GND

SERIAL REGISTER

CLR

CLK

SDI

FEATURES
Space Saving SO-8 or Mini-DIP Packages
Complete, Voltage Output with Internal Reference
1 mV/Bit with 4.095 V Full Scale
Single +5 Volt Operation
No External Components
3-Wire Serial Data Interface, 20 MHz Data Loading Rate
Low Power: 2.5 mW

APPLICATIONS
Portable Instrumentation
Digitally Controlled Calibration
Servo Controls
Process Control Equipment
PC Peripherals

GENERAL DESCRIPTION

The DAC8512 is a complete serial input, 12-bit, voltage output
digital-to-analog converter designed to operate from a single
+5 V supply. It contains the DAC, input shift register and
latches, reference and a rail-to-rail output amplifier. Built using
a CBCMOS process, these monolithic DACs offer the user low
cost, and ease of use in +5 V only systems.

Coding for the DAC8512 is natural binary with the MSB loaded
first. The output op amp can swing to either rail and is set to a
range of 0 V to +4.095 V--for a one-millivolt-per-bit resolution.
It is capable of sinking and sourcing 5 mA. An on-chip reference
is laser trimmed to provide an accurate full-scale output voltage
of 4.095 V.

Serial interface is high speed, three-wire, DSP compatible with
data in (SDI), clock (CLK) and load strobe (LD). There is also
a chip-select pin for connecting multiple DACs.

A CLR input sets the output to zero scale at power on or upon
user demand.

The DAC8512 is specified over the extended industrial (40

to +85

C) temperature range. DAC8512s are available in plas-

tic DIPs and SO-8 surface mount packages.

1.0

4096

0.5

0.75

0.25

0.5

0.75

3072

2048

1024

DIGITAL INPUT CODE Decimal

LINEARITY ERROR LSB

Linearity Error vs. Digital Input Code

REV. A

DAC8512SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Condition

Min

Typ

Max

Units

STATIC PERFORMANCE

Resolution

Note 2

Bits

Relative Accuracy

INL

E Grade

1/4

LSB

F Grade

3/4

LSB

Differential Nonlinearity

DNL

No Missing Codes

3/4

LSB

Zero-Scale Error

ZSE

Data = 000

+1/2

LSB

Full-Scale Voltage

Data = FFF

E Grade

4.087

4.095

4.103

F Grade

4.079

4.095

4.111

Full-Scale Tempco

TCV

Notes 3, 4

ppm/

ANALOG OUTPUT

Output Current

OUT

Data = 800

Load Regulation at Full Scale

REG

= 402

, Data = 800

LSB

Capacitive Load

No Oscillation

500

LOGIC INPUTS

Logic Input Low Voltage

0.8

Logic Input High Voltage

2.4

Input Leakage Current

Input Capacitance

INTERFACE TIMING SPECIFICATIONS

1, 4

Clock Width High

Clock Width Low

Load Pulse Width

LDW

Data Setup

Data Hold

Clear Pulse Width

CLRW

Load Setup

LD1

Load Hold

LD2

Select

CSS

Deselect

CSH

AC CHARACTERISTICS

Voltage Output Settling Time

1 LSB of Final Value

DAC Glitch

nV s

Digital Feedthrough

nV s

SUPPLY CHARACTERISTICS

Positive Supply Current

= 2.4 V, V

= 0.8 V, No Load

1.5

2.5

= 5 V, V

= 0 V, No Load

0.5

Power Dissipation

DISS

= 2.4 V, V

= 0.8 V, No Load

7.5

12.5

= 5 V, V

= 0 V, No Load

2.5

Power Supply Sensitivity

PSS

0.002

0.004

%/%

NOTES

All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

1 LSB = 1 mV for 0 V to +4.095 V output range.

Includes internal voltage reference error.

These parameters are guaranteed by design and not subject to production testing.

The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in

this 6 LSB region.

Specifications subject to change without notice.

(@ V

= +5.0 V 5%, 40 C

+85 C, unless otherwise noted)

REV. A

DAC8512

WAFER TEST LIMITS

(@ V

= +5.0 V 5%, T

= +25 C, applies to part number DAC8512GBC only, unless otherwise noted)

Parameter

Symbol

Condition

Min

Typ

Max

Units

STATIC PERFORMANCE

Relative Accuracy

INL

3/4

LSB

Differential Nonlinearity

DNL

No Missing Codes

0.7

LSB

Zero-Scale Error

ZSE

Data = 000

+1/2

LSB

Full-Scale Voltage

Data = FFF

4.085

4.095

4.105

LOGIC INPUTS

Logic Input Low Voltage

0.8

Logic Input High Voltage

2.4

Input Leakage Current

SUPPLY CHARACTERISTICS

Positive Supply Current

= 2.4 V, V

= 0.8 V, No Load

1.5

2.5

= 5 V, V

= 0 V, No Load

0.5

Power Dissipation

DISS

= 2.4 V, V

= 0.8 V, No Load

7.5

12.5

= 5 V, V

= 0 V, No Load

2.5

Power Supply Sensitivity

PSS

0.002

0.004

%/%

NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS*

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V, +10 V

Logic Inputs to GND . . . . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

OUT

to GND . . . . . . . . . . . . . . . . . . . . . 0.3 V, V

+ 0.3 V

OUT

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package Power Dissipation . . . . . . . . . . . . . . (T

max T

Thermal Resistance

8-Pin Plastic DIP Package (P) . . . . . . . . . . . . . . . . 103

C/W

8-Lead SOIC Package (S) . . . . . . . . . . . . . . . . . . . 158

C/W

Maximum Junction Temperature (T

max) . . . . . . . . . +150

Operating Temperature Range . . . . . . . . . . . . . 40

C to +85

Storage Temperature Range . . . . . . . . . . . . . 65

C to +150

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300

*Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability .

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the DAC8512 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

INL

Temperature

Package

Model

(LSB) Range

Description

Option

DAC8512EP

C to +85

C 8-Pin P-DIP

N-8

DAC8512FP

C to +85

C 8-Pin P-DIP

N-8

DAC8512FS

C to +85

C 8-Lead SOIC SO-8

DAC8512GBC

+25

Dice

DAC8512

REV. A

CLR

csh

D11

D10

ld2

css

ld1

ldw

clrw

1 LSB

ERROR BAND

SDI

CLK

SDI

CLK

OUT

Figure 1. Timing Diagram

DATA

SHIFT

REGISTER

ESD PROTECTION DIODES TO V

AND GND

SDI

CLK

Figure 2. Equivalent Clock Input Logic

Table I. Control-Logic Truth Table

CLK

CLR

Serial Shift Register Function

DAC Register Function

No Effect

Latched

No Effect

Latched

No Effect

Latched

Shift-Register-Data Advanced One Bit

Latched

Shift-Register-Data Advanced One Bit

Latched

No Effect

Updated with Current Shift Register Contents

No Effect

Transparent

No Effect

Loaded with All Zeros

No Effect

Latched All Zeros

NOTES

+ positive logic transition;

negative logic transition; X = Don't Care.

and CLK are interchangeable.

Returning CS HIGH avoids an additional "false clock" of serial data input.

Do not clock in serial data while LD is LOW.

DAC8512

REV. A

PIN CONFIGURATIONS

SO-8

P-DIP-8 & Cerdip-8

TOP VIEW

(Not to Scale)

DAC8512

TOP VIEW

(Not to Scale)

DAC8512

OUT

GND

CLR

CLK

SDI

OUT

GND

CLR

CLK

SDI

PIN DESCRIPTIONS

Pin

Name

Description

Positive Supply. Nominal value +5 V,

5%.

Chip Select. Active low input.

CLK

Clock input for the internal serial input shift register.

SDI

Serial Data Input. Data on this pin is clocked into the
internal serial register on positive clock edges of the
CLK pin. The Most Significant Bit (MSB) is loaded
first.

Active low input which writes the serial register data
into the DAC register. Asynchronous input.

CLR

Active low digital input that clears the DAC register to
zero, setting the DAC to minimum scale. Asynchronous
input.

GND Analog ground for the DAC. This also serves as the

digital logic ground reference voltage.

OUT

Voltage output from the DAC. Fixed output voltage
range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed
full-scale voltage independent of time, temperature and
power supply variations.

DICE CHARACTERISTICS

SUBSTRATE IS COMMON WITH V

NUMBER OF TRANSISTORS : 642
DIE SIZE: 0.055 inch

0.106 inch; 5830 sq mils

CLK

SDI

CLR

GND

OUT

OPERATION

The DAC8512 is a complete ready to use 12-bit digital-to-analog
converter. It contains a voltage-switched, 12-bit, laser-trimmed
DAC, a curvature-corrected bandgap reference, a rail-to-rail
output op amp, a DAC register, and a serial data input register.
The serial data interface consists of a CLK, serial data in (SDI),
and a load strobe (LD). This basic 3-wire interface offers maxi-
mum flexibility for interface to the widest variety of serial data
input loading requirements. In addition a CS select is provided
for multiple packaging loading and a power on reset CLR pin to
simplify start or periodic resets.

D/A CONVERTER SECTION

The DAC is a 12-bit voltage mode device with an output that
swings from GND potential to the 2.5 volt internal bandgap
voltage. It uses a laser trimmed R-2R ladder which is switched
by N channel MOSFETs. The output voltage of the DAC has a
constant resistance independent of digital input code. The DAC
output is internally connected to the rail-to-rail output op amp.

AMPLIFIER SECTION

The DAC's output is buffered by a low power consumption pre-
cision amplifier. This amplifier contains a differential PNP pair
input stage which provides low offset voltage and low noise, as
well as the ability to amplify the zero-scale DAC output volt-
ages. The rail-to-rail amplifier is configured in a gain of 1.6384
(= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output
(1 mV/LSB). See Figure 3 for an equivalent circuit schematic of
the analog section.

OUT

RAIL-TO-RAIL
OUTPUT
AMPLIFIER

BANDGAP

REFERENCE

SPDT

N-CH FET

SWITCHES

AV = 4.095/2.5
= 1.638V/V

VOLTAGE SWITCHED 12-BIT
R-2R D/A CONVERTER

BUFFER

2.5V

Figure 3. Equivalent DAC8512 Schematic of Analog
Portion

The op amp has a 16

s typical settling time to 0.01%. There

are slight differences in settling time for negative slowing signals
vs. positive. See the oscilloscope photos in the typical perfor-
mances section of this data sheet.

DAC8512

REV. A

OUTPUT SECTION

The rail-to-rail output stage of this amplifier has been designed
to provide precision performance while operating near either
power supply.

OUT

AGND

N-CH

P-CH

Figure 4. Equivalent Analog Output Circuit

Figure 4 shows an equivalent output schematic of the rail-to-rail
amplifier with its N channel pull down FETs that will pull an
output load directly to GND. The output sourcing current is
provided by a P channel pull up device that can supply GND
terminated loads, especially at the low supply tolerance values of
4.75 volts. Figures 5 and 6 provide information on output swing
performance near ground and full-scale as a function of load. In
addition to resistive load driving capability the amplifier has also
been carefully designed and characterized for up to 500 pF ca-
pacitive load driving capability.

POWER SUPPLY

The very low power consumption of the DAC8512 is a direct
result of a circuit design optimizing use of the CBCMOS pro-
cess. By using the low power characteristics of the CMOS for
the logic, and the low noise, tight matching of the complemen-
tary bipolar transistors good analog accuracy is achieved.

For power consumption sensitive applications it is important to
note that the internal power consumption of the DAC8512 is
strongly dependent on the actual logic input voltage levels
present on the SDI, CS, LD, and CLR pins. Since these inputs
are standard CMOS logic structures they contribute static
power dissipation dependent on the actual driving logic V

and

voltage levels. The graph in Figure 9 shows the effect on to-

tal DAC8512 supply current as a function of the actual value of
input logic voltage. Consequently use of CMOS logic vs. TTL
minimizes power dissipation in the static state. A V

= 0 V on

the SDI, CS and CLR pins provides the lowest standby power
dissipation of 2.5 mW (500

5 V).

As with any analog system, it is recommended that the DAC8512
power supply be bypassed on the same PC card that contains the
chip. Figure 10 shows the power supply rejection versus frequen-
cy performance. This should be taken into account when using
higher frequency switched mode power supplies with ripple fre-
quencies of 100 kHz and higher.

One advantage of the rail-to-rail output amplifier used in the
DAC8512 is the wide range of usable supply voltage. The part
is fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current ca-
pability near full scale can be tolerated, operation of the DAC8512
is possible down to +4.3 volts. The minimum operating supply
voltage versus load current plot, in Figure 11, provides informa-
tion for operation below V

= +4.75 V.

TIMING AND CONTROL

The DAC8512 has a separate serial input register from the
12-bit DAC register that allows preloading of a new data value
into the serial register without disturbing the present DAC out-
put voltage. After the new value is fully loaded in the serial in-
put register it can be asynchronously transferred to the DAC
register by strobing the LD pin. The DAC register uses a level
sensitive LD strobe that should be returned high before any
new data is loaded into the serial input register. At any time the
contents of the DAC register can be reset to zero by strobing
the CLR pin which causes the DAC output voltage to go to
zero volts. All of the timing requirements are detailed in Figure
1 along with the Table I Control-Logic Truth Table.

REV. A

Typical Performance Characteristics -- DAC8512

100

100k

10k

LOAD RESISTANCE 

OUTPUT VOLTAGE Volts

RL TIED TO AGND
D = FFFH

TIED TO AGND

DATA = FFF

= +5V

= +25 C

TIED TO +5V

DATA = 000H

Figure 5. Output Swing vs. Load

TIME = 2ms/DIV

OUTPUT NOISE VOLTAGE 500

V/DIV

100

SCALE = 100X

CODE = FFF

= 4095

BW = 630kHz

= +25 C

2mS

50mV

Figure 8. Broadband Noise

0.01

0.1

1.0

5.0

4.8

4.0

4.6

4.4

4.2

0.04

0.4

4.0

OUTPUT LOAD CURRENT mA

MIN Volts

VFS

1 LSB

DATA = FFF

= +25 C

PROPER OPERATION
WHEN V

SUPPLY

VOLTAGE ABOVE
CURVE

Figure 11. Minimum Supply Voltage
vs. Load

1000

100

0.01

0.1

OUTPUT SINK CURRENT A

OUTPUT PULL-DOWN VOLTAGE mV

= +5V

DATA = 000

= +85 C

= 40 C

= +25 C

Figure 6. Pull-Down Voltage vs. Out-
put Sink Current Capability

4.0

0.0

0.8

2.4

1.6

3.2

LOGIC VOLTAGE VALUE Volts

SUPPLY CURRENT mA

= +5V

= +25 C

NO LOAD

Figure 9. Supply Current vs. Logic
Input Voltage

2.028

2.018

2.048

2.038

TIME 200ns/DIV

OUT

 Volts

2048

TO 2047

= 5V

= +25 C

Figure 12. Midscale DAC Glitch
Performance

100

60

80

20

40

OUTPUT VOLTAGE Volts

OUTPUT CURRENT mA

POS

CURRENT

LIMIT

NEG
CURRENT
LIMIT

DATA = 800

TIED TO +2V

Figure 7. Short Circuit Current

100

100k

10k

POWER SUPPLY REJECTION dB

FREQUENCY Hz

= +5V 200mV AC

= +25 C

DATA = FFF

Figure 10. Power Supply Rejection
vs. Frequency

100

TIME = 20

s/DIV

= NO LOAD

= 110pF

= +25 C

1V/DIV

Figure 13. Large Signal Settling Time

DAC8512 -- Typical Performance Characteristics

REV. A

= +5V

= +25 C

= NO LOAD

OUTPUT VOLTAGE

1mV/DIV

TIME 10

s/DIV

Figure 15. Fall Time Detail

4.115

4.075

125

4.085

4.080

25

50

4.095

4.090

4.100

4.105

4.110

100

TEMPERATURE C

FULL-SCALE OUTPUT Volts

= +5V

NO LOAD
SS = 300 PCS

AVG 3

AVG + 3

AVG

Figure 18. Full-Scale Voltage vs.
Temperature

1200

200

1000

600

800

400

OUTPUT VOLTAGE CHANGE mV

HOURS OF OPERATION AT +125 C

135 UNITS TESTED

READINGS NORMALIZED
TO ZERO HOUR TIME POINT

AVERAGE

RANGE

Figure 21. Long Term Drift Acceler-
ated by Burn-In

= +5V

= +25 C

= NO LOAD

OUTPUT VOLTAGE

1mV/DIV

TIME 10

s/DIV

Figure 14. Rise Time Detail

TOTAL UNADJUSTED ERROR mV

NUMBER OF UNITS

12

+12

TUE =

INL + ZS + FS

SS = 300 UNITS

TA = +25 C

Figure 17. Total Unadjusted Error
Histogram

0.1

0.01

100

100k

10k

FREQUENCY Hz

= +5V

= +25 C

DATA = FFF

OUTPUT NOISE DENSITY 

Figure 20. Output Voltage Noise vs.
Frequency

2.0

4096

1.0

1.5

512

0.0

0.5

1.0

1.5

3584

3072

2560

2048

1536

1024

DIGITAL INPUT CODE Decimal

LINEARITY ERROR LSB

= +5V

= 40 C, +25 C, +85 C

+25 C & +85 C

40 C

Figure 16. Linearity Error vs. Digital
Code

125

25

50

100

TEMPERATURE C

ZERO-SCALE mV

DATA = 000

NO LOAD
V

= +5.0V

Figure 19. Zero-Scale Voltage vs.
Temperature

125

25

50

100

0
TEMPERATURE C

SUPPLY CURRENT mA

LOGIC

= 2.4V

DATA = FFF

NO LOAD

= +4.75V

= +5.25V

= +5.0V

Figure 22. Supply Current vs.
Temperature

DAC8512

REV. A

APPLICATIONS SECTION

Power Supplies, Bypassing, and Grounding

All precision converter products require careful application of
good grounding practices to maintain full rated performance.
Because the DAC8512 has been designed for +5 V applications,
it is ideal for those applications under microprocessor or micro-
computer control. In these applications, digital noise is preva-
lent; therefore, special care must be taken to assure that its
inherent precision is maintained. This means that particularly
good engineering judgment should be exercised when address-
ing the power supply, grounding, and bypassing issues using the
DAC8512.

The power supply used for the DAC8512 should be well filtered
and regulated. The device has been completely characterized for
a +5 V supply with a tolerance of

5%. Since a +5 V logic sup-

ply is almost universally available, it is not recommended to
connect the DAC directly to an unfiltered logic supply without
careful filtering. Because it is convenient, a designer might be
inclined to tap a logic circuit's supply for the DAC's supply.
Unfortunately, this is not wise because fast logic with nanosec-
ond transition edges induce high current pulses. The high tran-
sient current pulses can generate glitches hundreds of millivolts
in amplitude due to wiring resistances and inductances. This
high frequency noise will corrupt the analog circuits internal to
the DAC and cause errors. Even though their spike noise is
lower in amplitude, directly tapping the output of a +5 V system
supply can cause errors because these supplies are of the switch-
ing regulator type that can and do generate a great deal of high
frequency noise. Therefore, the DAC and any associated analog
circuitry should be powered directly from the system power sup-
ply outputs using appropriate filtering. Figure 23 illustrates how
a clean, analog-grade supply can be generated from a +5 V logic
supply using a differential LC filter with separate power supply
and return lines. With the values shown, this filter can easily
handle 100 mA of load current without saturating the ferrite
cores. Higher current capacity can be achieved with larger ferrite
cores. For lowest noise, all electrolytic capacitors should be low
ESR (Equivalent Series Resistance) type.

100

ELECT
.

10-22

TANT.

0.1

CER.

TTL/CMOS

LOGIC

CIRCUITS

+5V

POWER SUPPLY

+5V

RETURN

FERRITE BEADS:
2 TURNS, FAIR-RITE
#2677006301

Figure 23. Properly Filtering a +5 V Logic Supply Can Yield
a High Quality Analog Supply

In order to fit the DAC8512 in an 8-pin package, it was neces-
sary to use only one ground connection to the device. The
ground connection of the DAC serves as the return path for
supply currents as well as the reference point for the digital in-
put thresholds. The ground connection also serves as the supply
rail for the internal voltage reference and the output amplifier.
Therefore, to minimize any errors, it is recommended that

the ground connection of the DAC8512 be connected to a high
quality analog ground, such as the one described above. Gener-
ous bypassing of the DAC's supply goes a long way in reducing
supply line-induced errors. Local supply bypassing consisting of
a 10

F tantalum electrolytic in parallel with a 0.1

F ceramic is

recommended. The decoupling capacitors should be connected
between the DAC's supply pin (Pin 1) and the analog ground
(Pin 7). Figure 24 shows how the ground and bypass connec-
tions should be made to the DAC8512.

GND

DAC8512

0.1

OUT

+5V

TO ANALOG GROUND

CLR

SCLK

SDI

OUT

Figure 24. Recommended Grounding and Bypassing
Scheme for the DAC8512

Unipolar Output Operation

This is the basic mode of operation for the DAC8512. As shown
in Figure 24, the DAC8512 has been designed to drive loads as
low as 2 k

in parallel with 500 pF. The code table for this op-

eration is shown in Table II.

0.1

OUT

4.095V

+5V

500pF

DAC8512

CLR

SCLK

SDI

GND

OUT

Figure 25. Unipolar Output Operation

Table II. Unipolar Code Table

Hexadecimal Number

Decimal Number

Analog Output

in DAC Register

Voltage (V)

FFF

4095

+4.095

801

2049

+2.049

800

2048

+2.048

7FF

2047

+2.047

000

Typical Performance Characteristics--

DAC8512

REV. A

Operating the DAC8512 on +12 V or +15 V Supplies Only

Although the DAC8512 has been specified to operate on a
single, +5 V supply, a single +5 V supply may not be available in
many applications. Since the DAC8512 consumes no more than
2.5 mA, maximum, then an integrated voltage reference, such as
the REF02, can be used as the DAC8512 +5 V supply. The
configuration of the circuit is shown in Figure 26. Notice that
the reference's output voltage requires no trimming because of
the REF02's excellent load regulation and tight initial output
voltage tolerance. Although the maximum supply current of the
DAC8512 is 2.5 mA, local bypassing of the REF02's output
with at least 0.1

F at the DAC's voltage supply pin is recom-

mended to prevent the DAC's internal digital circuits from af-
fecting the DAC's internal voltage reference.

+12V OR +15V

0.1

REF02

0.1

DAC8512

OUT

GND

CLR

SCLK

SDI

Figure 26. Operating the DAC8512 on +12 V or +15 V
Supplies Using a REF02 Voltage Reference

Measuring Offset Error

One of the most commonly specified endpoint errors associated
with real world nonideal DACs is offset error.

In most DAC testing, the offset error is measured by applying
the zero-scale code and measuring the output deviation from 0
volt. There are some DACs where offset errors may be present
but not observable at the zero scale because of other circuit limi-
tations (for example, zero coinciding with single-supply ground).
In these DACs, nonzero output at zero code cannot be read as
the offset error. In the DAC8512, for example, the zero-scale
error is specified to be

3 LSBs. Since zero scale coincides with

zero volt, it is not possible to measure negative offset error.

OUT

0.1

200

A, MAX

DAC8512

+5V

CLR

SCLK

SDI

SET CODE = 000

AND MEASURE V

OUT

GND

Figure 27. Measuring Zero-Scale or Offset Error

By adding a pull-down resistor from the output of the DAC8412
to a negative supply as shown in Figure 27, offset errors can
now be read at zero code. This configuration forces the output
p-channel MOSFET to source current to the negative supply
thereby allowing the designer to determine in which direction the
offset error appears. The value of the resistor should be such that,
at zero code, current through the resistor is 200

A, maximum.

Bipolar Output Operation

Although the DAC8512 has been designed for single-supply op-
eration, bipolar operation is achievable using the circuit illus-
trated in Figure 28. The circuit uses a single-supply, rail-to-rail
OP295 op amp and the REF03 to generate the 2.5 V reference
required to level-shift the DAC output voltage. Note that the
2.5 V reference was generated without the use of precision resis-
tors. The circuit has been configured to provide an output
voltage in the range 5 V

OUT

+5 V and is coded in com-

plementary offset binary. Although each DAC LSB corresponds
to 1 mV, each output LSB has been scaled to 2.44 mV. Table
III provides the relationship between the digital codes and out-
put voltage.

The transfer function of the circuit is given by:

= 1 mV

Digital Code

+ 2.5

and, for the circuit values shown, becomes:

= 2.44 mV

Digital Code + 5 V

+5V

0.1

DAC8512

GND

10k

12.7k

R3
247k

5V

+5V

5V

10k

ZERO SCALE

ADJUST

500

23.7k

FULL SCALE

ADJUST

2.5V

CLR

SCLK

SDI

0.1

+5V

REF03

2.5V

0.01

100

P1
10k

2.5V

TRIM

A1, A2 = 1/2 OP295

Figure 28. Bipolar Output Operation

DAC8512

REV. A

Table III. Bipolar Code Table

Hexadecimal Number

Decimal Number

Analog Output

in DAC Register

Voltage (V)

4095

4.9976

801

2049

2.44E3

800

2048

7FF

2047

+2.44E3

000

To maintain monotonicity and accuracy, R1, R2, and R4 should
be selected to match within 0.01% and must all be of the same
(preferably metal foil) type to assure temperature coefficient
matching. Mismatching between R1 and R2 causes offset and gain
errors while an R4 to R1 and R2 mismatch yields gain errors.

For applications that do not require high accuracy, the circuit
illustrated in Figure 29 can also be used to generate a bipolar
output voltage. In this circuit, only one op amp is used and no
potentiometers are used for offset and gain trim. The output
voltage is coded in offset binary and is given by:

= 1 mV

Digital Code

2.5

43.2k + 499

10k

2.5V

OUT

RANGE

10k

20k

10k

15.4k + 274

CLR

SCLK

SDI

GND

DAC8512

+5V

0.1µF

+2.5V

REF03

+5V

5V

A1 = 1/2 OP295

+5V

0.1µF

Figure 29. Bipolar Output Operation without Trim

For the

2.5 V output range and the circuit values shown in the

table, the transfer equation becomes:

= 1.22 mV

Digital Code  2.5 V

Similarly, for the

5 V output range, the transfer equation

becomes:

= 2.44 mV

Digital Code  5 V

Generating a Negative Supply Voltage

Some applications may require bipolar output configuration but
only have a single power supply rail available. This is very com-
mon in data acquisition systems using microprocessor-based
systems. In these systems, +12 V, +15 V, and/or +5 V are only
available. Shown in Figure 30 is a method of generating a nega-
tive supply voltage using one CD4049, a CMOS hex inverter,
operating on +12 V or +15 V. The circuit is essentially a charge
pump where two of the six are used as an oscillator. For the val-
ues shown, the frequency of oscillation is approximately 3.5 kHz
and is fairly insensitive to supply voltage because R1 > 2

R2.

The remaining four inverters are wired in parallel for higher out-
put current. The square wave output is level translated by C2 to
a negative-going signal, rectified using a pair of 1N4001s, and
then filtered by C3. With the values shown, the charge pump
will provide an output voltage of 5 V for current loadings in the
range 0.5 mA

OUT

10 mA with a +15 V supply and 0.5 mA

OUT

7 mA with a +12 V supply.

R2
5.1k

R1
510k

0.02

C2
47

D1
1N4001

C3
47

1N5231
5.1V
ZENER

1N4001

470

5V

INVERTERS = CD4049

Figure 30. Generating a 5 V Supply When Only +12 V
or +15 V Is Available

A High-Compliance, Digitally Controlled Precision Current
Source

The circuit in Figure 31 shows the DAC8512 controlling a
high-compliance precision current source using an AMP05 in-
strumentation amplifier. The AMP05's reference pin becomes
the input, and the "old" inputs now monitor the voltage across a
precision current sense resistor, R

. Voltage gain is set to unity,

so the transfer function is given by the following equation:

OUT

If R

equals 100

, the output current is limited to +10 mA

with a 1 V input. Therefore, each DAC LSB corresponds to
2.4

A. If a bipolar output current is required, then the circuit

in Figure 28 can be modified to drive the AMP05's reference
pin with a

1 V input signal.

Potentiometer P1 trims the output current to zero with the in-
put at 0 V. Fine gain adjustment can be accomplished by adjust-
ing R1 or R2.

DAC8512

REV. A

100k

0.1

15V

AMP05

100

0mA

OUT

10mA

2.4

A/ BIT

0.1

+15V

0.1

REF02

0.1

R4
1k

DAC8512FZ

CLR

SCLK

SDI

Figure 31. A High-Compliance, Digitally Controlled
Precision Current Source

A Single-Supply, Programmable Current Source

The circuit in Figure 32 shows how the DAC8512 can be used
with an OP295 single-supply, rail-to-rail output op amp to pro-
vide a digitally programmable current sink from V

SOURCE

that

consumes less than 3.8 mA, maximum. The DAC's output volt-
age is applied across R1 by placing the 2N2222 transistor in the

OP295's feedback loop. For the circuit values shown, the full-
scale output current is 1 mA which is given by the following
equation:

OUT

4.095V

where DW = DAC8512's binary digital input code.

FULL-SCALE
ADJUST

A1 = 1/2 OP295

+5V

DAC8512FP

CLR

SCLK

SDI

+5V

0.1

LOAD

2N2222

R1
4.02k

P1
200

Figure 32. A Single-Supply, Programmable Current
Source

The usable output voltage range of the current sink is +5 V to
+60 V. The low limit of the range is controlled by transistor
saturation, and the high limit is controlled by the collector-base
breakdown voltage of the 2N2222.

A Digitally Programmable Window Detector

A digitally programmable, upper/lower limit detector using two
DAC8512s is shown in Figure 33. The required upper and
lower limits for the test are loaded into each DAC individually
by controlling HDAC/LDAC. If a signal at the test input is not
within the programmed limits, the output will indicate a logic
zero which will turn the red LED on.

1/6

74HC05

HDAC/LDAC

CLR

+5V

R1
604

RED LED

+5V

R2
604

GREEN LED

PASS/FAIL

C1, C2 = 1/4 CMP-404

1/6

74HC05

SCLK

SDI

0.1

+5V

DAC8512

0.1

+5V

DAC8512

0.1

Figure 33. A Digitally Programmable Window Detector

DAC8512

REV. A

Opto-Isolated Interfaces for Process Control Environments

In many process control type applications, it is necessary to pro-
vide an isolation barrier between the controller and the unit be-
ing controlled. Opto-isolators can provide isolation in excess of
3 kV. The serial loading structure of the DAC8512 makes it
ideal for opto-isolated interfaces as the number of interface lines
is kept to a minimum.

Illustrated in Figure 34 is an opto-isolated interface using the
DAC8512. In this circuit, the CS line is always LOW to enable
the DAC, and the 10 k

F combination connected to the

DAC's CLR pin sets a turn-on time constant of 10 ms to reset
the DAC upon application of power. Three opto-couplers are
then used for the SDI, SCLK, and LD lines.

Often times reducing the number of interface lines to two lines
is required in many control environments. The circuit illustrated
in Figure 35 shows how to convert a two-line interface into the
three control lines required to control the DAC8512 without us-
ing one shots. This technique uses a counter to keep track of the
clock cycles and, when all the data has been input to the DAC,
the external logic generates the LD pulse.

0.1

+5V

DAC8512

0.1

10k

+5V

VOUT

+5V

10k

SCLK

10k

SDI

10k

SCLK

SDI

+5V
REG

+5V

POWER

HIGH VOLTAGE
ISOLATION

Figure 34. An Opto-Isolated DAC Interface

+5V

10k

SCLK

SDI

+5V
REG

+5V

POWER

HIGH VOLTAGE
ISOLATION

74HC161

CLR

CLK

ENP

GND

RCO

ENT

LOAD

+5V

10k

0.1

+5V

10k

1/4 74HCOO

0.1

DAC8512

+5V

SCLK

SDI

CLR

GND

OUT

+5V

10k

Figure 35. A Two-Wire, Opto-lsolated DAC Interface

DAC8512

REV. A

COUNTER

CLK

LOAD

(X)

DAC8512

CLK (Y)

DAC8512 CLK = LOAD

SCLK

LOAD = Q

LOAD DAC

Figure 36. Opto-lsolated Two-Wire Serial Interface Timing Diagram

The timing diagram of Figure 36 can be used to understand the
operation of the circuit. Only two opto-couplers are used in the
circuit; one for SCLK and one for SDI. The 74HC161 counter
in incremented on every rising edge of the clock. Additionally,
the data is loaded into the DAC8512 on the falling edge of the
clock by inverting the serial clock using gate "Y." The timing
diagram shows that after the twelfth bit has been clocked the
output of the counter is binary 1011. On the very next rising
clock edge, the output of the counter changes to binary 1100
upon which the output of gate "X" goes LOW to generate the
LD

pulse. The LD signal is connected to both the DAC's LD

and the counter's LOAD pins to prevent the thirteenth rising
clock edge from advancing the DAC's internal shift register.
This prevents false loading of data into the DAC8512. Inverting
the DAC's serial clock allows sufficient time from the CLK edge
to the LD edge, and from the LD edge to the next clock pulse
all of which satisfies the timing requirements for loading the
DAC8512.

After loading one address of the DAC, the entire process can re-
peated to load another address. If the loading is complete, then
the clock must stop after the thirteenth pulse of the final load.
The DAC's clock input will be pulled high and the counter reset
to zero. As was shown in Figure 35, both the 74HC161's and
the DAC8512's CLR pins are connected to a simple R-C timing
circuit that resets both ICs when the power in turned on. The
circuit's time constant should be set longer than the power sup-
ply turn-on time and, in this circuit, is set to 10 ms, which
should be adequate for most systems. This same two-wire inter-
face can be used for other three-wire serial input DACs.

Decoding Multiple DAC8512s

The CS function of the DAC8512 can be used in applications
to decode a number of DACs. In this application, all DACs re-
ceive the same input data; however, only one of the DAC's CS
input is asserted to transfer its serial input register contents into
the destination DAC register. In this circuit, shown in Figure 37,
the CS timing is generated by a 74HC139 decoder and should
follow the DAC8512's standard timing requirements. To pre-
vent timing errors, the 74HC139 should not be activated by its

OUT3

DAC8512

OUT2

DAC8512

OUT1

DAC8512

GND

1Y0

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

+5V

ENABLE

CODED

ADDRESS

0.1

74HC139

OUT4

DAC8512

+5V

SCLK

SDI

Figure 37. Decoding Multiple DAC8512s Using the CS Pin

ENABLE input while the coded address inputs are changing. A
simple timing circuit, R1 and C1, connected to the DACs' CLR
pins resets all DAC outputs to zero during power-up.

DAC8512

REV. A

A Digitally Controlled, Ultralow Noise VCA

The circuit in Figure 38 illustrates how the DAC8512 can be
used to control an ultralow noise VCA, using the AD600/
AD602. The AD600/AD602 is a dual, low noise, wideband,
variable gain amplifier based on the X-AMP topology.* Both
channels of the AD600 are wired in parallel to achieve a
wideband VCA which exhibits an RTI (Referred To Input)
noise voltage spectral density of approximately 1 nV/

. The

output of the VCA requires an AD844 configured in a gain of 4
to account for signal loss due to input and output 50

termina-

tions. As configured, the total gain in the circuit is 40 dB.

Since the output of the DAC8512 is single quadrant, it was nec-
essary to offset the AD600's gain control voltage so that the gain
of the circuit is 0 dB for zero scale and 40 dB at full scale. This
was achieved by setting C1LO and C2LO to +625 mV using R1
and R2. Next, the output of the DAC8512 was scaled so that
the gain of the AD600 equaled 20 dB when the digital input
code equaled 800

. The frequency response of the VCA as a

function of digital code is shown in Figure 39.

*For more details regarding the AD600 or AD602, please consult the AD600/

AD602 data sheet.

+70

+20

30

100k

100M

10M

10k

+30

+40

+50

+60

20

10

+10

FREQUENCY Hz

SYSTEM GAIN dB

4095

3072

2048

1024

Figure 39. VCA Frequency Response vs. Digital Code

REF

AD600JN

V+

0.1

DAC8512FZ

CLR

0.1

V+

2.26k

R7
1k

1.25V

SCLK

SDI

619

4.32k

V+

+625mV

0.1

V+

OUT

0.01dB/BIT

+5V

5V

V+

FB = FAIR RITE

#2743001111

SUPPLY DECOUPLING NETWORK

806

402

49.9

I N

AD844

Figure 38. A Digitally Controlled, Ultralow Noise VCA

DAC8512

REV. A

A Serial DAC, Audio Volume Control

The DAC8512 is well suited to control digitally the gain or at-
tenuation of a voltage controlled amplifier. In professional audio
mixing consoles, music synthesizers, and other audio processors,
VCAs, such as the SSM2018, adjust audio channel gain and at-
tenuation from front panel potentiometers. The VCA provides a
clean gain transition control of the audio level when the slew
rate of the analog input control voltage, V

, is properly chosen.

The circuit in Figure 40 illustrates a volume control application
using the DAC8512 to control the attenuation of the SSM2018.

DAC8512

+15V

CLR

0.1

REF02

18k

10pF

470k

100k

10M

OFFSET

TRIM

47pF

SYMMETRY
TRIM

500k

OUT

+15V

15V

30k

+15V

15V

0.1

+15V

18k

SSM2018

+5V

0.1

CON

825

+2.24V

* PRECISION RESISTOR
PT146
1k

COMPENSATOR

SCLK

SDI

Figure 40. A Serial DAC, Audio Volume Control

Since the supply voltage available in these systems is typically

15 V or

18 V, a REF02 is used to supply the +5 V required

to power the DAC. No trimming of the reference is required be-
cause of the reference's tight initial tolerance and low supply
current consumption of the DAC8512. The SSM2018 is config-
ured as a unity-gain buffer when its control voltage equals 0
volt. This corresponds to a 000

code from the DAC8512.

Since the SSM2018 exhibits a gain constant of 28 mV/dB
(typical), the DAC's full-scale output voltage has to be scaled
down by R6 and R7 to provide 80 dB of attenuation when the

Table IV. SSM-2018 VCA Attenuation vs.
DAC8512 Input Code

Hexadecimal Number

Control

VCA

in DAC Register

Voltage (V)

Attenuation (dB)

000

400

+0.56

800

+1.12

C00

+1.68

FFF

+2.24

digital code equals FFF

. Therefore, every DAC LSB corre-

sponds to 0.02 dB of attenuation. Table IV illustrates the at-
tenuation vs. digital code of the volume control circuit.

To compensate for the SSM2018's gain constant temperature
coefficient of 3300 ppm/

C, a 1 k

, temperature-sensitive re-

sistor (R7) manufactured by the Precision Resistor Company
with a temperature coefficient of +3500 ppm/

C is used. A

CON

of 1

F provides a control transition time of 1 ms which

yields a click-free change in the audio channel attenuation. Sym-
metry and offset trimming details of the VCA can be found in
the SSM2018 data sheet.

Information regarding the PT146 1 k

"Compensator" can be

obtained by contacting:

Precision Resistor Company, Incorporated
10601 75th Street North
Largo, Fl 34647
(813) 541-5771

An Isolated, Programmable, 4-20 mA Process Controller

In many process control system, applications, two-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a "zero-scale" sig-
nal current of 4 mA that can be used to power the transmitter's
signal conditioning circuitry. The "full-scale" output signal in
these transmitters is 20 mA. The converse approach to process
control can also be used; a low-power, programmable current
source can be used to control remotely located sensors or de-
vices in the loop.

A circuit that performs this function is illustrated in Figure 41.
Using the DAC8512 as the controller, the circuit provides a
programmable output current of 4 mA to 20 mA, proportional
to the DAC's digital code. Biasing for the controller is provided
by the REF02 and requires no external trim for two reasons:

(1) the REF02's tight initial output voltage tolerance and (2) the
low supply current consumption of both the OP90 and the
DAC8512. The entire circuit, including opto-couplers, con-
sumes less than 3 mA from the total budget of 4 mA. The OP90
regulates the output current to satisfy the current summation at
the noninverting node of the OP-90. The KCL equation at
Pin 3 is given by:

OUT

1 mV

Digital Code

REF

DAC8512

REV. A

CLR

SCLK

SCI

DAC8512

200k

10k

20mA

ADJUST

80.6k

R2
976k

P2
50

4mA
ADJUST

R4
54.9k

R5
100k

150

Q1
2N1711

REF02

420mA

OP90

100

ILQ-1

CLK

SCLK

+5V

10k

360

REPEAT FOR SDI, LD, & CLR

D1 = HP5082-2810

100

LOOP

+12 TO +40V

Figure 41. An Isolated, Programmable, 4-20 mA Process Controller

For the values shown in Figure 41,

OUT

= 3.9

Digital Code + 4 mA

giving a full-scale output current of 20 mA when the
DAC8512's digital code equals FFF

. Offset trim at 4 mA is

provided by P2, and P1 provides the circuit's gain trim at 20 mA.
These two trims do not interact because the noninverting input
of the OP90 is at virtual ground. The Schottky diode, D1, is re-
quired in this circuit to prevent loop supply power-on transients
from pulling the noninverting input of the OP90 more than
300 mV below its inverting input. Without this diode, such tran-
sients could cause phase reversal of the OP90 and possible
latchup of the controller. The loop supply voltage compliance of
the circuit is limited by the maximum applied input voltage to
the REF02 and is from +12 V to +40 V.

MICROPROCESSOR INTERFACING

DAC8512MC68HC11 Interface

The circuit illustrated in Figure 42 shows a serial interface be-
tween the DAC8512 and the MC68HC11 8-bit microcontrol-
ler. SCK of the 68HC11 drives SCLK of the DAC8512, while
the MOSI output drives the serial data line, SDI, of the
DAC8512. The DAC's CLR, LD, and CS signals are derived
from port lines PC1, PD5, and PC0, respectively, as shown.

For correct operation of the serial interface, the 68HC11 should
be configured such that its CPOL bit is set to 1 and its CPHA
bit is also set to 1. When the serial data is to be transmitted to
the DAC, PC0 is taken low, asserting the DAC's CS input.
When the 68HC11 is configured in this manner, serial data on

PC1

PC0

SCK

MOSI

CLK

SDI

MC68HC11*

DAC8512*

CLR

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 42. DAC8512MC68HC11 Interface

MOSI is valid on the rising edge of SCLK. The 68HC11 trans-
mits its serial data in 8-bit bytes (MSB first), with only eight ris-
ing clock edges occurring in the transmit cycle. To load data to
the DAC8512's input serial register, PC0 is left low after the
first eight bits are transferred, and a second byte of data is then
transferred serially to the DAC8512. During the second byte
load, the first four most significant bits of the first byte are
pushed out of the DAC's input shift register. At the end of the
second byte load, PC0 is then taken high. To prevent an acci-
dental advancing of the internal shift register, SCLK must al-
ready be asserted before PC0 is taken high. To transfer the
contents of the input shift register to the DAC register, PD5 is
taken low, asserting the DAC's LD input. The DAC's CLR in-
put, controlled by the 68HC11's PC1 port, provides an asyn-
chronous clear function, setting the DAC output to zero.
Included in this section is the source code for operating the
DAC8512--M68HC11 interface.

DAC8512

REV. A

DAC8512M68HC11 Interface Program Source Code

*
PORTC

EQU

$1003

Port C control register

"0,0,0,0;0,0,CLR/,CS/"

DDRC

EQU

$1007

Port C data direction

PORTD

EQU

$1008

Port D data register

"0,0,LD/,SCLK;SDI,0,0,0

DDRD

EQU

$1009

Port D data direction

SPCR

EQU

$1028

SPI control register

"SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPRl,SPR0"

SPSR

EQU

$1029

SPI status register

"SPIF,WCOL,0,MODF;0,0,0,0"

SPDR

EQU

$102A

SPI data register; Read-Buffer; Write-Shifter

* SDI RAM variables:

SDI1 is encoded from 0 (Hex) to F (Hex)

SDI2 is encoded from 00 (Hex) to FF (Hex)

DAC requires two 8-bit loads; upper 4 bits of SDI1

are ignored.

*
SDI1

EQU

$00

SDI packed byte 1 "0,0,0,0;MSB,DB10,DB9,DB8"

SDI2

EQU

$01

SDI packed byte 2 "DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0"

ORG

$C000

Start of user's RAM in EVB

INIT

LDS

#$CFFF

Top of C page RAM

LDAA

#$03

0,0,0,0;0,0,1,1

CLR/-Hi, CS/-Hi

STAA

PORTC

Initialize Port C Outputs

LDAA

#$03

0,0,0,0;0,0,1,1

STAA

DDRC

CLR/ and CS/ are now enabled as outputs

LDAA

#$30

0,0,1,1;0,0,0,0

LDI-Hi,SCLK-Hi,SDI-Lo

STAA

PORTD

Initialize Port D Outputs

LDAA

#$38

0,0,1,1;1,0,0,0

STAA

DDRD

LD/,SCLK, and SDI are now enabled as outputs

LDAA

#$5F

STAA

SPCR

SPI is Master,CPHA=1,CPOL=1,Clk rate=E/32

BSR

UPDATE

Xfer 2 8-bit words to DAC8512

JMP

$E000

Restart BUFFALO

*
UPDATE

PSHX

Save registers X, Y, and A

PSHY
PSHA

LDAA

#$0A

0,0,0,0;1,0,1,0

STAA

SDI1

SDI1 is set to 0A (Hex)

LDAA

#$AA

1,0,1,0;1,0,1,0

STAA

SDI2

SDI2 is set to AA (Hex)

LDX

#SDI1

Stack pointer at 1st byte to send via SDI

LDY

#$1000

Stack pointer at on-chip registers

BCLR

PORTC,Y

$02 Assert CLR/

BSET

PORTC,Y

$02 De-assert CLR/

BCLR

PORTC,Y

$01 Assert CS/

DAC8512

REV. A

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

C1734xx11/96

PRINTED IN U.S.A.

8-Pin Plastic DIP (P Suffix)

0.160 (4.06)

0.115 (2.93)

0.430 (10.92)

0.348 (8.84)

0.280 (7.11)

0.240 (6.10)

0.070 (1.77)

0.045 (1.15)

0.022 (0.558)

0.014 (0.356)

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

0.195 (4.95)

0.115 (2.93)

0.130

(3.30)

MIN

0.210

(5.33)

MAX

0.015

(0.381) TYP

- 15

0.100

(2.54)

BSC

SEATING

PLANE

8-Pin Cerdip (Z Suffix)

0.005 (0.13) MIN

0.055 (1.4) MAX

0.405 (10.29) MAX

0.150

(3.81)

MIN

0.200

(5.08)

MAX

0.070 (1.78)

0.030 (0.76)

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

0.060 (1.52)

0.015 (0.38)

-15

0.100 (2.54)

BSC

SEATING PLANE

0.310 (7.87)

0.220 (5.59)

8-Lead SOIC (S Suffix)

SEATING

PLANE

SEE DETAIL

ABOVE

0.0688 (1.75)
0.0532 (1.35)

0.0098 (0.25)
0.0075 (0.19)

0.1574 (4.00)
0.1497 (3.80)

0.2440 (6.20)
0.2284 (5.80)

0.1968 (5.00)
0.1890 (4.80)

0.0192 (0.49)
0.0138 (0.35)

0.0500

(1.27)

BSC

0.0098 (0.25)
0.0040 (0.10)

0.0196 (0.50)
0.0099 (0.25)

0.0500 (1.27)
0.0160 (0.41)

PIN 1

- 8

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC8512EP

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DAC8512EP