Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- TABLE OF CONTENTS
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-
-
-
-
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-
-
-
-
-
-
-
-
- Control Latch
- N Counter Latch
- R Counter Latch
-
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-
Integrated Synthesizer and VCO
ADF4360-1
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
Output frequency range: 2050 MHz to 2450 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-1 is a fully integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-1 is
designed for a center frequency of 2250 MHz. In addition, there
is a divide-by-2 option available, whereby the user gets an RF
output of between 1025 MHz and 1225 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CP
V
VCO
REF
IN
CLK
DATA
LE
AV
DD
DV
DD
CE
AGND
DGND
CPGND
R
SET
V
TUNE
C
C
C
N
RF
OUT
A
RF
OUT
B
VCO
CORE
PHASE
COMPARATOR
MUTE
DIVSEL = 2
DIVSEL = 1
N = (BP + A)
LOAD
LOAD
CHARGE
PUMP
OUTPUT
STAGE
M
U
L
T
I
PL
EXER
INTEGER
REGISTER
13-BIT B
COUNTER
14-BIT R
COUNTER
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
5-BIT A
COUNTER
PRESCALER
P/P+1
MULTIPLEXER
LOCK
DETECT
2
ADF4360-1
04414-0-001
Figure 1.
ADF4360-1
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description........................................................................... 9
Reference Input Section............................................................... 9
Prescaler (P/P + 1)........................................................................ 9
A and B Counters ......................................................................... 9
R Counter ...................................................................................... 9
PFD and Charge Pump................................................................ 9
MUXOUT and Lock Detect...................................................... 10
Input Shift Register..................................................................... 10
VCO ............................................................................................. 10
Output Stage................................................................................ 11
Latch Structure ........................................................................... 12
Control Latch .............................................................................. 16
N Counter Latch......................................................................... 17
R Counter Latch ......................................................................... 17
Applications..................................................................................... 18
Direct Conversion Modulator .................................................. 18
Fixed Frequency LO................................................................... 19
Power-Up..................................................................................... 19
Interfacing ................................................................................... 19
PCB Design Guidelines for Chip-Scale Package.......................... 20
Output Matching ........................................................................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
6/04--Data Sheet Changed from Rev. 0 to Rev. A
Changes to Specifications ................................................................ 3
Changes to Table 6.......................................................................... 12
Changes to Table 7.......................................................................... 13
Changes to Table 9.......................................................................... 15
8/03--Revision 0: Initial Version
ADF4360-1
Rev. A | Page 3 of 24
SPECIFICATIONS
1
AV
DD
= DV
DD
= V
VCO
= 3.3 V 10%; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter B
Version
Unit
Conditions/Comments
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency
10/250
MHz min/max
For f < 10 MHz, use a dc-coupled CMOS compatible
square wave, slew rate > 21 V/s.
REF
IN
Input Sensitivity
0.7/AV
DD
p-p min/max
AC-coupled.
0 to AV
DD
V max
CMOS compatible.
REF
IN
Input Capacitance
5.0
pF max
REF
IN
Input Current
100
A max
PHASE DETECTOR
Phase Detector Frequency
2
8
MHz max
CHARGE PUMP
I
CP
Sink/Source
3
With R
SET
= 4.7 k.
High Value
2.5
mA typ
Low Value
0.312
mA typ
R
SET
Range
2.7/10
k
I
CP
3-State Leakage Current
0.2
nA typ
Sink and Source Current Matching
2
% typ
1.25 V V
CP
2.5 V.
I
CP
vs. V
CP
1.5
% typ
1.25 V V
CP
2.5 V.
I
CP
vs. Temperature
2
% typ
V
CP
= 2.0 V.
LOGIC INPUTS
V
INH,
, Input High Voltage
1.5
V min
V
INL
, Input Low Voltage
0.6
V max
I
INH
/I
INL
, Input Current
1
A max
C
IN
, Input Capacitance
3.0
pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage
DV
DD
0.4
V min
CMOS output chosen.
I
OH
, Output High Current
500
A max
V
OL
, Output Low Voltage
0.4
V max
I
OL
= 500 A.
POWER SUPPLIES
AV
DD
3.0/3.6
V min/V max
DV
DD
AV
DD
V
VCO
AV
DD
AI
DD
4
10
mA typ
DI
DD
4
2.5
mA typ
I
VCO
4, 5
24.0
mA typ
I
CORE
= 15 mA.
I
RFOUT
4
3.511.0
mA typ
RF output stage is programmeable.
Low Power Sleep Mode
4
7
A typ
RF OUTPUT CHARACTERISTICS
5
VCO Output Frequency
2050/2450
MHz min/max
I
CORE
= 15 mA.
VCO Sensitivity
57
MHz/V typ
Lock Time
6
400
s typ
To within 10 Hz of final frequency.
Frequency Pushing, (Open Loop)
6
MHz/V typ
Frequency Pulling, (Open Loop)
15
kHz typ
Into 2.00 VSWR load.
Harmonic Content (Second)
-20
dBc typ
Harmonic Content (Third)
-35
dBc typ
Output Power
5, 7
-13/-6
dBm typ
Programmable in 3 dB steps. Table 7.
Output Power Variation
3
dB typ
For tuned loads, see Output Matching section.
VCO Tuning Range
1.25/2.5
V min/max
ADF4360-1
Rev. A | Page 4 of 24
Parameter B
Version
Unit
Conditions/Comments
NOISE CHARACTERISTICS
1, 5
VCO Phase Noise Performance
8
-110
dBc/Hz typ
@ 100 kHz offset from carrier.
-130
dBc/Hz typ
@ 1 MHz offset from carrier.
-141
dBc/Hz typ
@ 3 MHz offset from carrier.
-148
dBc/Hz typ
@ 10 MHz offset from carrier.
Synthesizer Phase Noise Floor
9
-172
dBc/Hz typ
@ 25 kHz PFD frequency.
-163
dBc/Hz typ
@ 200 kHz PFD frequency.
-147
dBc/Hz typ
@ 8 MHz PFD frequency.
In-Band Phase Noise
10,
11
-81
dBc/Hz typ
@ 1 kHz offset from carrier.
RMS Integrated Phase Error
12
0.72
Degrees typ
100 Hz to 100 kHz.
Spurious Signals due to PFD Frequency
11,
13
-70
dBc typ
1
Operating temperature range is: 40C to +85C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
I
CP
is internally modified to maintain constant-loop gain over the frequency range.
4
T
A
= 25C; AV
DD
= DV
DD
= V
VCO
= 3.3 V; P = 32.
5
These characteristics are guaranteed for VCO Core Power = 15 mA.
6
Jumping from 2.05 GHz to 2.45 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
Using 50 resistors to V
VCO
, into a 50 load. For tuned loads, see
section.
Output Matching
8
The noise of the VCO is measured in open-loop conditions.
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).
10
The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
11
f
REFIN
= 10 MHz; f
PFD
= 200 kHz; N = 12500; Loop B/W = 10 kHz.
12
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; N = 2400; Loop B/W = 25 kHz.
13
The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer; f
REFOUT
= 10 MHz @ 0 dBm.
ADF4360-1
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= V
VCO
= 3.3 V 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
Limit at T
MIN
to T
MAX
(B Version)
Unit
Test Conditions/Comments
t
1
20
ns min
LE Setup Time
t
2
10
ns min
DATA to CLOCK Setup Time
t
3
10
ns min
DATA to CLOCK Hold Time
t
4
25
ns min
CLOCK High Duration
t
5
25
ns min
CLOCK Low Duration
t
6
10
ns min
CLOCK to LE Setup Time
t
7
20
ns min
LE Pulse Width
CLOCK
DATA
LE
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
04414-
0-
002
Figure 2. Timing Diagram
ADF4360-1
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to GND
1
-0.3 V to +3.9 V
AV
DD
to DV
DD
-0.3 V to +0.3 V
V
VCO
to GND
-0.3 V to +3.9 V
V
VCO
to AV
DD
-0.3 V to +0.3 V
Digital I/O Voltage to GND
-0.3 V to V
DD
+ 0.3 V
Analog I/O Voltage to GND
-0.3 V to V
DD
+ 0.3 V
REF
IN
to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Maximum Junction Temperature
150C
CSP
JA
Thermal Impedance
(Paddle Soldered)
50C/W
(Paddle Not Soldered)
88C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
215C
Infrared (15 sec)
220C
1
GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat-
ing only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device
reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
12543 (CMOS) and 700 (Bipolar)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADF4360-1
Rev. A | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADF4360
TOP VIEW
(Not to Scale)
CPGND
1
AV
DD
2
AGND
3
RF
OUT
A
4
RF
OUT
B
5
V
VCO
6
DATA
18
CLK
17
REF
IN
16
DGND
15
C
N
14
R
SET
13
V
TUNE
7
AGND
8
AGND
9
AGND
10
AGND
11
C
C
12
CP
24
CE
23
AGND
22
DV
DD
21
MUXOU
T
20
LE
19
04414-
0-
003
PIN 1
IDENTIFIER
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Function
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2 AV
DD
Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV
DD
must have the same value as DV
DD
.
3, 8 to 11, 22
AGND
Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF
OUT
A
VCO Output. The output level is programmable from -6 dBm to -13 dBm. See the Output Matching section
for a description of the various output stages.
5 RF
OUT
B
VCO Complementary Output. The output level is programmable from -6 dBm to -13 dBm. See Output
Matching section for a description of the various output stages.
6 V
VCO
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V
VCO
must have the same value as AV
DD
.
7 V
TUNE
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
output voltage.
12 C
C
Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 R
SET
Connecting a resistor between this pin and CP
GND
sets the maximum charge pump output current for the
synthesizer. The nominal voltage potential at the R
SET
pin is 0.6 V. The relationship between I
CP
and R
SET
is
SET
CPmax
R
I
75
.
11
=
With R
SET
= 4.7 k, I
CPMAX
= 2.5 mA.
14 C
N
Internal Compensation Node. This pin must be decoupled to V
VCO
with a 10 F capacitor.
15
DGND
Digital Ground.
16 REF
IN
Reference Input. This is a CMOS input with a nominal threshold of V
DD
/2 and a dc equivalent input resistance of
100 k. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
17 CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
19 LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the
four latches, and the relevant latch is selected using the control bits.
20 MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
21 DV
DD
Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV
DD
must have the same value as AV
DD
.
23 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bits.
24 CP
Charge Pump Output. When enabled, this provides I
CP
to the external loop filter, which in turn drives the
internal VCO.
ADF4360-1
Rev. A | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
04414-0-004
150
160
170
140
130
120
110
100
90
80
70
40
50
60
30
20
10
0
1k
10M
1M
100k
10k
FREQUENCY OFFSET (Hz)
4
3
2
1
OUTPUT POWER (dB)
Figure 4. Open Loop VCO Phase Noise
04414-0-005
145
150
155
140
135
130
125
120
115
110
105
90
95
100
85
80
75
70
100
10M
1M
100k
10k
1000
FREQUENCY OFFSET (Hz)
O
U
T
P
UT
PO
WER (d
B)
Figure 5. VCO Phase Noise, 2250 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth
04414-0-006
145
150
155
140
135
130
125
120
115
110
105
90
95
100
85
80
75
70
100
10M
1M
100k
10k
1000
FREQUENCY OFFSET (Hz)
O
U
T
P
UT
PO
WER (d
B)
Figure 6. VCO Phase Noise, 1125 MHz,
Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth
04414-0-007
OUTP
UT P
O
W
E
R (dB)
90
80
70
60
50
40
30
20
10
0
2kHz
1kHz
2250MHz
1kHz
2kHz
83.0dBc/Hz
V
DD
= 3V, V
VCO
= 3V
I
CP
= 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10
Figure 7. Close-In Phase Noise at 2250 MHz (200 kHz Channel Spacing)
04414-
0-
008
OUTPUT POW
E
R (
d
B)
90
80
70
60
50
40
30
20
10
0
200kHz
100kHz
2250MHz
100kHz
200kHz
70.7dBc
V
DD
= 3V, V
VCO
= 3V
I
CP
= 2.5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 1.3 SECONDS
AVERAGES = 1
Figure 8. Reference Spurs at 2250 MHz
(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)
04414-0-009
OUTP
UT P
O
W
E
R (dB)
90
80
70
60
50
40
30
20
10
0
1MHz
0.5MHz
2250MHz
0.5MHz
1MHz
84.8dBc/Hz
V
DD
= 3V, V
VCO
= 3V
I
CP
= 2.5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 25kHz
RES. BANDWIDTH = 10kHz
VIDEO BANDWIDTH = 10kHz
SWEEP = 1.9 SECONDS
AVERAGES = 10
Figure 9. Reference Spurs at 2250 MHz
(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)
ADF4360-1
Rev. A | Page 9 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
04414-0-010
BUFFER
TO R COUNTER
REF
IN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
Figure 10. Reference Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the VCO and divides it down to a manage-
able frequency for the CMOS A and B counters. The prescaler is
programmable. It can be set in software to 8/9, 16/17, or 32/33
and is based on a synchronous 4/5 core. There is a minimum
divide ratio possible for fully contiguous output frequencies;
this minimum is determined by P, the prescaler value, and is
given by (P
2
-P).
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feed-
back counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with a VCO
frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is
(
)
R
f
A
B
P
f
REFIN
VCO
/
]
+
[
=
where:
f
VCO
is the output frequency of the VCO.
P is the preset modulus of the dual-modulus prescaler (8/9,
16/17, and so on).
B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).
f
REFIN
is the external reference frequency oscillator.
N = BP + A
TO PFD
FROM VCO
N DIVIDER
MODULUS
CONTROL
LOAD
LOAD
13-BIT B
COUNTER
5-BIT A
COUNTER
PRESCALER
P/P+1
04414-0-011
Figure 11. A and B Counters
R COUNTER
The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 12 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
R counter latch, ABP2 and ABP1, control the width of the pulse
(see Table 9).
04414-
0-
012
PROGRAMMABLE
DELAY
U3
CLR2
Q2
D2
U2
CLR1
Q1
D1
CHARGE
PUMP
DOWN
UP
HI
HI
U1
ABP1
ABP2
R DIVIDER
N DIVIDER
CP OUTPUT
R DIVIDER
N DIVIDER
CP
CPGND
V
P
Figure 12. PFD Simplified Schematic and Timing (In Lock)
ADF4360-1
Rev. A | Page 10 of 24
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown on Table 7. Figure 13 shows
the MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It will stay set
high until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 k nominal. When
lock has been detected, this output will be high with narrow
low-going pulses.
R COUNTER OUTPUT
N COUNTER OUTPUT
DIGITAL LOCK DETECT
DGND
CONTROL
MUX
MUXOUT
DV
DD
ANALOG LOCK DETECT
SDOUT
04414-0-013
Figure 13. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4360 family's digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter, com-
prising of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs--DB1,
DB0--as shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2
C1
Data Latch
0
0
Control Latch
0
1
R Counter
1
0
N Counter (A and B)
1
1
Test Modes Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range to
be covered without a large VCO sensitivity (K
V
) and resultant
poor phase noise and spurious performance.
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
1.
R counter latch
2.
Control latch
3.
N counter latch
During band select, which takes five PFD cycles, the VCO V
TUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
04414-0-014
0.4
0.2
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.4
2.2
2.0
2.6
2.8
3.0
1850
1900
1950
2000
2050
2100
2150
2200
2250
2300
2350
2400
2450
2500
2550
2600
FREQUENCY (MHz)
VOLTAGE (V)
Figure 14. Frequency vs. V
TUNE
, ADF4360-1
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by Bits BSC1 and BSC2 in the R counter latch.
Where the required PFD frequency exceeds 1 MHz, the divide
ratio should be set to allow enough time for correct band
selection.
ADF4360-1
Rev. A | Page 11 of 24
After band select, normal PLL action resumes. The nominal value
of K
V
is 57 MHz/V or 28 MHZ/V if divide-by-2 operation has been
selected (by programming DIV2 (DB22), high in the N counter
latch). The ADF4360 family contains linearization circuitry to
minimize any variation of the product of I
CP
and K
V
.
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
DD
.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
VCO
RF
OUT
A
RF
OUT
B
BUFFER/
DIVIDE BY 2
04414-0-015
OUTPUT STAGE
The RF
OUT
A and RF
OUT
B pins of the ADF4360 family are con-
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of -13 dBm, -10.5 dBm,
-8 dBm, and -6 dBm, respectively, using a 50 resistor to V
DD
and ac coupling into a 50 load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180 microstrip
coupler (see the Output Matching section).
Figure 15. Output Stage ADF4360-1
ADF4360-1
Rev. A | Page 12 of 24
LATCH STRUCTURE
Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed.
Table 6. Latch Structure
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
PC1
PC2
CR
M1
M2
PDP
CP
CPG
MTLD
PL1
PL2
CPI1
CPI2
CPI3
CPI4
CPI5
CPI6
PD1
M3
CONTROL
BITS
MUXOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
PRESCALER
VALUE
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21
DB22
DB23
PO
WER-
DO
W
N
2
PO
WER-
DO
W
N
1
CO
UNTER
RESET
M
U
TE-
T
I
LL-
LD
C
P
GA
IN
CP
T
HREE-
STATE
PHASE
DET
E
CT
OR
POL
ARIT
Y
PD2
P1
P2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
R1
R2
R3
R4
R5
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
LDP
TMB
BSC1
R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21
DB22
DB23
LO
C
K
DET
E
CT
PRECISION
TEST
MO
D
E
BIT
RESERVED
RESERVED
DI
VI
DE-
BY-
2
DI
VI
DE-
B
Y-
2 SELECT
BSC2
RSV
RSV
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
RSV
CONTROL
BITS
5-BIT A COUNTER
13-BIT B COUNTER
CONTROL LATCH
N COUNTER LATCH
R COUNTER LATCH
DB21
DB22
DB23
C
P
GA
IN
RESERVED
CPG
DIV2
DIVSEL
04414-0-026
ADF4360-1
Rev. A | Page 13 of 24
Table 7. Control Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
PC1
PC2
CR
M1
M2
PDP
CP
CPG
MTLD
PL1
PL2
CPI1
CPI2
CPI3
CPI4
CPI5
CPI6
PD1
M3
CONTROL
BITS
MUXOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
PRESCALER
VALUE
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21
DB22
DB23
POWER-
DOWN 2
POWER-
DOWN 1
COUNT
ER
RESET
MU
TE
-
T
I
LL-
LD
CP GAIN
CP
T
HREE-
STATE
PHASE
DET
E
CT
O
R
PO
L
ARIT
Y
PD2
P1
P2
CR
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
PC2
0
0
1
0
CORE POWER LEVEL
5mA
10mA
15mA
PC1
0
1
1
1
20mA
CP
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
PDP
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
CPG
0
1
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
MTLD
0
1
MUTE-TILL-LOCK DETECT
DISABLED
ENABLED
M3
M2
M1
OUTPUT
THREE-STATE OUTPUT
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
P2
P1
PRESCALER VALUE
0
0
8/9
0
1
16/17
1
0
32/33
1
1
32/33
CE PIN
PD2
PD1
MODE
0
X
X
ASYNCHRONOUS POWER-DOWN
1
X
0
NORMAL OPERATION
1
0
1
ASYNCHRONOUS POWER-DOWN
1
1
1
SYNCHRONOUS POWER-DOWN
CPI6
CPI5
CPI4
I
CP
(mA)
CPI3
CPI2
CPI1
4.7k
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PL2
PL1
OUTPUT POWER LEVEL
CURRENT
POWER INTO 50
(USING 50
TO V
VCO
)
13dBm
10.5dBm
8dBm
6dBm
0
0
1
1
0
1
0
1
3.5mA
5.0mA
7.5mA
11.0mA
04414-0-016
ADF4360-1
Rev. A | Page 14 of 24
Table 8. N Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
RSV
CONTROL
BITS
5-BIT A COUNTER
13-BIT B COUNTER
DB21
DB22
DB23
CP GAIN
DIVIDE-BY-
2 SELECT
DIVIDE-
BY-2
RESERVED
CPG
DIV2
DIVSEL
THIS BIT IS NOT USED
BY THE DEVICE AND
IS A DON'T CARE BIT.
A5
A4
..........
A2
A1
A COUNTER
DIVIDE RATIO
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
28
1
1
..........
0
1
29
1
1
..........
1
0
30
1
1
..........
1
1
31
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN
OPERATION
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
0
0
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
1
0
N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N
F
REF
), AT THE OUTPUT, N
MIN
IS (P
2
P).
B13
B12
B11
B3
B2
B1
B COUNTER DIVIDE RATIO
..........
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOT ALLOWED
..........
0
0
1
NOT ALLOWED
..........
0
1
0
NOT ALLOWED
..........
1
1
1
3
..........
.
.
.
.
.
.
.
.
.
.
.
.
.
..........
.
.
.
.
..........
.
.
.
.
..........
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
8188
..........
1
0
1
8189
..........
1
1
0
8190
..........
1
1
1
8191
04414-0-018
DIV2
0
1
DIVIDE-BY-2
FUNDAMENTAL OUTPUT
DIVIDE-BY-2
DIVSEL
0
1
DIVIDE-BY-2 SELECT (PRESCALER INPUT)
FUNDAMENTAL OUTPUT SELECTED
DIVIDE-BY-2 SELECTED
ADF4360-1
Rev. A | Page 15 of 24
Table 9. R Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
R1
R2
R3
R4
R5
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
LDP
TMB
BSC1
R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21
DB22
DB23
LO
CK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED
RESERVED
BSC2
RSV
RSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14
R13
R12
R3
R2
R1
DIVIDE RATIO
..........
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not Allowed
..........
0
0
1
1
..........
0
1
0
2
..........
0
1
1
3
..........
.
.
.
.
.
.
.
.
.
.
.
.
.
..........
.
.
.
.
..........
.
.
.
.
..........
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
16380
..........
1
0
1
16381
..........
1
1
0
16382
..........
1
1
1
16383
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
04414-
0-
017
LDP
LOCK DETECT PRECISION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
0
3.0ns
0
1
1.3ns
1
0
6.0ns
1
1
3.0ns
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
0
0
1
0
1
2
1
0
4
1
1
8
ADF4360-1
Rev. A | Page 16 of 24
CONTROL LATCH
With (C2, C1) = (0, 0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.
Prescaler Value
In the ADF4360 family, P2 and P1 in the control latch set the
prescaler values.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable power-
down modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 has been loaded with a 0. In the pro-
grammed synchronous power-down, the device power-down is
gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a 1 into
Bit PD1 (on the condition that a 1 has also been loaded to PD2),
the device will go into power-down on the second rising edge of
the R counter output, after LE goes high. When the CE pin is
low, the device is immediately disabled regardless of the state of
PD1 or PD2.
When a power-down is activated (either in synchronous or
asynchronous mode), the following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load
state conditions.
The charge pump is forced into three-state mode.
The digital lock detect circuitry is reset.
The RF outputs are debiased to a high impedance state.
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1.
CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7.
Output Power Level
Bits PL1 and PL2 set the output power level of the VCO. See the
truth table in Table 7.
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360 family is the Mute-Till-
Lock Detect bit. This function, when enabled, ensures that the RF
outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the Charge
Pump Gain bit. When it is programmed to a 1, Current Setting 2
is used. When it is programmed to a 0, Current Setting 1 is used.
Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0. This is
required if an active inverting loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Table 7.
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The recom-
mended setting is 15 mA. See the truth table in Table 7.
ADF4360-1
Rev. A | Page 17 of 24
N COUNTER LATCH
With (C2, C1) = (1, 0), the N counter latch is programmed.
Table 8 shows the input data format for programming the
N counter latch.
A Counter Latch
A5 to A1 program the 5-bit A counter. The divide range is 0
(00000) to 31 (11111).
Reserved Bits
DB7 is a spare bit and has been designated as Reserved. It
should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00.....0011) to 8191 (11....111).
Overall Divide Range
The overall divide range is defined by ((P B) + A), where P is
the prescaler value.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When this is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is used.
This bit can also be programmed through DB10 of the control
latch. The bit will always reflect the latest value written to it,
whether this is through the control latch or the N counter latch.
Divide-by-2
DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2
function is chosen. When it is set to 0, normal operation occurs.
Divide-by-2 Select
DB23 is the divide-by-2 select bit. When programmed to 1, the
divide-by-2 output is selected as the prescaler input. When set
to 0, the fundamental is used as the prescaler input. For exam-
ple, using the output divide-by-2 feature and a PFD frequency
of 200 kHz, the user will need a value of N = 12,000 to generate
1.2 GHz. With the divide-by-2 select bit high, the user may keep
N = 6,000.
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Table 9 shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is 1
(00......001) to 16383 (111......111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
DB18 is the lock detect precision bit and sets the number of
references cycles with less than 15 ns phase error for entering
the locked state. With LDP at 1, five cycles are taken, and with
LDP at 0, three cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be pro-
grammed by the user.
Band Select Clock
These bits set a divider for the band select logic clock input. The
output of the R counter is by default the value used to clock the
band select logic, but if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).
Reserved Bits
DB23 to DB22 are spare bits and have been designated as
Reserved. They should be programmed to 0.
ADF4360-1
Rev. A | Page 18 of 24
APPLICATIONS
DIRECT CONVERSION MODULATOR
Direct conversion architectures are increasingly being used to
implement base station transmitters. Figure 16 shows how ADI
parts can be used to implement such a system.
The circuit block diagram shows the AD9761 TxDAC being
used with the AD8349. The use of dual integrated DACs, such
as the AD9761 with its specified 0.02 dB and 0.004 dB gain
and offset matching characteristics, ensures minimum error
contribution (over temperature) from this portion of the
signal chain.
The local oscillator is implemented using the ADF4360-1. The
low-pass filter was designed using ADIsimPLL for a channel
spacing of 1 MHz and an open-loop bandwidth of 25 kHz. The
frequency range of the ADF4360-1 (2.05 GHz to 2.45 GHz)
makes it ideally suited for implementation of a Bluetooth
transceiver.
The LO ports of the AD8349 can be driven differentially from
the complementary RF
OUT
A and RF
OUT
B outputs of the
ADF4360-1. This gives a better performance than a single-
ended LO driver and eliminates the often necessary use of a
balun to convert from a single-ended LO input to the more
desirable differential LO inputs for the AD8349. The typical
rms phase noise (100 Hz to 100 kHz) of the LO in this
configuration is 1.09.
The AD8349 accepts LO drive levels from -10 dBm to 0 dBm.
The optimum LO power can be software programmed on the
ADF4360-1, which allows levels from -13 dBm to -6 dBm from
each output.
The RF output is designed to drive a 50 load but must be ac-
coupled, as shown in Figure 16. If the I and Q inputs are driven
in quadrature by 2 V p-p signals, the resulting output power
from the modulator will be approximately 2 dBm.
AD9761
TxDAC
AD8349
REFIO
FSADJ
MODULATED
DIGITAL
DATA
QOUTB
IOUTA
IOUTB
QOUTA
2k
LOW-PASS
FILTER
LOW-PASS
FILTER
SPI COMPATIBLE SERIAL BUS
ADF4360-1
V
VCO
V
VCO
V
VCO
CPGND
AGND
DGND RF
OUT
B
RF
OUT
A
CP
1nF
680pF
330pF
10nF
47nH
47nH
1.5pF
1.5pF
100pF
TO RF PA
3.9nH
3.9nH
1nF
1nF
4.7k
3.9k
2k
R
SET
C
C
LE
DATA
CLK
REF
IN
FREF
IN
C
N
V
TUNE
DV
DD
AV
DD
CE MUXOUT
VPS1
IBBP
IBBN
QBBP
QBBN
LOIP
LOIN
VPS2
5
4
24
7
20
23
2
21
6
14
16
17
18
19
13
1
3
8
9
10 11 22
15
12
V
DD
LOCK
DETECT
PHASE
SPLITTER
04414-
0-
019
51
10
F
Figure 16. Direct Conversion Modulator
ADF4360-1
Rev. A | Page 19 of 24
FIXED FREQUENCY LO
Figure 17 shows the ADF4360-1 used as a fixed frequency LO at
2.2 GHz. The low-pass filter was designed using ADIsimPLL for
a channel spacing of 8 MHz and an open-loop bandwidth of
40 kHz. The maximum PFD frequency of the ADF4360-1 is
8 MHz. Since using a larger PFD frequency allows users to use a
smaller N, the in-band phase noise is reduced to as low as pos-
sible, 99 dBc/Hz. The 40 kHz bandwidth is chosen to be just
greater than the point at which the open-loop phase noise of the
VCO is 99 dBc/Hz, thus giving the best possible integrated
noise. The typical rms phase noise (100 Hz to 100 kHz) of the
LO in this configuration is 0.3. The reference frequency is from
a 16 MHz TCXO from Fox, thus an R value of 2 is programmed.
Taking into account the high PFD frequency and its effect on
the band select logic, the band select clock divider is enabled. In
this case, a value of 8 is chosen. A very simple pull-up resistor
and dc blocking capacitor complete the RF output stage.
S
P
I
COM
P
ATIBLE
S
E
R
IAL BUS
ADF4360-1
V
VCO
V
VCO
FOX
801BE-160
16MHz
V
VCO
CPGND
AGND
DGND RF
OUT
B
RF
OUT
A
CP
1nF
3.3nF
15.0nF
51
51
51
100pF
100pF
1nF
1nF
10
F
4.7k
620
R
SET
C
C
LE
DATA
CLK
REF
IN
C
N
V
TUNE
DV
DD
AV
DD
CE MUXOUT
5
4
24
7
20
23
2
21
6
14
16
17
18
19
13
1
3
8
9
10 11 22
15
12
V
VDD
LOCK
DETECT
04414-
0-
023
Figure 17. Fixed Frequency LO
POWER-UP
After power-up, the part needs three writes for normal opera-
tion. The correct sequence is to the R counter latch, followed by
the control latch, and N counter latch.
INTERFACING
The ADF4360 family has a simple SPI compatible serial inter-
face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the appropriate register on each rising edge of CLK
will get transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means the maximum update rate possible is 833 kHz or one
update every 1.2 microseconds. This is certainly more than ade-
quate for systems that will have typical lock times in hundreds
of microseconds.
ADuC812 Interface
Figure 18 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three 8-
bit bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.
04414-0-024
ADuC812
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(Lock Detect)
SCLOCK
MOSI
I/O Ports
Figure 18. ADuC812 to ADF4360-x Interface
I/O port lines on the ADuC812 are also used to control power-
down (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the out-
put frequency can be changed is 166 kHz.
ADSP-2181 Interface
Figure 19 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate fram-
ing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.
04414-0-025
ADSP-21xx
ADF4360-x
SCLK
SDATA
LE
CE
MUXOUT
(Lock Detect)
SCLOCK
MOSI
TFS
I/O Ports
Figure 19. ADSP-21xx to ADF4360-x Interface
Set up the word length for 8 bits and use three memory loca-
tions for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
ADF4360-1
Rev. A | Page 20 of 24
PCB DESIGN GUIDELINES FOR CHIP-SCALE PACKAGE
The leads on the chip-scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package lead length and 0.05 mm wider than
the package lead width. The lead should be centered on the pad
to ensure that the solder joint size is maximized.
The bottom of the chip-scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short-
ing is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 ounce of
copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-1 for optimum operation; the most basic is to use a
50 resistor to V
VCO
. A dc bypass capacitor of 100 pF is con-
nected in series as shown Figure 20. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in the circuit below typically gives-6 dBm
output power into a 50 load.
100pF
04414-0-020
RF
OUT
V
VCO
50
51
Figure 20. Simple ADF4360-1 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to V
VCO.
This gives a better match and hence more
output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB addi-
tional rejection of the second harmonic. The shunt inductor
needs to be a relatively high value (>40 nH).
Experiments have shown that Figure 21 provides an excellent
match to 50 over the operating range of the ADF4360-1. This
gives approximately -4 dBm output power across the frequency
range of the ADF4360-1. Both single-ended architectures can be
examined using the EVAL_ADF4360-1EB1 evaluation board.
3.9nH
47nH
1.5pF
04414-0-021
RF
OUT
V
VCO
50
Figure 21. Optimum ADF4360-1 Output Stage
If the user does not need the differential outputs available on
the ADF4360, the user may either terminate the unused output
or combine both outputs using a balun. The circuit in Figure 22
shows how best to combine the outputs.
1nH
3.6nH
47nH
3.6nH
1.5pF
10pF
1.5pF
50
1nH
RF
OUT
A
V
VCO
RF
OUT
B
04414-0-022
Figure 22. Balun for Combining ADF4360-1 RF Outputs
The circuit in Figure 22 is a lumped lattice type LC balun. It is
designed for a center frequency of 2.2 GHz and outputs 1.0 dBm
at this frequency. The series 1 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by 90 and the second by -90, thus
combining the two. The action of the 3.6 nH inductor and the
1.5 pF capacitor accomplish this. The 47 nH is used to provide
an RF choke in order to feed the supply voltage, and the 10 pF
capacitor provides the necessary dc block. To ensure good RF
performance, the circuits in Figure 21 and Figure 22 were im-
plemented with Coilcraft 0402/0603 inductors and AVX 0402
thin-film capacitors.
Alternatively, instead of the LC balun shown above, both out-
puts may be combined using a 180 rat-race coupler.
ADF4360-1
Rev. A | Page 21 of 24
OUTLINE DIMENSIONS
1
24
6
7
13
19
18
12
2.25
2.10 SQ
1.95
0.60 MAX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 REF
0.50
BSC
12 MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR
TOP
VIEW
3.75
BSC SQ
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
COPLANARITY
0.08
0.20 REF
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 23. 24-Lead Lead Frame Chip-Scale Package [LFCSP]
(CP-24-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Frequency Range
Package Option
ADF4360-1BCP
-40C to +85C
2050 MHz to 2450 MHz
CP-24-1
ADF4360-1BCPRL
-40C to +85C
2050 MHz to 2450 MHz
CP-24-1
ADF4360-1BCPRL7
-40C to +85C
2050 MHz to 2450 MHz
CP-24-1
EVAL-ADF4360-1EB1
Evaluation
Board
ADF4360-1
Rev. A | Page 22 of 24
NOTES
ADF4360-1
Rev. A | Page 23 of 24
NOTES
ADF4360-1
Rev. A | Page 24 of 24
NOTES
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C Patent
Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
2004 Analog Devices, Inc. All rights reserved. Trademarks and
regis-
tered trademarks are the property of their respective owners.
C0441406/04(A)
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