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PIN CONNECTIONS
14-Lead Ceramic DIP (Y Suffix) and
14-Lead Plastic DIP (P Suffix)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OUT A
IN A
+IN A
V+
+IN B
IN B
OUT B
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
+
+
+
+
OP467
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Quad Precision, High-Speed
Operational Amplifier
OP467
FEATURES
High Slew Rate 170 V/ s
Wide Bandwidth 28 MHz
Fast Settling Time <200 ns to 0.01%
Low Offset Voltage <500 V
Unity-Gain Stable
Low Voltage Operation 5 V to 15 V
Low Supply Current <10 mA
Drives Capacitive Loads
APPLICATIONS
High-Speed Image Display Drivers
High Frequency Active Filters
Fast Instrumentation Amplifiers
High-Speed Detectors
Integrators
Photo Diode Preamps
GENERAL DESCRIPTION
The OP467 is a quad, high-speed, precision operational ampli-
fier. It offers the performance of a high-speed op amp combined
with the advantages of a precision operational amplifier all in a
single package. The OP467 is an ideal choice for applications
where, traditionally, more than one op amp was used to achieve
this level of speed and precision.
The OP467's internal compensation ensures stable unity-gain
operation, and it can drive large capacitive loads without oscilla-
tion. With a gain bandwidth product of 28 MHz driving a 30 pF
load, output slew rate in excess of 170 V/
s, and settling time
to 0.01% in less than 200 ns, the OP467 provides excellent
dynamic accuracy in high-speed data-acquisition systems. The
channel-to-channel separation is typically 60 dB at 10 MHz.
The dc performance of OP467 includes less than 0.5 mV of
offset, voltage noise density below 6 nV/
Hz and total supply
current under 10 mA. Common-mode rejection and power
supply rejection ratios are typically 85 dB. PSRR is maintained
to better than 40 dB with input frequencies as high as 1 MHz.
The low offset and drift plus high speed and low noise, make the
OP467 usable in applications such as high-speed detectors and
instrumentation.
The OP467 is specified for operation from
5 V to 15 V over
the extended industrial temperature range (40
C to +85C) and
is available in 14-lead plastic and ceramic DIP, plus 16-lead
SOIC and 20-terminal LCC surface mount packages.
Contact your local sales office for MIL-STD-883 data sheet
and availability.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2001
16-Lead SOIC
(S Suffix)
1
2
3
4
5
6
7
8
OUT A
IN A
+IN A
V+
+IN B
IN B
OUT B
16
15
14
13
12
11
10
9
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
NC
NC
OP467
NC = NO CONNECT
+IN
IN
OUT
V+
V
Figure 1. Simplified Schematic
20-Terminal LCC
(RC Suffix)
+IN D
V
+IN C
NC
NC
4
5
6
7
9
19
20
1
2
3
18
17
16
15
14
8
10 11 12 13
(TOP VIEW)
+IN A
V+
+IN B
NC
NC
OUT A
IN A
OUT D
IN D
NC
IN B
OUT B
IN C
OUT C
NC
OP467
NC = NO CONNECT
OP467SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
0.2
0.5
mV
40
C T
A
+85C
1
mV
Input Bias Current
I
B
V
CM
= 0 V
150
600
nA
V
CM
= 0 V, 40
C T
A
+85C
150
700
nA
Input Offset Current
I
OS
V
CM
= 0 V
10
100
nA
V
CM
= 0 V, 40
C T
A
+85C
10
150
nA
Common-Mode Rejection
CMR
V
CM
=
12 V
80
90
dB
CMR
V
CM
=
12 V, 40C T
A
+85C
80
88
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
83
86
dB
R
L
= 2 k
, 40C T
A
+85C
77.5
dB
Offset Voltage Drift
V
OS
/
T
3.5
V/C
Bias Current Drift
I
B
/
T
0.2
pA/
C
Long Term Offset Voltage Drift
V
OS
/
T
Note 1
750
V
OUTPUT CHARACTERISTICS
Output Voltage Swing
V
O
R
L
= 2 k
13.0
13.5
V
R
L
= 2 k
, 40C T
A
+85C
12.9
13.12
V
POWER SUPPLY
2
Power Supply Rejection Ratio
PSRR
4.5 V V
S
=
18 V
96
120
dB
40
C T
A
+85C
86
115
dB
Supply Current
I
SY
V
O
= 0 V
8
10
mA
V
O
= 0 V, 40
C T
A
+85C
13
mA
Supply Voltage Range
V
S
4.5
18
V
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBP
A
V
= +1, C
L
= 30 pF
28
MHz
Slew Rate
SR
V
IN
= 10 V Step, R
L
= 2 k
, C
L
= 30 pF
A
V
= +1
125
170
V/
s
A
V
= 1
350
V/
s
Full-Power Bandwidth
BW
V
IN
= 10 V Step
2.7
MHz
Settling Time
t
S
To 0.01%, V
IN
= 10 V Step
200
ns
Phase Margin
0
45
Degrees
Input Capacitance
Common Mode
2.0
pF
Differential
1.0
pF
NOISE PERFORMANCE
Voltage Noise
e
N
p-p
f = 0.1 Hz to 10 Hz
0.15
V p-p
Voltage Noise Density
e
N
f = 1 kHz
6
nV/
Hz
Current Noise Density
i
N
f = 1 kHz
8
pA/
Hz
NOTES
1
Long-Term Offset Voltage Drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125
C, with an LTPD of 1.3.
2
For proper operation the positive supply must be sequenced ON before the negative supply.
Specifications subject to change without notice.
REV. D
2
(@ V
S
= 15.0 V, T
A
= 25 C unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
INPUT CHARACTERISTICS
Offset Voltage
V
OS
0.3
0.5
mV
40
C T
A
+85C
1
mV
Input Bias Current
I
B
V
CM
= 0 V
125
600
nA
V
CM
= 0 V, 40
C T
A
+85C
150
700
nA
Input Offset Current
I
OS
V
CM
= 0 V
20
100
nA
V
CM
= 0 V, 40
C T
A
+85C
150
nA
Common-Mode Rejection
CMR
V
CM
=
2.0 V
76
85
dB
CMR
V
CM
=
2.0 V, 40C T
A
+85C
76
80
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
80
83
dB
R
L
= 2 k
, 40C T
A
+85C
74
dB
Offset Voltage Drift
V
OS
/
T
3 5
V/C
Bias Current Drift
I
B
/
T
0.2
pA/
C
OUTPUT CHARACTERISTICS
Output Voltage Swing
V
O
R
L
= 2 k
3.0
3.5
V
R
L
= 2 k
, 40C T
A
+85C
3.0
3.20
V
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
4.5 V V
S
=
5.5 V
92
107
dB
40
C T
A
+85C
83
105
dB
Supply Current
I
SY
V
O
= 0 V
8
10
mA
V
O
= 0 V, 40
C T
A
+85C
12
mA
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBP
A
V
= +1
22
MHz
Slew Rate
SR
V
IN
= 5 V Step, R
L
= 2 k
, C
L
= 39 pF
A
V
= +1
90
V/
s
A
V
= 1
90
V/
s
Full-Power Bandwidth
BW
V
IN
= 5 V Step
2.5
MHz
Settling Time
t
S
To 0.01%, V
IN
= 5 V Step
280
ns
Phase Margin
0
45
Degrees
NOISE PERFORMANCE
Voltage Noise
e
N
p-p
f = 0.1 Hz to 10 Hz
0.15
V p-p
Voltage Noise Density
e
N
f = 1 kHz
7
nV/
Hz
Current Noise Density
i
N
f = 1 kHz
8
pA/
Hz
Specifications subject to change without notice.
(@ V
S
= 5.0 V, T
A
= 25 C unless otherwise noted.)
OP467
REV. D
3
OP467
REV. D
4
WAFER TEST LIMITS
1
Parameter
Symbol
Conditions
Limit
Unit
Offset Voltage
V
OS
0.5
mV max
Input Bias Current
I
B
V
CM
= 0 V
600
nA max
Input Offset Current
I
OS
V
CM
= 0 V
100
nA max
Input Voltage Range
2
12
V min/max
Common-Mode Rejection Ratio
CMRR
V
CM
=
12 V
80
dB min
Power Supply Rejection Ratio
PSRR
V =
4.5 V to 18 V
96
dB min
Large Signal Voltage Gain
A
VO
R
L
= 2 k
83
dB min
Output Voltage Range
V
O
R
L
= 2 k
13.0
V min
Supply Current
I
SY
V
O
= 0 V, R
L
=
10
mA max
NOTES
1
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
2
Guaranteed by CMR test.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage
2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Input Voltage
3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Differential Input Voltage
3
. . . . . . . . . . . . . . . . . . . . . .
26 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . Limited
Storage Temperature Range
Y, RC Packages . . . . . . . . . . . . . . . . . . . . 65
C to +175C
P, S Packages . . . . . . . . . . . . . . . . . . . . . . 65
C to +150C
Operating Temperature Range
OP467A . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125C
OP467G . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85C
Junction Temperature Range
Y, RC Packages . . . . . . . . . . . . . . . . . . . . 65
C to +175C
P, S Packages . . . . . . . . . . . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300
C
Package Type
A
4
JC
Unit
14-Lead Cerdip (Y)
94
10
C/W
14-Lead Plastic DIP (P)
76
33
C/W
16-Lead SOIC (S)
88
23
C/W
20-Terminal LCC (RC)
78
33
C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
For proper operation the positive supply must be sequenced ON before the
negative supply.
3
For supply voltages less than
18 V, the absolute maximum input voltage is equal
to the supply voltage.
4
JA
is specified for the worst-case conditions, i.e.,
JA
is specified for device in socket
for cerdip, P-DIP, and LCC packages;
JA
is specified for device soldered in circuit
board for SOIC package.
ORDERING GUIDE
Temperature
Package
Package
Model
Ranges
Descriptions
Options
OP467ARC/883C 55
C to +125C 20-Terminal LCC
E-20A
OP467AY/883C
55
C to +125C 14-Lead Cerdip
Q-14
OP467GBC
DIE
OP467GP
40
C to +85C
14-Lead Plastic DIP N-14
OP467GS
40
C to +85C
16-Lead SOIC
R-16
OP467GS-REEL
40
C to +85C
16-Lead SOIC
R-16
DICE CHARACTERISTICS
OP467 Die Size 0.111 0.100 inch, 11,100 sq. mils Sub-
strate is Connected to V+, Number of Transistors 165
(@ V
S
= 15.0 V, T
A
= 25 C unless otherwise noted.)
OP467
REV. D
5
80
30
20
1k
10k
100M
10M
1M
100k
40
50
60
70
10
0
10
20
0
90
180
PHASE SHIFT
Degrees
OPEN-LOOP GAIN
dB
FREQUENCY Hz
GAIN
PHASE
V
S
= 15V
R
L
= 1M
C
L
= 30pF
TPC 1. Open-Loop Gain, Phase vs. Frequency
80
40
20
100k
100M
10M
1M
10k
20
0
60
FREQUENCY Hz
CLOSED-LOOP GAIN
dB
V
S
= 15V
T
A
= 25 C
TPC 2. Closed-Loop Gain vs. Frequency
25
0
20
15
5
5
10
0
20
15
10
SUPPLY VOLTAGE Volts
OPEN-LOOP GAIN
V/mV
T
A
= +125 C
T
A
= +25 C
T
A
= 55 C
TPC 3. Open-Loop Gain vs. Supply Voltage
Typical Performance Characteristics
100
60
0
1k
100k
10k
100
40
20
80
FREQUENCY Hz
IMPEDANCE
V
S
= 15V
T
A
= 25 C
1M
A
VCL
= +100
A
VCL
= +10
A
VCL
= +1
TPC 4. Closed-Loop Output Impedance vs. Frequency
0.0
100k
1M
10M
0.1
0.2
0.3
0.1
0.2
0.3
GAIN ERROR
dB
FREQUENCY Hz
3.4
5.8
V
S
= 5V
V
S
= 15V
TPC 5. Gain Linearity vs. Frequency
30
15
0
10k
10M
1M
100k
1k
10
5
20
25
FREQUENCY Hz
MAXIMUM OUTPUT SWING
Volts
A
VCL
= 1
A
VCL
= +1
V
S
= 15V
T
A
= 25 C
R
L
= 2k
TPC 6. Max V
OUT
Swing vs. Frequency
OP467
REV. D
6
12
6
0
10k
10M
1M
100k
1k
4
2
8
10
FREQUENCY Hz
MAXIMUM OUTPUT SWING
Volts
V
S
= 5V
T
A
= 25 C
R
L
= 2k
A
VCL
= 1
A
VCL
= +1
TPC 7. Max V
OUT
Swing vs. Frequency
120
60
0
10k
10M
1M
100k
1k
40
20
80
100
FREQUENCY Hz
COMMON-MODE REJECTION
Volts
V
S
= 15V
T
A
= 25 C
TPC 8. Common-Mode Rejection vs. Frequency
120
60
0
1k
1M
100k
10k
100
40
20
80
100
FREQUENCY Hz
POWER SUPPLY REJECTION
dB
V
S
= 15V
T
A
= 25 C
TPC 9. Power-Supply Rejection vs. Frequency
60
0
1600
30
10
200
20
0
50
40
1400
1000
800
600
1200
400
LOAD CAPACITANCE pF
OVERSHOOT
%
V
S
= 15V
R
L
= 2k
V
IN
= 100mV p-p
A
VCL
= +1
A
VCL
= 1
TPC 10. Small Signal Overshoot vs. Load Capacitance
60
0
1600
30
10
200
20
0
50
40
1400
1000
800
600
1200
400
LOAD CAPACITANCE pF
OVERSHOOT
%
V
S
= 5V
R
L
= 2k
V
IN
= 100mV p-p
A
VCL
= +1
A
VCL
= 1
TPC 11. Small Signal Overshoot vs. Load Capacitance
60
10
40
10k
100M
10M
1M
100k
20
30
40
50
30
20
10
0
GAIN
dB
FREQUENCY Hz
V
S
= 15V
10000pF
1000pF
500pF
200pF
C
IN
= NETWORK
ANALYZER
TPC 12. Noninverting Gain vs. Capacitive Loads
OP467
REV. D
7
0
50
100
1k
100M
10M
1M
100k
10k
40
30
20
10
90
80
70
60
FREQUENCY Hz
CHANNEL SEPARATION
dB
V
S
= 15V
100
TPC 13. Channel Separation vs. Frequency
12
6
0
100
1
1k
10
4
2
8
10
FREQUENCY Hz
INPUT CURRENT NOISE DENSITY
pA/ Hz
5V
V
S
15V
TPC 14. Input Current Noise Density vs. Frequency
100
10
1.0
0.1
1
10k
1k
100
10
FREQUENCY Hz
nV/ Hz
TPC 15. Voltage Noise Density vs. Frequency
500
2
0
0
1
1
2
400
300
200
100
TIME ns
V
OUT
ERROR
mV
V
S
= 15V
V
IN
= 5V
C
L
= 50pF
3
4
3
4
TPC 16. Settling Time, Negative Edge
500
2
0
0
1
1
2
400
300
200
100
TIME ns
V
OUT
ERROR
mV
V
S
= 15V
V
IN
= 5V
C
L
= 50pF
3
4
3
4
TPC 17. Settling Time, Positive Edge
20
20
5
0
0
5
5
10
15
15
10
20
10
15
SUPPLY VOLTAGE Volts
INPUT VOLTAGE RANGE
Volts
T
A
= 25 C
TPC 18. Input Voltage Range vs. Supply Voltage
OP467
REV. D
8
0
100k
100M
10M
1M
10k
10
20
10
GAIN
dB
FREQUENCY Hz
V
S1
= 15V
V
S2
= 5V
R
L
= 10k
C
L
= 50pF
V
S1
= 15V
V
S2
= 5V
20
30
40
50
30
40
50
TPC 19. Noninverting Gain vs. Supply Voltage
14
4
0
10
2
6
8
12
OUTPUT SWING
Volts
100
10k
1k
10
LOAD RESISTANCE
POSITIVE
SWING
NEGATIVE
SWING
V
S
= 15V
T
A
= 25 C
TPC 20. Output Swing vs. Load Resistance
2
0
5
1
3
4
OUTPUT SWING
Volts
100
10k
1k
10
LOAD RESISTANCE
POSITIVE
SWING
NEGATIVE
SWING
V
S
= 5V
T
A
= 25 C
TPC 21. Output Swing vs. Load Resistance
500
0
400
300
100
50
200
100
400
350
300
250
200
150
100
50
0
INPUT OFFSET VOLTAGE V
OS
V
UNITS
V
S
= 15V
T
A
= 25 C
1252 OP AMPS
TPC 22. Input Offset Voltage Distribution
500
0
400
300
100
50
200
100
400
350
300
250
200
150
100
50
0
INPUT OFFSET VOLTAGE V
OS
V
UNITS
V
S
= 5V
T
A
= 25 C
1252 OP AMPS
TPC 23. Input Offset Voltage Distribution
TC V
OS
V/ C
500
0
5.0
300
100
0.5
200
0
400
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
UNITS
V
S
= 15V
T
A
= 25 C
1252 OP AMPS
TPC 24. TC V
OS
Distribution
OP467
REV. D
9
TC V
OS
V/ C
500
0
5.0
300
100
0.5
200
0
400
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
UNITS
V
S
= 5V
T
A
= 25 C
1252 OP AMPS
TPC 25. TC V
OS
Distribution
60
40
75
125
55
45
50
50
75
100
50
25
0
25
29.0
27.0
28.5
27.5
28.0
TEMPERATURE C
PHASE MARGIN
Degrees
GAIN BANDWIDTH PRODUCT
MHz
GBW
M
V
S
= 15V
R
L
= 2k
TPC 26. Phase Margin and Gain Bandwidth vs.
Temperature
400
0
125
100
50
50
75
200
150
250
300
350
100
75
50
25
0
25
TEMPERATURE C
SLEW RATE
V/
s
+SR
SR
V
S
= 5V
R
L
= 2k
A
VCL
= 1
TPC 27. Slew Rate vs. Temperature
400
0
125
100
50
50
75
200
150
250
300
350
100
75
50
25
0
25
TEMPERATURE C
SLEW RATE
V/
s
SR
+SR
V
S
= 5V
R
L
= 2k
A
VCL
= +1
TPC 28. Slew Rate vs. Temperature
650
250
125
350
300
50
75
450
400
500
550
600
100
75
50
25
0
25
TEMPERATURE C
SLEW RATE
V/
s
V
S
= 15V
R
L
= 2k
A
VCL
= 1
+SR
SR
TPC 29. Slew Rate vs. Temperature
400
0
125
100
50
50
75
200
150
250
300
350
100
75
50
25
0
25
TEMPERATURE C
SLEW RATE
V/
s
V
S
= 15V
R
L
= 2k
A
VCL
= +1
+SR
SR
TPC 30. Slew Rate vs. Temperature
OP467
REV. D
10
10
10
400
4
8
100
6
0
2
2
0
4
6
8
300
200
5
1
4
2
3
1
5
0
2
3
4
SETTLING TIME ns
OUTPUT STEP FOR
15V SUPPLY
Volts
OUTPUT STEP FOR
5V SUPPLY
Volts
0.1%
0.01%
0.1%
0.01%
R
F
= 5k
T
A
= 25 C
TPC 31. Settling Time vs. Output Step
10
0
20
6
2
5
4
0
8
15
10
SUPPLY VOLTAGE Volts
SUPPLY CURRENT
mA
T
A
= +125 C
T
A
= +25 C
T
A
= 55 C
TPC 32. Supply Current vs. Supply Voltage
200
0
125
120
40
50
80
75
160
100
75
50
25
0
25
TEMPERATURE C
INPUT BIAS CURRENT
nA
V
S
= 15V
TPC 33. Input Bias Current vs. Temperature
25
0
125
15
5
50
10
75
20
100
75
50
25
0
25
TEMPERATURE C
INPUT OFFSET CURRENT
nA
V
S
= 15V
TPC 34. Input Offset Current vs. Temperature
OP467
REV. D
11
APPLICATIONS INFORMATION
OUTPUT SHORT-CIRCUIT PERFORMANCE
To achieve a wide bandwidth and high slew rate, the OP467
output is not short circuit protected. Shorting the output to
ground or to the supplies may destroy the device.
For safe operation, the output load current should be limited
so that the junction temperature does not exceed the absolute
maximum junction temperature.
To calculate the maximum internal power dissipation, the fol-
lowing formula can be used:
P
T
T
D
A
A
=
J
J
max
where T
J
and T
A
are junction and ambient temperatures respec-
tively, P
D
is device internal power dissipation, and
JA
is pack-
aged device thermal resistance given in the data sheet.
UNUSED AMPLIFIERS
It is recommended that any unused amplifiers in a quad package
be connected as a unity gain follower with a 1 k
feedback resistor
with noninverting input tied to the ground plain.
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Satisfactory performance of a high-speed op amp largely depends
on a good PC layout. To achieve the best dynamic performance,
following high frequency layout technique is recommended.
GROUNDING
A good ground plain is essential to achieve the optimum perfor-
mance in high-speed applications. It can significantly reduce the
undesirable effects of ground loops and IR drops by providing a
low impedance reference point. Best results are obtained with a
multilayer board design with one layer assigned to ground plain.
To maintain a continuous and low impedance ground, avoid
running any traces on this layer.
POWER SUPPLY CONSIDERATIONS
For proper operation the positive supply must be sequenced ON
before the negative supply. All users should take steps to ensure
this. In high frequency circuits, device lead length introduces an
inductance in series with the circuit. This inductance, combined
with stray capacitance, forms a high frequency resonance circuit.
Poles generated by these circuits will cause gain peaking and
additional phase shift, reducing the op amp's phase margin and
leading to an unstable operation.
A practical solution to this problem is to reduce the resonance
frequency low enough to take advantage of the amplifier's power
supply rejection.
This is easily done by placing capacitors across the supply line
and the ground plain as close as possible to the device pin. Since
capacitors also have internal parasitic components, such as stray
inductance, selecting the right capacitor is important. To be
effective, they should have low impedance over the frequency
range of interest. Tantalum capacitors are an excellent choice
for their high capacitance/size ratio, but their ESR (Effective
Series Resistance) increases with frequency making them less
effective. On the other hand, ceramic chip capacitors have excel-
lent ESR and ESL (Effective Series Inductance) performance at
higher frequencies, and because of their small size, they can be
placed very close to the device pin, further reducing the stray
inductance. Best results are achieved by using a combination of
these two capacitors. A 5
F10 F tantalum parallel with a
0.1
F ceramic chip caps are recommended. If additional isola-
tion from high frequency resonances of the power supply is
needed, a ferrite bead should be placed in series with the supply
lines between the bypass caps and the power supply. A word of
caution, addition of the ferrite bead will introduce a new pole
and zero to frequency response of the circuit and could cause
unstable operation if it is not selected properly.
+V
S
10 F TANTALUM
0.1 F CERAMIC CHIP
V
S
10 F TANTALUM
0.1 F CERAMIC CHIP
+
Figure 2. Recommended Power Supply Bypass
SIGNAL CONSIDERATIONS
Input and output traces need special attention to assure a mini-
mum stray capacitance. Input nodes are very sensitive to capaci-
tive reactance, particularly when connected to a high impedance
circuit. Stray capacitance can inject undesirable signals from a
noisy line into a high impedance input. Protect high impedance
input traces by providing guard traces around them. This will
also improve the channel separation significantly.
Additionally, any stray capacitance in parallel with the op amp's
input capacitance generates a pole in the frequency response of
the circuit. The additional phase shift caused by this pole will
reduce the circuit's gain margin. If this pole is within the gain
range of the op amp, it will cause unstable performance. To reduce
these undesirable effects, use the lowest impedance where pos-
sible. Lowering the impedance at this node places the poles at a
higher frequency, far above the gain range of the amplifier. Stray
capacitance on the PC board can be reduced by making the
traces narrow and as short as possible. Further reduction can be
realized by choosing smaller pad size, increasing the spacing
between the traces, and using PC board material with a low
dielectric constant insulator (Dielectric Constant of some com-
mon insulators: air = 1, Teflon
= 2.2, and FR4 = 4.7; with air
being an ideal insulator).
Removing segments of the ground plain directly under the input
and output pads is recommended.
Outputs of high-speed amplifiers are very sensitive to capacitive
loads. A capacitive load will introduce a pair of pole and zero to
the circuit's frequency response, reducing the phase margin,
leading to unstable operation or oscillation.
Teflon is a registered trademark of E.I. du Pont Co.
OP467
REV. D
12
Generally, it is a good design practice to isolate the amplifier's
output from any capacitive load by placing a resistor between
the amplifier's output and the rest of the circuits. A series resis-
tor of 10
to 100 is normally sufficient to isolate the output
from a capacitive load.
The OP467 is internally compensated to provide stable opera-
tion, and is capable of driving large capacitive loads without
oscillation.
Sockets are not recommended since they increase the lead
inductance/capacitance and reduce the power dissipation of the
package by increasing the leads' thermal resistance. If sockets
must be used, use Teflon or pin sockets with the shortest
possible leads.
PHASE REVERSAL
The OP467 is immune to phase reversal; its inputs can exceed
the supply rails by a diode drop without any phase reversal.
OUTPUT
INPUT
10
0%
100
90
200 s
10V
10V
V1
15.8V
Figure 3. No Phase Reversal (A
V
= +1)
SATURATION RECOVERY TIME
The OP467 has a fast and symmetrical recovery time from either
rail. This feature is very useful in applications such as high-speed
instrumentation and measurement circuits, where the amplifier
is frequently exposed to large signals that overload the amplifier.
10
0%
100
90
5V
DLY 9.842 s
20ns
5V
Figure 4. Saturation Recovery Time, Positive Rail
10
0%
100
90
5V
DLY 4.806 s
20ns
5V
Figure 5. Saturation Recovery Time, Negative Rail
HIGH-SPEED INSTRUMENTATION AMPLIFIER
The OP467 performance lends itself to a variety of high-speed
applications, including high-speed precision instrumentation
amplifiers. Figure 6 represents a circuit commonly used for data
acquisition, CCD imaging, and other high-speed applications.
Circuit gain is set by R
G
. A 2 k
resistor will set the circuit gain
to 2; for unity gain, remove R
G
. For any other gain settings use
the following formula:
G = 2/R
G
Resistor Value is in k
R
C
is used for adjusting the dc common-mode rejection, and C
C
is used for ac common-mode rejection adjustments.
OUTPUT
V
IN
+V
IN
1k
2k
1k
2k
10k
10k
5pF
1.9k
2k
C
C
R
G
R
C
200
10T
Figure 6. A High-Speed Instrumentation Amplifier
2.5mV
2.5mV
0.01% 10V STEP
V
S
= 15V
NEG SLOPE
Figure 7. Instrumentation Amplifier Settling Time to
0.01% for a 10 V Step Input (Negative Slope)
OP467
REV. D
13
2.5mV
2.5mV
0.01% 10V STEP
V
S
= 15V
POS SLOPE
Figure 8. Instrumentation Amplifier Settling Time to
0.01% for a 10 V Step Input (Positive Slope)
ERROR
TO
SCOPE
TO
INPUT
TO
IN-AMP
OUTPUT
2k
2k
AD9617
549
1k
61.9
+V
S
V
S
+
+
Figure 9. Settling Time Measurement Circuit
2 MHz BIQUAD BANDPASS FILTER
The circuit in Figure 10 is commonly used in medical imaging
ultrasound receivers. The 30 MHz bandwidth is sufficient to
accurately produce the 2 MHz center frequency, as the measured
response shows in Figure 11. When the op amp's bandwidth is
too close to the filter's center frequency, the amplifier's internal
phase shift causes excess phase shift at 2 MHz, which alters the
filter's response. In fact, if the chosen op amp has a bandwidth
close to 2 MHz, the combined phase shift of the three op amps
will cause the loop to oscillate.
Careful consideration must be given to the layout of this circuit
as with any other high-speed circuit.
If the phase shift introduced by the layout is large enough, it
could alter the circuit performance, or worse, it will oscillate.
2k
R1
3k
V
IN
R3
2k
R2
2k
R4
2k
R5
2k
C2
50pF
C1
50pF
R6
1k
V
OUT
+
+
+
+
1/4
OP467
1/4
OP467
1/4
OP467
1/4
OP467
Figure 10. 2 MHz Biquad Filter
20
100k
100M
10M
1M
10k
10
0
40
30
FREQUENCY Hz
GAIN
dB
Figure 11. Biquad Filter Response
OP467
REV. D
14
15
V
DD
V
REF
A
R
FB
A
I
OUT
1A
I
OUT
2A/
I
OUT
2B
I
OUT
1B
R
FB
B
V
REF
B
DGND
R
FB
C
I
OUT
1C
I
OUT
2C/
I
OUT
2D
V
REF
C
I
OUT
1D
R
FB
D
V
REF
D
DAC8408
+5V
+10V
+10V
V
OUT
A
V
OUT
B
0.1 F
+15V
15V
C2
10pF
C1
10pF
0.1 F
7
OP467
5
4
11
6
OP467
2
3
1
1
2
3
7
8
9
10
11
12
4
5
6
13
14
+
+10V
+10V
V
OUT
A
V
OUT
B
DIGITAL
CONTROL
SIGNALS
C3
10pF
C4
10pF
14
12
13
OP467
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
8
10
9
OP467
(MSB) DB7
DB6
28
27
26
22
21
20
19
18
17
25
24
23
16
+
+
+
R/
W
A/
B
DS1
DS2
Figure 12. Quad DAC Unipolar Operation
FAST I-TO-V CONVERTER
The fast slew rate and fast settling time of the OP467 are well
suited to the fast buffers and I-to-V converters used in variety of
applications. The circuit in Figure 12 is a unipolar quad D/A
converter consisting of only two ICs. The current output of the
DAC8408 is converted to a voltage by the OP467 configured as
an I-to-V converter. This circuit is capable of settling to 0.1%
within 200 ns. Figures 13 and 14 show the full-scale settling
time of the outputs. To obtain reliable circuit performance, keep
the traces from the DAC's I
OUT
to the inverting inputs of the
OP467 short to minimize parasitic capacitance.
10
0%
100
90
260.0ns
2V
50mV
100ns
Figure 13. Voltage Output Settling Time
10
0%
100
90
251.0ns
2V
50mV
100ns
Figure 14. Voltage Output Settling Time
R
FB
I
OUT
3pF
OP467
I-V
DAC-8408
1k
50
604
60.4
2k
DC OFFSET
2k
AD847
Figure 15. DAC V
OUT
Settling Time Circuit
OP467
REV. D
15
OP467 SPICE MACRO-MODEL
* Node assignments
noninverting input
inverting input
positive supply
negative supply
output
*
. SUBCKT OP467
1
2
99
50
27
*
* INPUT STAGE
*
I1
4
50
10E3
CIN
1
2
1E12
IOS
1
2
5E9
Q1
5
2
8 QN
Q2
6
7
9 QN
R3
99
5
185 . 681
R4
99
6
185 . 681
R5
8
4
180 . 508
R6
9
4
180 . 508
EOS
7
1
POLY (1) (14,20) 50E6
1
EREF
98
0
(20,0) 1
*
* GAIN STAGE AND DOMINANT POLE AT 1.5 kHz
*
R7
10
98
3 . 714E6
C2
10
98
28 . 571E12
G1
98
10
(5,6) 5 . 386E3
V1
99
11
1 . 6
V2
12
50
1 . 6
D1
10
11
DX
D2
12
10
DX
RC
10
28
1 . 4E3
CC
28
27
12E12
*
* COMMON-MODE STAGE WITH ZERO AT 1.26 kHz
*
ECM
13
98
POLY (2) (1,20)
(2,20) 0 0 . 5 0 . 5
R8
13
14
1E6
R9
14
98
25 . 119
C3
13
14
126 . 721E12
*
* POLE AT 400E6
*
R10
15
98
1E6
C4
15
98
0 . 398E15
G2
98
15
(10,20) 1E6
*
* OUTPUT STAGE
*
ISY
99
50
8 . 183E3
RMP1
99
20
96 . 429E3
RMP2
20
50
96 . 429E3
RO1
99
26
200
RO2
26
50
200
L1
26
27
1E7
GO1
26
99
(99,15) 5E3
GO2
50
26
(15,50) 5E3
G4
23
50
(15,26) 5E3
G5
24
50
(26,15) 5E3
V3
21
26
50
V4
26
22
50
D3
15
21
DX
D4
22
15
DX
D5
99
23
DX
D6
99
24
DX
D7
50
23
DY
D8
50
24
DY
*
* MODELS USED
*
. MODEL QN NPN (BF=33.333E3)
. MODEL DX D
. MODEL DY D (BV=50)
. ENDS OP467
G2
R10
C4
98
E
REF
I
SY
RMP2
RMP1
20
15
G4
D7
D5
D3
D4
G5
D8
D6
23
24
22
21
V3
V4
G01
R02
R01
G02
L1
99
50
26
15
99
50
27
+
+
+
Figure 16. SPICE Macro-Model Output Stage
I
OS
C
IN
I1
E
OS
R3
5
G1
99
50
99
50
N
N+
2
1
R4
6
R5
R6
4
7
C2
R7
10
98
12
V2
E
REF
R
C
28
C3
R8
E
CM
14
C
C
27
V1
11
13
D2
D1
R9
+
+
+
+
+
Q1
Q2
8
9
Figure 17. SPICE Macro-Model Input and Gain Stage
OP467
REV. D
16
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C00302c04/01(D)
PRINTED IN U.S.A.
14-Lead Plastic DIP (P Suffix)
(N-14)
14
1
7
8
PIN 1
0.795 (20.19)
0.725 (18.42)
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
16-Lead SOIC (S Suffix)
(R-16)
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050 (1.27)
BSC
16
9
8
1
0.4193 (10.65)
0.3937 (10.00)
0.2992 (7.60)
0.2914 (7.40)
PIN 1
0.4133 (10.50)
0.3977 (10.00)
0.0125 (0.32)
0.0091 (0.23)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
0.0500 (1.27)
0.0157 (0.40)
14-Lead Cerdip (Y Suffix)
(Q-14)
14
1
7
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.098 (2.49) MAX
0.100 (2.54) BSC
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
20-Terminal Leadless Ceramic Chip Carrier (RC Suffix)
(E-20A)
1
20
4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45 TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) BSC
0.200 (5.08)
BSC
0.150 (3.81)
BSC
0.075
(1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
OP467Revision History
Location
Page
Data Sheet changed from REV. C to REV. D.
Footnote added to POWER SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Footnote added to MAX RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to POWER SUPPLY CONSIDERATIONS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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