FEATURES

q 20MHz 16-bit Microcontroller compatible with industry

standard's MCS-96 ISA

- Register to Register Architecture

- 1000 Byte Register RAM

q Three 8-bit I/O Ports
q On-board Interrupt Controller
q Three Pulse-Width Modulated Outputs
q High Speed I/O
q UART Serial Port
q Dedicated Baud Rate Generator
q Software and Hardware Timers

- 16-Bit Watchdog Timer, Four 16-Bit Software Timers

- Three 16-Bit Counter/Timers

q Radiation-hardened process and design; total dose

irradiation testing to MIL-STD-883 Method 1019

- Total-dose: 100K rads(Si)
- Effective LET threshold: 25 MeV-cm

/mg

- Saturated cross section: 3.66e-7cm

/bit

- Latchup immune (LET > 128 MeV-cm

/mg)

q Error detection and correction for external memory accesses

q QML Q and QML V compliant part

q Standard Microcircuit Drawing 5962-98583

INTRODUCTION

The UT80CRH196KD is compatible with industry standard's

MCS-96 instruction set. The UT80CRH196KD is supported

by commercial hardware and software development tools.
Built on UTMC's Commercial RadHard

epitaxial CMOS

technology, the microcontroller is hardened against ionizing

dose and charged particles. The microcontroller's on-board

1000 byte scratch-pad SRAM and flip-flops can withstand
charged particles with energies up to 25 MeV-cm

/mg.

The UT80CRH196KD accesses instruction code and data via

a 16-bit address and data bus. The 16-bit bus allows the

microcontroller to access 128K bytes of instruction/data

memory. Integrated software and hardware timers, high speed

I/O, pulse width modulation circuitry, and UART make the

UT80CRH196KD ideal for control type applications. The

CPU's ALU supports byte and word adds and subtracts, 8 and

16 bit multiplies, 32/16 and 16/8 bit divides, as well as

increment, decrement, negate, compare, and logical

operations. The UT80CRH196KD's interrupt controller

prioritizes and vectors 18 interrupt events. Interrupts include

normal interrupts and special interrupts. To reduce power

consumption, the microcontroller supports software invoked

idle and power down modes. The UT80CRH196KD is

packaged in a 68-lead quad flatpack.

1000 Bytes

RAM

ALU

MicroCode

Engine

Interrupt

Controller

PTS

Memory

Controller

Queue

Watchdog

Timer

PWM

PORT2

Serial

Port

HSIO and

Timers

HSI HSO

Alternate

Functions

CPU

Alternate

Functions

PORT1

HOLD

HLDA

BREQ

PWM1
PWM2

Control
Signals

Address /Data Bus

Figure 1. UT80CRH196KD Microcontroller

PORT0

EXTINT

ECB0-

ECB5

Standard Products

UT80CRH196KD Microcontroller

Datasheet

September, 2002

1.0 SIGNAL DESCRIPTION

Port 0 (P0.0 - P0.7): Port 0 is an 8-bit input only port when used
in its default mode. When configured for their alternate function,

five of the bits are bi-directional EDAC check bits as shown in
Table 1.

Port 1 (P1.0 - P1.7): Port 1 is an 8-bit, quasi-bidirectional, I/O
port. All pins are quasi-bidirectional unless the alternate
function is selected per Table 2. When the pins are configured

for their alternate functions, they act as standard I/O, not quasi-
bidirectional.

Port 2 (P2.0 - P2.7): Port 2 is an 8-bit, multifunctional, I/O port.
These pins are shared with timer 2 functions, serial data I/O and
PWM0 output, per Table 3.

AD0-AD7: The lower 8-bits of the multiplexed address/data
bus. The pins on this port are bidirectional during the data phase

of the bus cycle.

AD8-AD15: The upper 8-bits of the multiplexed address/data

bus. The pins on this port are bidirectional during the data phase
of the 16-bit bus cycle. When running in 8-bit bus width, these
pins are non-multiplexed, dedicated upper address bit outputs.

HSI: Inputs to the High Speed Input Unit. Four HSI pins are
available: HSI.0, HSI.1, HSI.2, and HSI.3. Two of these pins
(HSI.2 and HSI.3) are shared with the HSO Unit. Two of these

pins (HSI.0 and HSI.1) have alternate functions for Timer 2.

HSO: Outputs from the High Speed Output Unit. Six HSO pins
are available: HSO.0, HSO.1, HSO.2, HSO.3, HSO.4, and
HSO.5. Pins HSO.4 and HSO.5 are shared with pins HSI.2 and

HSI.3 of the HSI Unit respectively.

Table 1. Port 0 Alternate Functions

Port Pin

Alternate

Name

Alternate Function

P0.0-P0.3,

P0.6

ECB0-ECB4 Error Detection & Correction

Check Bits

P0.4
P0.5

Input Port Pins

P0.7

EXTINT

Setting IOC1.1=1 will allow P0.7
to be used for EXTINT (INT07)

Table 2. Port 1 Alternate Functions

Port

Pin

Alternate

Name

Alternate Function

P1.0

I/O Pin

P1.1

I/O Pin

P1.2

I/O Pin

P1.3

PWM1

Setting IOC3.2=1 enables P1.3 as

the Pulse Width Modulator
(PWM1) output pin.

P1.4

PWM2

Setting IOC3.3=1 enables P1.4 as

the Pulse Width Modulator
(PWM2) output pin.

P1.5

BREQ

Bus Request, output activated

when the bus controller has a
pending external memory cycle.

P1.6

HLDA

Bus Hold Acknowledge, output

indicating the release of the bus.

P1.7

HOLD

Bus Hold, input requesting control
of the bus.

Table 3. Port 2 Alternate Functions

Port

Pin

Alternate

Name

Alternate Function

P2.0

TXD

Transmit Serial Data.

P2.1

RXD

Receive Serial Data.

P2.2

EXTINT

External interrupt. Clearing
IOC1.1 will allow P2.2 to be
used for EXTINT (INT07)

P2.3

T2CLK

Timer 2 clock input and Serial
port baud rate generator input.

P2.4

T2RST

Timer 2 Reset

P2.5

PWM0

Pulse Width Modulator
output 0

P2.6

T2UP-DN

Controls the direction of the

Timer 2 counter. Logic High
equals count down. Logic low
equals count up.

P2.7

T2CAPTURE

A rising edge on P2.7 causes
the value of Timer 2 to be
captured into this register, and
generates a Timer 2 Capture
interrupt (INT11).

1.1 Hardware Interface

1.1.1 Interfacing with External Memory
The UT80CRH196KD can interface with a variety of external

memory devices. It supports either a fixed 8-bit bus width or a
dynamic 8-bit/16-bit bus width, internal READY control for
slow external memory devices, a bus-hold protocol that enables

external devices to take over the bus, and several bus-control
modes. These features provide a great deal of flexibility when
interfacing with external memory devices.

1.1.1.1 Chip Configuration Register

The Chip Configuration Register (CCR) is used to initialize the
UT80CRH196KD immediately after reset. The CCR is fetched
from external address 2018H (Chip Configuration Byte) after

removal of the reset signal. The Chip Configuration Byte (CCB)
is read as either an 8-bit or 16-bit word depending on the value
of the BUSWIDTH pin. The composition of the bits in the CCR

are shown in Table 4.

There are 8 configuration bits available in the CCR. However,

bits 7 and 6 are not used by the UT80CRH196KD. Bits 5 and 4
comprise the READY mode control which define internal limits
for waitstates generated by the READY pin. Bit 3 controls the

definition of the ALE/ADV pin for system memory controls
while bit 2 selects between the different write modes. Bit 1
selects whether the UT80CRH196KD will use a dynamic 16-

bit bus or whether it will be locked in as an 8-bit bus. Finally,
Bit 0 enables the Power Down mode and allows the user to
disable this mode for protection against inadvertent power

downs.

1.1.1.2 Bus Width and Memory Configurations

The UT80CRH196KD external bus can operate as either an 8-
bit or 16-bit multiplexed address/data bus (see figure 2). The
value of bit 1 in the CCR determines the bus operation. A logic

low value on CCR.1 locks the bus controller in 8-bit bus mode.
If, however, CCR.1 is a logic high, then the BUSWIDTH signal
is used to decide the width of the bus. The bus is 16 bits wide

when the BUSWIDTH signal is high, and is 8 bits when the
BUSWIDTH signal is low.

1.1.2 Reset

To reset the UT80CRH196KD, hold the RESET pin low for at
least 16 state times after the power supply is within tolerance

and the oscillator has stabilized. Resets following the power-up
reset may be asserted for at least one state time, and the device
will turn on a pull-down transistor for 16 state times. This

enables the RESET signal to function as the system reset. The
reset state of the external I/O is shown in Table 9, and the register
reset values are shown in Table 8.

1.1.3 Instruction Set
The instruction set for the UT80CRH196KD is compatible with

the industry standard MCS-96 instruction set used on the
8XC196KD.

Notes:

1.The first instruction read following reset will be from location 2080h. All other external memory can be used as instruction a nd/or data memory.

Table 4. Chip Configuration Register

Bit

Function

N/A

IRC1 - Internal READY Mode Control

IRC0 - Internal READY Mode Control

Address Valid Strobe Select (ALE/ADV)

Write Strobe Mode Select (WR and BHE/WRL and WRH)

Dynamic Bus Width Enable

Enable Power Down Mode

Table 5. Memory Map

Memory Description

Begin

End

External Memory

02080H

0FFFFH

Reserved

0205EH

0207FH

PTS Vectors

02040H

0205DH

Upper Interrupt Vectors

02030H

0203FH

Reserved

02020H

0202FH

Reserved

02019H

0201FH

Chip Configuration Byte

02018H

Reserved

02014H

02017H

Lower Interrupt Vectors

02000H

02013H

External Memory

00400H

1FFFH

Internal Memory (RAM)

0001AH

003FFH

Special Function Registers

00000H

00019H

Table 6. Interrupt Vector Sources, Locations, and Priorities

Number

Interrupt Vector

Source(s)

Interrupt

Vector

Location

PTS

Vector

Location

Priority

(0 is the

Lowest

Priority)

Special

Unimplemented
Opcode

Unimplemented Opcode

2012h

N/A

Special

Software Trap

2010h

N/A

INT 15

NMI

203Eh

N/A

INT 14

HSI FIFO Full

203Ch

205Ch

INT 13

EXTINT 1

Port 2.2

203Ah

205Ah

INT 12

Timer 2 Overflow

2038h

2058h

INT 11

Timer 2 Capture

2036h

2056h

INT 10

HSI FIFO 4

HSI FIFO
Fourth Entry

2034h

2054h

INT 9

Receive

RI Flag

2032h

2052h

INT 8

Transmit

TI Flag

2030h

2050h

INT 7

EXTINT

Port 2.2 or Port 0.7

200Eh

204Eh

INT 6

Serial Port

RI Flag and
TI Flag

200Ch

204Ch

INT 5

Software Timer

Software Timer 0-3
Timer 2 Reset

200Ah

204Ah

INT 4

HSI.0

HSI.0 Pin

2008h

2048h

INT 3

High Speed
Outputs

Events on HSO.0 thru
HSO.5 Lines

2006h

2046h

INT 2

HSI Data Available

HSI FIFO Full or
HSI Holding Reg.
Loaded

2004h

2044h

INT 1

EDAC Bit Error

Single Bit Error
Single Bit Error OVF
Double Bit Error

2002h

2042h

INT 0

Timer Overflow

Timer 1 or Timer 2

2000h

2040h

All of the previous maskable interrupts can be assigned to the PTS.

Any PTS interrupt has priority over all other maskable interrupts.

Notes:
1.

The Unimplemented Opcode and Software Trap interrupts are not prioritized. The Interrupt Controller immediately services these interrupts when they are
asserted. NMI has the highest priority of all prioritized interrupts. Any PTS interrupt has priority over lower priority interru pts, and over all other maskable
interrupts. The standard maskable interrupts are serviced according to their priority number with INT0 has the lowest priority of all interrupts.

These interrupts can be configured to function as independent, external interrupts.

If the Serial interrupt is masked and the Receive and Transmit interrupts are enabled, the RI flag and TI flag generate separate Receive and Transmit inter-
rupts.

If the Receive and Transmit interrupts are masked and the Serial interrupt is enabled, both RI flag and TI flag generate a Serial Port interrupt.

Электронный компонент: 5962R9858301QXXC